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m ? 1997 microchip technology inc. december 1997 /ds33023a picmicro mid-range mcu family reference manual
m december 1997 /ds33023a ? 1997 microchip technology inc. internationally recognized quality system certi?ations microchips quality system embodies the requirements of iso9001:1994. our microchip chandler and tempe design and manufacturing facilities have been certi?d to iso 9001. the microchip kaohsiung test facility, and primary assembly houses have been certi?d to iso 9002. iso certi?ation plans are in-process for an esti- mated certi?ation grant by year-end 1997. in addition, microchip has received numerous customer certi?a- tions, including a delco issued certi?ate of compliance to aec-a100/qs9000. microchip received iso 9001 quality system certi?a- tion for its worldwide headquarters, design, and wafer fabrication facilities in january, 1997. our ?ld-pro- grammable picmicro 8-bit mcus, serial eeproms, related specialty memory products and development systems conform to the stringent quality standards of the international standard organization (iso). ?ll rights reserved. copyright ?1997, microchip technology incorporated, usa. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no rep- resentation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accu- racy or use of such information, or infringement of patents or other intellectual property rights arising from such use or oth- erwise. use of microchips products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. no licenses are conveyed, implicitly or otherwise, under any intellectual prop- erty rights. trademarks the microchip name, logo, pic, k ee l oq , picmaster, picstart, pro mate, and seeval are registered trademarks of microchip technology incorporated in the u.s.a. mplab, picmicro, icsp and in-circuit serial programming are trademarks of microchip technology incorporated. serialized quick-turn production is a service mark of micro- chip technology incorporated. all other trademarks mentioned herein are property of their respective companies.
? 1997 microchip technology inc. ds00097d-page iii m p a ge section 1. introduction 1-1 introduction .................................................................................................................. .....................................1-2 manual objective .............................................................................................................. ................................1-3 device structure .............................................................................................................. .................................1-4 development support ........................................................................................................... ............................1-6 device varieties .............................................................................................................. .................................1-7 style and symbol conventions .................................................................................................. ....................1-12 related documents ............................................................................................................. ...........................1-14 related application notes ..................................................................................................... .........................1-17 revision history .............................................................................................................. ...............................1-18 section 2. oscillator 2-1 introduction .................................................................................................................. .....................................2-2 oscillator configurations ..................................................................................................... .............................2-2 crystal oscillators / ceramic resonators ...................................................................................... ...................2-4 external rc oscillator ........................................................................................................ ............................2-12 internal 4 mhz rc oscillator .................................................................................................. ........................2-13 effects of sleep mode on the on-chip oscillator ............................................................................... .............2-17 effects of device reset on the on-chip oscillator ............................................................................. ............2-17 design tips ................................................................................................................... .................................2-18 related application notes ..................................................................................................... .........................2-19 revision history .............................................................................................................. ...............................2-20 section 3. reset 3-1 introduction .................................................................................................................. .....................................3-2 power-on reset (por), power-up timer (pwrt), oscillator start-up timer (ost), brown-out reset (bor), and parity error reset (per) ..............................3-4 registers and status bit values ............................................................................................... ......................3-10 design tips ................................................................................................................... .................................3-16 related application notes ..................................................................................................... .........................3-17 revision history .............................................................................................................. ...............................3-18 section 4. architecture 4-1 introduction .................................................................................................................. .....................................4-2 clocking scheme/instruction cycle ............................................................................................. .....................4-5 instruction flow/pipelining ................................................................................................... .............................4-6 i/o descriptions .............................................................................................................. ..................................4-7 design tips ................................................................................................................... .................................4-12 related application notes ..................................................................................................... .........................4-13 revision history .............................................................................................................. ...............................4-14 table of contents
ds00097d-page iv ? 1997 microchip technology inc. m p a ge section 5. cpu and alu 5-1 introduction .................................................................................................................. .....................................5-2 general instruction format .................................................................................................... ...........................5-4 central processing unit (cpu) ................................................................................................. ........................5-4 instruction clock ............................................................................................................. ..................................5-4 arithmetic logical unit (alu) ................................................................................................. ..........................5-5 status register ............................................................................................................... ..............................5-6 option_reg register ........................................................................................................... ........................5-8 pcon register ................................................................................................................. ................................5-9 design tips ................................................................................................................... .................................5-10 related application notes ..................................................................................................... .........................5-11 revision history .............................................................................................................. ...............................5-12 section 6. memory organization 6-1 introduction .................................................................................................................. .....................................6-2 program memory organization ................................................................................................... .....................6-2 data memory organization ...................................................................................................... ........................6-8 initialization ................................................................................................................ .....................................6-14 design tips ................................................................................................................... .................................6-16 related application notes ..................................................................................................... .........................6-17 revision history .............................................................................................................. ...............................6-18 section 7. data eeprom 7-1 introduction .................................................................................................................. .....................................7-2 control register .............................................................................................................. .................................7-3 eeadr ......................................................................................................................... ....................................7-4 eecon1 and eecon2 registers ................................................................................................... .................7-4 reading the eeprom data memory ................................................................................................ ...............7-5 writing to the eeprom data memory ............................................................................................. ................7-5 write verify .................................................................................................................. .....................................7-6 protection against spurious writes ............................................................................................ ......................7-7 data eeprom operation during code protected configuration ....................................................................7 -7 initialization ................................................................................................................ .......................................7-7 design tips ................................................................................................................... ...................................7-8 related application notes ..................................................................................................... ...........................7-9 revision history .............................................................................................................. ...............................7-10 section 8. interrupts 8-1 introduction .................................................................................................................. .....................................8-2 control registers ............................................................................................................. .................................8-5 interrupt latency ............................................................................................................. ...............................8-10 int and external interrupts ................................................................................................... .........................8-10 context saving during interrupts .............................................................................................. .....................8-11 initialization ................................................................................................................ .....................................8-14 design tips ................................................................................................................... .................................8-16 related application notes ..................................................................................................... .........................8-17 revision history .............................................................................................................. ...............................8-18 table of contents
? 1997 microchip technology inc. ds00097d-page v m p a ge section 9. i/o ports 9-1 introduction .................................................................................................................. .....................................9-2 porta and the trisa register .................................................................................................. ....................9-4 portb and the trisb register .................................................................................................. ....................9-6 portc and the trisc register .................................................................................................. ....................9-8 portd and the trisd register .................................................................................................. ....................9-9 porte and the trise register .................................................................................................. ..................9-10 portf and the trisf register .................................................................................................. ..................9-11 portg and the trisg register .................................................................................................. .................9-12 gpio and the trisgp register .................................................................................................. ...................9-13 i/o programming considerations ................................................................................................ ...................9-14 initialization ................................................................................................................ .....................................9-16 design tips ................................................................................................................... .................................9-17 related application notes ..................................................................................................... .........................9-19 revision history .............................................................................................................. ...............................9-20 section 10. parallel slave port 10-1 introduction .................................................................................................................. ...................................10-2 control register .............................................................................................................. ...............................10-3 operation ..................................................................................................................... ...................................10-4 operation in sleep mode ....................................................................................................... .........................10-5 effect of a reset ............................................................................................................. ................................10-5 psp waveforms ................................................................................................................. ............................10-5 design tips ................................................................................................................... .................................10-6 related application notes ..................................................................................................... .........................10-7 revision history .............................................................................................................. ...............................10-8 table of contents
ds00097d-page vi ? 1997 microchip technology inc. m p a ge section 11. timer0 11-1 introduction .................................................................................................................. ...................................11-2 control register .............................................................................................................. ...............................11-3 operation ..................................................................................................................... ...................................11-4 tmr0 interrupt ................................................................................................................ ...............................11-5 using timer0 with an external clock ........................................................................................... ..................11-6 tmr0 prescaler ................................................................................................................ .............................11-7 design tips ................................................................................................................... ...............................11-10 related application notes ..................................................................................................... .......................11-11 revision history .............................................................................................................. .............................11-12 section 12. timer1 12-1 introduction .................................................................................................................. ...................................12-2 control register .............................................................................................................. ...............................12-3 timer1 operation in timer mode ................................................................................................ ...................12-4 timer1 operation in synchronized counter mode ................................................................................. ........12-4 timer1 operation in asynchronous counter mode ................................................................................. .......12-5 timer1 oscillator ............................................................................................................. ...............................12-7 sleep operation ............................................................................................................... ..............................12-9 resetting timer1 using a ccp trigger output ................................................................................... ...........12-9 resetting of timer1 register pair (tmr1h:tmr1l) ............................................................................... .......12-9 timer1 prescaler .............................................................................................................. ..............................12-9 initialization ................................................................................................................ ...................................12-10 design tips ................................................................................................................... ...............................12-12 related application notes ..................................................................................................... .......................12-13 revision history .............................................................................................................. .............................12-14 section 13. timer2 13-1 introduction .................................................................................................................. ...................................13-2 control register .............................................................................................................. ...............................13-3 timer clock source ............................................................................................................ ............................13-4 timer (tmr2) and period (pr2) registers ....................................................................................... .............13-4 tmr2 match output ............................................................................................................. ..........................13-4 clearing the timer2 prescaler and postscaler .................................................................................. .............13-4 sleep operation ............................................................................................................... ..............................13-4 initialization ................................................................................................................ .....................................13-5 design tips ................................................................................................................... .................................13-6 related application notes ..................................................................................................... .........................13-7 revision history .............................................................................................................. ...............................13-8 section 14. compare/capture/pwm (ccp) 14-1 introduction .................................................................................................................. ...................................14-2 control register .............................................................................................................. ...............................14-3 capture mode .................................................................................................................. ...............................14-4 compare mode .................................................................................................................. .............................14-6 pwm mode ...................................................................................................................... ...............................14-8 initialization ................................................................................................................ ...................................14-12 design tips ................................................................................................................... ...............................14-15 related application notes ..................................................................................................... .......................14-17 revision history .............................................................................................................. .............................14-18 table of contents
? 1997 microchip technology inc. ds00097d-page vii m p a ge section 15. synchronous serial port (ssp) 15-1 introduction .................................................................................................................. ...................................15-2 control registers ............................................................................................................. ...............................15-3 spi mode ...................................................................................................................... ..................................15-6 ssp i 2 c operation ................................................................................................................... ....................15-16 initialization ................................................................................................................ ...................................15-26 design tips ................................................................................................................... ...............................15-28 related application notes ..................................................................................................... .......................15-29 revision history .............................................................................................................. .............................15-30 section 16. basic sychronous serial port (bssp) 16-1 introduction .................................................................................................................. ...................................16-2 control registers ............................................................................................................. ...............................16-3 spi mode ...................................................................................................................... ..................................16-6 ssp i 2 c operation ................................................................................................................... ....................16-15 initialization ................................................................................................................ ...................................16-23 design tips ................................................................................................................... ...............................16-24 related application notes ..................................................................................................... .......................16-25 revision history .............................................................................................................. .............................16-26 section 17. master synchronous serial port (mssp) 17-1 introduction .................................................................................................................. ...................................17-2 control register .............................................................................................................. ...............................17-4 spi mode ...................................................................................................................... ..................................17-9 ssp i 2 c operation .................................................................................................................. ..................17-18 connection considerations for i 2 c bus ........................................................................................................17-56 initialization ................................................................................................................ ...................................17-57 design tips ................................................................................................................... ...............................17-58 related application notes ..................................................................................................... .......................17-59 revision history .............................................................................................................. .............................17-60 section 18. usart 18-1 introduction .................................................................................................................. ...................................18-2 control registers ............................................................................................................. ...............................18-3 usart baud rate generator (brg) ............................................................................................... ..............18-5 usart asynchronous mode ....................................................................................................... ..................18-8 usart synchronous master mode ................................................................................................. ............18-15 usart synchronous slave mode .................................................................................................. .............18-19 initialization ................................................................................................................ ...................................18-21 design tips ................................................................................................................... ...............................18-22 related application notes ..................................................................................................... .......................18-23 revision history .............................................................................................................. .............................18-24 table of contents
ds00097d-page viii ? 1997 microchip technology inc. m p a ge section 19. voltage reference 19-1 introduction .................................................................................................................. ...................................19-2 control register .............................................................................................................. ...............................19-3 configuring the voltage reference ............................................................................................. ...................19-4 voltage reference accuracy/error .............................................................................................. ...................19-5 operation during sleep ........................................................................................................ ..........................19-5 effects of a reset ............................................................................................................ ...............................19-5 connection considerations ..................................................................................................... .......................19-6 initialization ................................................................................................................ .....................................19-7 design tips ................................................................................................................... .................................19-8 related application notes ..................................................................................................... .........................19-9 revision history .............................................................................................................. .............................19-10 section 20. comparator 20-1 introduction .................................................................................................................. ...................................20-2 control register .............................................................................................................. ...............................20-3 comparator configuration ...................................................................................................... ........................20-4 comparator operation .......................................................................................................... ..........................20-6 comparator reference .......................................................................................................... .........................20-6 comparator response time ...................................................................................................... ....................20-8 comparator outputs ............................................................................................................ ...........................20-8 comparator interrupts ......................................................................................................... ...........................20-9 comparator operation during sleep ............................................................................................. ..............20-9 effects of a reset ............................................................................................................ ............................20-9 analog input connection considerations ........................................................................................ .............20-10 initialization ................................................................................................................ ...................................20-11 design tips ................................................................................................................... ...............................20-12 related application notes ..................................................................................................... .......................20-13 revision history .............................................................................................................. .............................20-14 section 21. 8-bit a/d converter 21-1 introduction .................................................................................................................. ...................................21-2 control registers ............................................................................................................. ...............................21-3 operation ..................................................................................................................... ...................................21-5 a/d acquisition requirements .................................................................................................. ......................21-6 selecting the a/d conversion clock ............................................................................................ ..................21-8 configuring analog port pins .................................................................................................. .......................21-9 a/d conversions ............................................................................................................... ...........................21-10 a/d operation during sleep .................................................................................................... .....................21-12 a/d accuracy/error ............................................................................................................ ...........................21-13 effects of a reset ............................................................................................................ ..........................21-13 use of the ccp trigger ........................................................................................................ ........................21-14 connection considerations ..................................................................................................... .....................21-14 transfer function ............................................................................................................. ............................21-14 initialization ................................................................................................................ ...................................21-15 design tips ................................................................................................................... ...............................21-16 related application notes ..................................................................................................... .......................21-17 revision history .............................................................................................................. .............................21-18 table of contents
? 1997 microchip technology inc. ds00097d-page ix m p a ge section 22. basic 8-bit a/d converter 22-1 introduction .................................................................................................................. ...................................22-2 control registers ............................................................................................................. ...............................22-3 a/d acquisition requirements .................................................................................................. ......................22-6 selecting the a/d conversion clock ............................................................................................ ..................22-8 configuring analog port pins .................................................................................................. .....................22-10 a/d conversions ............................................................................................................... ...........................22-11 a/d operation during sleep .................................................................................................... .....................22-14 a/d accuracy/error ............................................................................................................ ...........................22-15 effects of a reset ............................................................................................................ ..........................22-16 connection considerations ..................................................................................................... .....................22-16 transfer function ............................................................................................................. ............................22-16 initialization ................................................................................................................ ...................................22-17 design tips ................................................................................................................... ...............................22-18 related application notes ..................................................................................................... .......................22-19 revision history .............................................................................................................. .............................22-20 section 23. 10-bit a/d converter 23-1 introduction .................................................................................................................. ...................................23-2 control register .............................................................................................................. ...............................23-3 operation ..................................................................................................................... ...................................23-5 a/d acquisition requirements .................................................................................................. ......................23-6 selecting the a/d conversion clock ............................................................................................ ..................23-8 configuring analog port pins .................................................................................................. .......................23-9 a/d conversions ............................................................................................................... ...........................23-10 operation during sleep ........................................................................................................ ........................23-14 effects of a reset ............................................................................................................ .............................23-14 a/d accuracy/error ............................................................................................................ ...........................23-15 connection considerations ..................................................................................................... .....................23-16 transfer function ............................................................................................................. ............................23-16 initialization ................................................................................................................ ...................................23-17 design tips ................................................................................................................... ...............................23-18 related application notes ..................................................................................................... .......................23-19 revision history .............................................................................................................. .............................23-20 section 24. slope a/d 24-1 introduction .................................................................................................................. ...................................24-2 control registers ............................................................................................................. ...............................24-3 conversion process ............................................................................................................ ...........................24-6 other analog modules .......................................................................................................... ........................24-12 calibration parameters ........................................................................................................ .........................24-13 design tips ................................................................................................................... ...............................24-14 related application notes ..................................................................................................... .......................24-15 revision history .............................................................................................................. .............................24-16 table of contents
ds00097d-page x ? 1997 microchip technology inc. m p a ge section 25. lcd 25-1 introduction .................................................................................................................. ...................................25-2 control register .............................................................................................................. ...............................25-3 lcd timing .................................................................................................................... ................................25-6 lcd interrupts ................................................................................................................ ..............................25-12 pixel control ................................................................................................................. ................................25-13 voltage generation ............................................................................................................ ..........................25-15 operation during sleep ........................................................................................................ ........................25-16 effects of a reset ............................................................................................................ .............................25-17 configuring the lcd module .................................................................................................... ....................25-17 discrimination ratio .......................................................................................................... ...........................25-18 lcd voltage generation ........................................................................................................ ......................25-20 contrast ...................................................................................................................... ..................................25-22 lcd glass ..................................................................................................................... ...............................25-22 initialization ................................................................................................................ ...................................25-23 design tips ................................................................................................................... ...............................25-24 related application notes ..................................................................................................... .......................25-25 revision history .............................................................................................................. .............................25-26 section 26. watchdog timer and sleep mode 26-1 introduction .................................................................................................................. ...................................26-2 control register .............................................................................................................. ...............................26-3 watchdog timer (wdt) operation ................................................................................................ .................26-4 sleep (power-down) mode ....................................................................................................... ...................26-7 initialization ................................................................................................................ .....................................26-9 design tips ................................................................................................................... ...............................26-10 related application notes ..................................................................................................... .......................26-11 revision history .............................................................................................................. .............................26-12 section 27. device configuration bits 27-1 introduction .................................................................................................................. ...................................27-2 configuration word bits ....................................................................................................... ..........................27-4 program verification/code protection .......................................................................................... ..................27-8 id locations .................................................................................................................. .................................27-9 design tips ................................................................................................................... ...............................27-10 related application notes ..................................................................................................... .......................27-11 revision history .............................................................................................................. .............................27-12 section 28. in-circuit serial programming 28-1 introduction .................................................................................................................. ...................................28-2 entering in-circuit serial programming mode ................................................................................... .............28-3 application circuit ........................................................................................................... ................................28-4 programmer .................................................................................................................... ...............................28-6 programming environment ....................................................................................................... ......................28-6 other benefits ................................................................................................................ ................................28-7 field programming of picmicro otp mcus ........................................................................................ ..........28-8 field programming of flash picmicros .......................................................................................... ...........28-10 design tips ................................................................................................................... ...............................28-12 related application notes ..................................................................................................... .......................28-13 revision history .............................................................................................................. .............................28-14 table of contents
? 1997 microchip technology inc. ds00097d-page xi m p a ge section 29. instruction set 29-1 introduction .................................................................................................................. ...................................29-2 instruction formats ........................................................................................................... ..............................29-4 special function registers as source/destination .............................................................................. ..........29-6 q cycle activity .............................................................................................................. ................................29-7 instruction descriptions ...................................................................................................... ............................29-8 design tips ................................................................................................................... ...............................29-45 related application notes ..................................................................................................... .......................29-47 revision history .............................................................................................................. .............................29-48 section 30. electrical specifications 30-1 introduction .................................................................................................................. ...................................30-2 absolute maximums ............................................................................................................. ..........................30-3 device selection table ........................................................................................................ ...........................30-4 device voltage specifications ................................................................................................. .......................30-5 device current specifications ................................................................................................. .......................30-6 input threshold levels ........................................................................................................ ...........................30-9 i/o current specifications .................................................................................................... ........................30-10 output drive levels ........................................................................................................... ...........................30-11 i/o capacitive loading ........................................................................................................ .........................30-12 data eeprom / flash ........................................................................................................... ......................30-13 lcd ........................................................................................................................... ...................................30-14 comparators and voltage reference ............................................................................................. ..............30-15 timing parameter symbology .................................................................................................... ..................30-16 example external clock timing waveforms and requirements ..................................................................30-1 7 example power-up and reset timing waveforms and requirements ........................................................30-19 example timer0 and timer1 timing waveforms and requirements ...........................................................30-20 example ccp timing waveforms and requirements ................................................................................. 30-21 example parallel slave port (psp) timing waveforms and requirements .................................................30-22 example ssp and master ssp spi mode timing waveforms and requirements ......................................30-23 example ssp i 2 c mode timing waveforms and requirements ..................................................................30-27 example master ssp i 2 c mode timing waveforms and requirements ......................................................30-30 example usart/sci timing waveforms and requirements ......................................................................30-32 example 8-bit a/d timing waveforms and requirements ........................................................................... 30-34 example 10-bit a/d timing waveforms and requirements .........................................................................3 0-36 example slope a/d timing waveforms and requirements .........................................................................30 -38 example lcd timing waveforms and requirements ................................................................................. .30-40 related application notes ..................................................................................................... .......................30-41 revision history .............................................................................................................. .............................30-42 section 31. device characteristics 31-1 introduction .................................................................................................................. ...................................31-2 characterization vs. electrical specification ................................................................................. ..................31-2 dc and ac characteristics graphs and tables ................................................................................... ..........31-2 revision history .............................................................................................................. .............................31-22 table of contents
ds00097d-page xii ? 1997 microchip technology inc. m p a ge section 32. development tools 32-1 introduction .................................................................................................................. ...................................32-2 the integrated development environment (ide) .................................................................................. .........32-3 mplab software language support ............................................................................................... ..............32-6 mplab-sim simulator software .................................................................................................. ..................32-8 mplab emulator hardware support ............................................................................................... ...............32-9 mplab programmer support ...................................................................................................... .................32-10 supplemental tools ............................................................................................................ ..........................32-11 development boards ............................................................................................................ ........................32-12 development tools for other microchip products ................................................................................ ........32-14 related application notes ..................................................................................................... .......................32-15 revision history .............................................................................................................. .............................32-16 section 33. code development 33-1 revision history .............................................................................................................. ...............................33-2 section 34. appendix 34-1 i 2 c ? overview ..................................................................................................................... ..........................34-2 list of lcd glass manufacturers ................................................................................................ ................. 34-11 device enhancement ............................................................................................................ .......................34-13 revision history ............................................................................................................... ............................ 34-19 section 35. glossary 35-1 revision history .............................................................................................................. .............................35-14 table of contents
1997 microchip technology inc. ds31001a page 1-1 introduction 1 m section 1. introduction highlights this section of the manual contains the following major topics: 1.1 introduction ................................................................................................................ ....1-2 1.2 manual objective ...........................................................................................................1 -3 1.3 device structure ............................................................................................................ 1-4 1.4 development support ....................................................................................................1-6 1.5 device varieties............................................................................................................ ..1-7 1.6 style and symbol conventions ....................................................................................1-12 1.7 related documents .....................................................................................................1-14 1.8 related application notes............................................................................................1-17 1.9 revision history ...........................................................................................................1 -18
picmicro mid-range mcu family ds31001a-page 1-2 1997 microchip technology inc. 1.1 introduction microchip is the embedded control solutions company a . the companys focus is on products that meet the needs of the embedded control market. we are a leading supplier of: 8-bit general purpose microcontrollers (picmicro mcus) speciality and standard non-volatile memory devices security devices (k ee l oq ) application speci? standard products please request a microchip product line card for a listing of all the interesting products that we have to offer. this literature can be obtained from your local sales of?e, or downloaded from the microchip web site (www.microchip.com). in the past, 8-bit mcu users were ?ed on the traditional mcu model for production, a rom device was required. microchip has been the leader in changing this perception by showing that otp devices can give a better lifetime product cost compared to rom versions. microchip has a strength is in eprom technology. that made it the memory technology of choice for the picmicro mcus program memory. microchip has minimized the cost difference between eprom and rom memory technology, and therefore microchip can pass these bene?s onto our customers. this is not true for other mcu vendors, and is seen in the price difference between their eprom and rom versions. the growth of microchips 8-bit mcu market share is a testament to the picmicro mcus ability to meet the needs of many. this growth has made the picmicro architecture one of the top three architectures available in the general market today. this growth was fueled by the microchip vision of the bene?s of a low cost otp solution. some of the bene?s for the customer include: quick time to market allows code changes to product, during production run no non-recurring engineering (nre) charges for mask revisions ability to easily serialize the product ability to store calibration data, without additional hardware better able to maximize picmicro mcu inventory less risk, since the same device is used for development as well as for production. microchips picmicro 8-bit mcus offer a price/performance ratio that allows them to be considered for any traditional 8-bit mcu application as well as some traditional 4-bit applications (base-line family), dedicated logic replacement and low-end dsp applications (high-end family). these fea- tures and price-performance mix make picmicro mcus an attractive solution for most applications.
1997 microchip technology inc. ds31001a-page 1-3 section 1. introduction introduction 1 1.2 manual objective picmicro devices are grouped by the size of their instruction word. the three current picmicro families are: 1. base-line: 12-bit instruction word length 2. mid-range: 14-bit instruction word length 3. high-end: 16-bit instruction word length this manual focuses on the mid-range devices, which are also referred to as the pic16cxxx mcu family. the operation of the pic16cxxx mcu family architecture and peripheral modules is explained, but does not cover the speci?s of each device. therefore, it is not intended to replace the device data sheets, but complement them. in other words, this guide supplies the general details and operation of the picmicro architecture and peripheral modules, while the data sheet s give spe- ci? details such as device memory mapping. initialization examples are given throughout this manual. these examples sometimes need to be written as device speci? as opposed to family generic, though they are valid for most other devices. some modi?ations may be required for devices with variations in register ?e mappings. note: the ?st few mid-range devices have minor device variations when compared to this general description. we have tried to describe these variations throughout this manual. please refer to the speci? device data sheet for complete information on the device.
picmicro mid-range mcu family ds31001a-page 1-4 1997 microchip technology inc. 1.3 device structure each part of a device can be placed into one of three groups: 1. core 2. peripherals 3. special features 1.3.1 the core the core pertains to the basic features that are required to make the device operate. these include: 1. device oscillator revision ?s31002a 2. reset logic revision ?s31003a 3. cpu (central processing unit) operation revision ?s31005a 4. alu (arithmetic logical unit) operation revision ?s31005a 5. device memory map organization revision ?s31006a 6. interrupt operation revision ?s31008a 7. instruction set revision ?s31029a 1.3.2 peripherals peripherals are the features that add a differentiation from a microprocessor. these ease in inter- facing to the external world (such as general purpose i/o, lcd drivers, a/d inputs, and pwm outputs), and internal tasks such as keeping different time bases (such as timers). the peripher- als that are discussed are: 1. general purpose i/o revision ?s31009a 2. timer0 revision ?s31011a 3. timer1 revision ?s31012a 4. timer2 revision ?s31013a 5. capture, compare, and pwm (ccp) revision ?s31014a 6. synchronous serial port (ssp) revision ?s31015a 7. basic synchronous serial port (ssp) revision ?s31016a 8. master synchronous serial port (mssp) revision ?s31017a 9. usart (sci) revision ?s31018a 10. voltage references revision ?s31019a 11. comparators revision ?s31020a 12. 8-bit analog to digital (a/d) revision ?s31021a 13. basic 8-bit analog to digital (a/d) revision ?s31022a 14. 10-bit analog to digital (a/d) revision ?s31023a 15. slope analog to digital (a/d) w/ thermister revision ?s31024a 16. liquid crystal display (lcd) drivers revision ?s31025a 17. parallel slave port (psp) revision ?s31010a
1997 microchip technology inc. ds31001a-page 1-5 section 1. introduction introduction 1 1.3.3 special features special features are the unique features that help to do one or more of the following things: decrease system cost increase system reliability increase design ?xibility the mid-range picmicro mcus offer several features that help achieve these goals. the special features discussed are: 1. device con?uration bits revision ?s31027a 2. on-chip power-on reset (por) revision ?s31003a 3. brown-out reset (bor) logic revision ?s31003a 4. watchdog timer revision ?s31026a 5. low power mode (sleep) revision ?s31026a 6. internal rc device oscillator revision ?s31002a 7. in-circuit serial programming (icsp) revision ?s31028a
picmicro mid-range mcu family ds31001a-page 1-6 1997 microchip technology inc. 1.4 development support microchip offers a wide range of development tools that allow users to ef?iently develop and debug application code. microchips development tools can be broken down into four categories: 1. code generation 2. software debug 3. device programmer 4. product evaluation boards all tools developed by microchip operate under the mplab integrated development environ- ment (ide), while some third party tools may not. the code generation tools include: mpasm mplab-c mp-driveway these software development programs include device header ?es. each header ?e de?es the register names (as shown in the device data sheet) to the speci?d address or bit location. using the header ?es eases code migration, and reduces the tediousness of memorizing a registers address or a bits position in a register. tools which ease in debugging software are: picmaster in-circuit emulator icepic in-circuit emulator mplab-sim software simulator after generating and debugging the application software, the device will need to be programmed. microchip offers two levels of programmers: 1. picstart a plus programmer 2. promate a ii programmer demonstration boards allow the developer of software code to evaluate the capability and suit- ability of the device to the application. the demo boards offered are: picdem-1 picdem-2 picdem-3 picdem-14a a full description of each of microchips development tools is discussed in the ?evelopment tools section. as new tools are developed, product briefs and user guides may be obtained from the microchip web site (www.microchip.com) or from your local microchip sales of?e. code development recommendations and techniques are provided in the ?ode development section. microchip offers other reference tools to speed the development cycle. these include: application notes reference designs microchip web site microchip bbs local sales of?es with field application support corporate support line additional avenues of assistance can be found in many web user groups including the mit re?ctor piclist. the microchip web site lists other sites that may be useful references. note: microchip strongly recommends that the supplied header ?es be used in the source code of your program. this eases code migration as well as increases the quality and depth of the technical support that microchip can offer.
1997 microchip technology inc. ds31001a-page 1-7 section 1. introduction introduction 1 1.5 device varieties once the functional requirements of the device are speci?d, some other decisions need to be made. these include: memory technology operating voltage operating temperature range operating frequency packaging microchip has a large number of options and option combinations, one of which should ful?l your requirements. 1.5.1 memory varieties memory technology has no effect on the logical operation of a device. due to the different pro- cessing steps required, some electrical characteristics may vary between devices with the same feature set/pinout but with different memory technologies. an example is the electrical character- istic v il (input low voltage), which may have some difference between a typical eprom device and a typical rom device. each device has a variety of frequency ranges and packaging options available. depending on application and production requirements, the proper device options can be identi?d using the information in the product selection system section at the end of each data sheet. when placing orders, please use the ?roduct identi?ation system at the back of the data sheet to specify the correct part number. when discussing the functionality of the device, the memory technology and the voltage range do not matter. microchip offers three program memory types. the memory type is designated in the part number by the ?st letter(s) after the family af?iation designators. 1. c , as in pic16 c xxx. these devices have eprom type memory. 2. cr , as in pic16 cr xxx. these devices have rom type memory. 3. f , as in pic16 f xxx. these devices have flash type memory. 1.5.1.1 eprom microchip focuses on erasable programmable read only memory (eprom) technology to give the customers ?xibility throughout their entire design cycle. with this technology microchip offers various packaging options as well as services. 1.5.1.2 read only memory (rom) devices microchip offers a masked read only memory (rom) version of several of the highest volume parts, thus giving customers a lower cost option for high volume, mature products. rom devices do not allow serialization information in the program memory space. for information on submitting rom code, please contact your local microchip sales of?e. 1.5.1.3 flash memory devices these devices are electrically erasable, and can therefore be offered in a low cost plastic pack- age. being electrically erasable, these devices can be both erased and reprogrammed without removal from the circuit. a device will have the same speci?ations whether it is used for proto- type development, pilot programs, or production.
picmicro mid-range mcu family ds31001a-page 1-8 1997 microchip technology inc. 1.5.2 operating voltage range options all mid-range picmicro mcus operate over the standard voltage range. devices are also offered which operate over an extended voltage range (and reduced frequency range). table 1-1 shows all possible memory types and voltage range designators for the pic16cxxx mcu family. the designators are in bold typeface. table 1-1: device memory type and voltage range designators as you can see in table 1-2 , microchip speci?ations its extended range devices at a more con- servative voltage range until device characterization has ensured they will be able to meet the goal of their ?al design speci?ations. table 1-2: typical voltage ranges for each device type memory type voltage range standard extended eprom pic16 c xxx pic16 lc xxx rom pic16 cr xxx pic16 lcr xxx flash pic16 f xxx pic16 lf xxx note:not all memory types may be available for a particular device. typical voltage range (1) eprom rom flash standard c 4.5 - 6.0v cr 4.5 - 6.0v f 4.5 - 6.0v extended before device characterization lc 3.0 - 6.0v lcr 3.0 - 6.0v lf 3.0 - 6.0v final speci?ation (2) lc 2.5 - 6.0v lcr 2.5 - 6.0v lf 2.0 - 6.0v note 1: devices fabricated in microchips 120k process technology will have a maximum limit on v dd of 5.5v. new device data sheets will specify microchips technology designation 2: this voltage range depends on the results of device characterization.
1997 microchip technology inc. ds31001a-page 1-9 section 1. introduction introduction 1 1.5.3 packaging varieties depending on the development phase of your project, one of three package types would be used: the ?st is a device with an erasure window. typically these are found in packages with a ceramic body. these devices are used for the development phase, since the devices program memory can be erased and reprogrammed many times. the second package type is a low cost plastic package. this package type is used in production where device cost is to be kept to a minimum. lastly, there is the die option. a die is an unpackaged device that has been tested. dies are used in low cost designs and designs where board space is at a minimum. table 1-3 shows a quick summary of this. table 1-3: typical package uses package type typical usage windowed development mode plastic production die special applications, such as those which require minimum board space
picmicro mid-range mcu family ds31001a-page 1-10 1997 microchip technology inc. 1.5.3.4 uv erasable devices the uv erasable version of eprom program memory devices is optimal for prototype develop- ment and pilot programs. these devices can be erased and reprogrammed to any of the con?uration modes. third party programmers are also available; refer to microchips third party guide (ds00104) for a list of sources. the amount of time required to completely erase a uv erasable device depends on: the wave- length of the light, its intensity, distance from uv source, the process technology of the device (how small are the memory cells). 1.5.3.5 one-time-programmable (otp) devices the availability of otp devices is especially useful for customers expecting code changes and updates. otp devices, packaged in plastic packages, permit the user to program them once. in addition to the program and data eprom memories, the con?uration bits must be programmed. 1.5.3.6 flash devices a flash device allows its memory to be changed by an electric charge. this means that the sys- tem can be designed so that programming may be performed in-circuit. since no window is required, the lower cost plastic packages can used for these devices. 1.5.3.7 eeprom devices an eeprom device allows its memory to be erased by an electric charge. this means that the system can be designed so that erasure and reprogramming may be performed in-circuit. since no window is required, the lower cost plastic packages can used for these devices. note: fluorescent lights and sunlight both emit ultraviolet light at the erasure wavelength. leaving a uv erasable devices window uncovered could cause, over time, the devices memory cells to become erased. the erasure time for a ?orescent light is about three years, while sunlight requires only about one week. to prevent the mem- ory cells from losing data, an opaque label should be placed over the erasure win- dow.
1997 microchip technology inc. ds31001a-page 1-11 section 1. introduction introduction 1 1.5.3.8 rom devices rom devices have their program memory ?ed at the time of the silicon manufacture. since the program memory cannot be changed, the device can be housed in the lower cost plastic pack- age. 1.5.3.9 die the die option allows the board size to become as small as physically possible. the die support document (ds30258) explains general information about using and designing with die. there are also individual speci?ation sheets that detail die speci? information. manufacturing with die requires special knowledge and equipment. this means that the number of manufacturing houses that support die will be limited. if you decide to use the die option, please research your manufacturing sites to ensure that they will be able to meet the specialized requirements of die use. 1.5.3.10 specialized services for otp customers with established code, microchip offers two specialized services. these two services, quick turn production programming and serialized quick turn production program- ming, that allow customers to shorten their manufacturing cycle time. 1.5.3.11 quick turn production (qtp) programming microchip offers this programming service for factory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. the devices are identical to the otp devices but with all eprom loca- tions and con?uration options already programmed by the factory. certain code and prototype veri?ation procedures apply before production shipments are available. please contact your local microchip sales of?e for more details. 1.5.3.12 serialized quick turn production (sqtp sm ) programming microchip offers a this unique programming service where a few user-de?ed locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number which can serve as an entry-code, password or id number.
picmicro mid-range mcu family ds31001a-page 1-12 1997 microchip technology inc. 1.6 style and symbol conventions throughout this document, certain style and font format changes are used. most format changes imply a distinction should be made for the emphasized text. the mcu industry has many symbols and non-conventional word de?itions/abbreviations. table 1-4 provides a description for many of the conventions contained in this document. a glossary is provided in the ?lossary section, which contains more word and abbreviation de?itions that are used throughout this manual. 1.6.1 document conventions table 1-4 de?es some of the symbols and terms used throughout this manual. table 1-4: document conventions symbol or term description set to force a bit/register to a value of logic ?? clear to force a bit/register to a value of logic ?? reset 1) to force a register/bit to its default state. 2) a condition in which the device places itself after a device reset occurs. some bits will be forced to ? (such as interrupt enable bits), while others will be forced to ? (such as the i/o data direction bits). 0xnn or nnh designates the number ?n in the hexadecimal number system. these conventions are used in the code examples. b?bbbbbbb designates the number ?bbbbbbb in the binary number system. this convention is used in the text and in ?ures and tables. r-m-w read - modify - write. this is when a register or port is read, then the value is modi?d, and that value is then written back to the register or port. this action can occur from a single instruction (such as bit set ?e, bsf ) or a sequence of instructions. : (colon) used to specify a range, or the concatenation of registers / bits / pins. an example is tmr1h:tmr1l is the concatenation of two 8-bit registers to form a 16-bit timer value, while sspm3:sspm0 are 4-bits used to specify the mode of the ssp module. concatenation order (left-right) usually speci?s a positional relationship (msb to lsb, higher to lower). < > speci?s bit(s) locations in a particular register. an example is sspcon (or sspcon<3:0>) speci?s the register and associated bits or bit positions. courier font used for code examples, binary numbers, and for instruction mnemonics in the text. times font used for equations and variables. times, bold font, italics used in explanatory text for items called out from a graphic/equa- tion/example. note notes present information that we wish to reemphasize, either to help you avoid a common pitfall, or make you aware of operating differences between some device family members. a note is always in a shaded box (as below), unless used in a table, where it is at the bottom of the table (as in this table). note: this is a note in a note box. caution (1) a caution statement describes a situation that could potentially damage software or equipment. warning (1) a warning statement describes a situation that could potentially cause personnel harm. note 1: the information in a caution or a warning is provided for your protection. please read each caution and warning carefully.
1997 microchip technology inc. ds31001a-page 1-13 section 1. introduction introduction 1 1.6.2 electrical speci?ations throughout this manual there will be references to electrical speci?ation parameter numbers. a parameter number represents a unique set of characteristics and conditions that is consistent between every data sheet, though the actual parameter value may vary from device to device. the ?lectrical speci?ations section shows all the speci?ations that are documented for all devices. no one device has all these speci?ations. this section is intended to let you know the types of parameters that microchip speci?s. the value of each speci?ation is device depen- dent, though we strongly attempt to keep them consistent across all devices. table 1-5: electrical speci?ation parameter numbering convention parameter number format comment dxxx dc speci?ation axxx dc speci?ation for analog peripherals xxx timing (ac) speci?ation pdxxx device programming dc speci?ation pxxx device programming timing (ac) speci?ation legend: xxx: represents a number.
picmicro mid-range mcu family ds31001a-page 1-14 1997 microchip technology inc. 1.7 related documents microchip, as well as other sources, offers additional documentation which can aid in your devel- opment with picmicro mcus. these lists contain the most common documentation but other documents may also be available. please check the microchip web site (www.microchip.com) for the latest published technical documentation. 1.7.1 microchip documentation the following documents are available from microchip. many of these documents provide appli- cation speci? information that give actual examples of using, programming and designing with picmicro mcus. 1. mpasm users guide (ds33014) this document explains how to use microchips mpasm assembler. 2. mplab-c compiler users guide (ds51014) this document explains how to use microchips mplab-c c compiler. 3. mplab users guide (ds51025) this document explains how to use microchips mplab integrated development environ- ment. 4. mplab editor users guide (ds30420) this document explains how to use microchips mplab built-in editor. 5. picmaster users guide (ds30421) this document explains how to use microchips picmaster in-circuit emulator. 6. mpsim users guide (ds30027) this document explains how to use microchips mplab simulator. 7. pro mate users guide (ds30082) this document explains how to use microchips pro mate universal programmer. 8. picstart -plus users guide (ds51028) this document explains how to use microchips picstart-plus low-cost universal pro- grammer. 9. fuzzy tech -mp users guide (ds30389) this document explains how to use the fuzzy tech-mp fuzzy logic code generator. 10. mp-driveway users guide (ds51027) this document explains how to use the mp-driveway code generator. 11. fuzzy tech-mp fuzzy logic handbook (ds30238) this document explains the basics of fuzzy tech-mp fuzzy. 12. embedded control handbook volume i (ds00092) this document contains a plethora of application notes. this is useful for insight on how to use the device (or parts of it) as well as getting started on your particular application due to the availability of extensive code ?es. 13. embedded control handbook volume ii (ds00167) this document contains the math libraries for picmicro mcus. 14. in-circuit serial programming guide (ds30277) this document discusses implementing in-circuit serial programming. 15. picdem-1 users guide (ds351079) this document explains how to use microchips picdem-1 demo board. 16. picdem-2 users guide (ds30374) this document explains how to use microchips picdem-2 demo board. 17. picdem-3 users guide (ds33015) this document explains how to use microchips picdem-3 demo board. 18. third party guide (ds00104) this document lists microchips third parties, as well as various consultants. 19. die support (ds30258) this document gives information on using microchip products in die form.
1997 microchip technology inc. ds31001a-page 1-15 section 1. introduction introduction 1 1.7.2 third party documentation there are several documents available from third party sources around the world. microchip does not review these documents for technical accuracy, however they may be a helpful source for understanding the operation of microchip mcu devices. this is not necessarily a complete list, but are the documents that we were aware of at the time of printing. for more information on how to contact some of these sources, as well as any new sources that we become aware of, please visit the microchip web site. document langu a ge the pic16c5x microcontroller: a practical approach to embedded control bill rigby/ terry dalby, tecksystems inc. 0-9654740-0-3............................................................................................................ englis h easy pic'n david benson, square 1 electronics 0-9654162-0-8............................................................................................................ englis h a beginners guide to the microchip pic nigel gardner, bluebird electronics 1-899013-01-6............................................................................................................ englis h pic microcontroller operation and applications dn de beer, cape technikon ..................................................................................... english digital systems and programmable interface controllers wp verburg, pretoria technikon ................................................................................ english mikroprozessor pic16c5x michael rose, h?thig 3-7785-2169-1...........................................................................................................german mikroprozessor pic17c42 michael rose, h?thig 3-7785-2170-5...........................................................................................................german les microcontrolleurs pic et mise en oeuvre christian tavernier, dunod 2-10-002647-x ............................................................................................................french micontrolleurs pic a structure risc c.f. urbain, publitronic 2-86661-058-x ............................................................................................................french new possibilities with the microchip pic riga ......................................................................................................................... ru ssian
picmicro mid-range mcu family ds31001a-page 1-16 1997 microchip technology inc. document langu a ge pic16c5x/71/84 development and design, part 1 united tech electronic co. ltd 957-21-0807-7.......................................................................................................... chinese pic16c5x/71/84 development and design, part 2 united tech electronic co. ltd 957-21-1152-3.......................................................................................................... chinese pic16c5x/71/84 development and design, part 3 united tech electronic co. ltd 957-21-1187-6.......................................................................................................... chinese pic16c5x/71/84 development and design, part 4 united tech electronic co. ltd 957-21-1251-1.......................................................................................................... chinese pic16c5x/71/84 development and design, part 5 united tech electronic co. ltd 957-21-1257-0.......................................................................................................... chinese pic16c84 mcu architecture and software development icc company 957-8716-79-6.......................................................................................................... chinese
1997 microchip technology inc. ds31001a-page 1-17 section 1. introduction introduction 1 1.8 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the pic16cxxx mid-range mcu family (that is they may be written for the base-line, or the high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to an introduction to microchips picmicro mcus are: title application note # a comparison of low end 8-bit microcontrollers an520 pic16c54a emi results an577 continuous improvement an503 improving the susceptibility of an application to esd an595 plastic packaging and the effects of surface mount soldering techniques an598
picmicro mid-range mcu family ds31001a-page 1-18 1997 microchip technology inc. 1.9 revision history revision a this is the initial released revision of microchips picmicro mcus introduction.
1997 microchip technology inc. ds31002a page 2-1 m oscillator 2 section 2. oscillator highlights this section of the manual contains the following major topics: 2.1 introduction ................................................................................................................ ....2-2 2.2 oscillator con?urations ................................................................................................2-2 2.3 crystal oscillators / ceramic resonators ......................................................................2-4 2.4 external rc oscillator..................................................................................................2-12 2.5 internal 4 mhz rc oscillator .......................................................................................2-13 2.6 effects of sleep mode on the on-chip oscillator .........................................................2-17 2.7 effects of device reset on the on-chip oscillator .......................................................2-17 2.8 design tips ................................................................................................................. .2-18 2.9 related application notes............................................................................................2-19 2.10 revision history ........................................................................................................... 2-20
picmicro mid-range mcu family ds31002a-page 2-2 1997 microchip technology inc. 2.1 introduction the internal oscillator circuit is used to generate the device clock. the device clock is required for the device to execute instructions and for the peripherals to function. four device clock peri- ods generate one internal instruction clock (t cy ) cycle. there are up to eight different modes which the oscillator may have. there are two modes which allow the selection of the internal rc oscillator clock out (clkout) to be driven on an i/o pin, or allow that i/o pin to be used for a general purpose function. the oscillator mode is selected by the device con?uration bits. the device con?uration bits are nonvolatile memory locations and the operating mode is determined by the value written during device programming. the oscillator modes are: lp low frequency (power) crystal xt crystal/resonator hs high speed crystal/resonator rc external resistor/capacitor (same as extrc with clkout) extrc external resistor/capacitor extrc external resistor/capacitor with clkout intrc internal 4 mhz resistor/capacitor intrc internal 4 mhz resistor/capacitor with clkout these oscillator options are made available to allow a single device type the ?xibility to ? appli- cations with different oscillator requirements. the rc oscillator option saves system cost while the lp crystal option saves power. con?uration bits are used to select the various options. for more details on the device con?uration bits, see the ?evice characteristics section. 2.2 oscillator con?urations 2.2.1 oscillator types mid-range devices can have up to eight different oscillator modes. the user can program up to three device con?uration bits (fosc2, fosc1 and fosc0) to select one of these eight modes: lp low frequency (power) crystal xt crystal/resonator hs high speed crystal/resonator rc external resistor/capacitor (same as extrc with clkout) extrc external resistor/capacitor extrc external resistor/capacitor with clkout intrc internal 4 mhz resistor/capacitor intrc internal 4 mhz resistor/capacitor with clkout the main difference between the lp, xt, and hs modes is the gain of the internal inverter of the oscillator circuit which allows the different frequency ranges. table 2-1 and table 2-2 give infor- mation to aid in selecting an oscillator mode. in general, use the oscillator option with the lowest possible gain which still meet speci?ations. this will result in lower dynamic currents (i dd ). the frequency range of each oscillator mode is the recommended (tested) frequency cutoffs, but the selection of a different gain mode is acceptable as long as a thorough validation is performed (voltage, temperature, component variations (resistor, capacitor, and internal microcontroller oscillator circuitry)). the rc mode and the extrc with clkout mode have the same functionality. they are named like this to help describe their operation vs. the other oscillator modes.
1997 microchip technology inc. ds31002a-page 2-3 section 2. oscillator oscillator 2 table 2-1: selecting the oscillator mode for devices with fosc1:fosc0 table 2-2: selecting the oscillator mode for devices with fosc2:fosc0 con?uration bits fosc1:fosc0 osc mode osc feedback inverter gain comment 1 1 rc least expensive solution for device oscillation (only an external resistor and capacitor is required). most variation in time-base. devices default mode. 1 0 hs high gain high frequency application. oscillator circuits mode consumes the most current of the three crystal modes. 0 1 xt medium gain standard crystal/resonator frequency. oscillator circuits mode consumes the middle current of the three crystal modes. 0 0 lp low gain low power/frequency applications. oscillator circuits mode consumes the least current of the three crystal modes. con?uration bits fosc2:fosc0 osc mode osc feedback inverter gain comment 1 1 1 extrc with clkout inexpensive solution for device oscillation. most variation in timebase. clkout is enabled on pin. devices default mode. 1 1 0 extrc inexpensive solution for device oscillation. most variation in timebase. clkout is disabled (use as i/o) on pin. 1 0 1 intrc with clkout least expensive solution for device oscillation. 4 mhz oscillator, which can be tuned. clkout is enabled on pin. 1 0 0 intrc least expensive solution for device oscillation. 4 mhz oscillator, which can be tuned. clkout is disabled (use as i/o) on pin. 0 1 1 reserved 0 1 0 hs high gain high frequency application. oscillator circuits mode consumes the most current of the three crystal modes. 0 0 1 xt medium gain standard crystal/resonator frequency. oscillator circuits mode consumes the middle current of the three crystal modes. 0 0 0 lp low gain low power/frequency applications. oscillator circuits mode consumes the least current of the three crystal modes.
picmicro mid-range mcu family ds31002a-page 2-4 1997 microchip technology inc. 2.3 crystal oscillators / ceramic resonators in xt, lp or hs modes a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation ( figure 2-1 ). the picmicro oscillator design requires the use of a parallel cut crystal. using a series cut crystal may give a frequency out of the crystal manufacturers speci?ations. when in xt, lp or hs modes, the device can have an external clock source drive the osc1 pin ( figure 2-3 ). figure 2-1: crystal or ceramic resonator operation (hs, xt or lp oscillator mode) c1 c2 xtal osc2 rs (1) osc1 r f (2) sleep to internal logic (3) pic16cxxx to internal logic (3) note 1: a series resistor, r s , may be required for at strip cut crystals. 2: the feedback resistor, r f , is typically in the range of 2 to 10 m w. 3: depending on the device, the buffer to the internal logic may be either before or after the oscillator inverter.
1997 microchip technology inc. ds31002a-page 2-5 section 2. oscillator oscillator 2 2.3.1 oscillator / resonator start-up as the device voltage increases from v ss , the oscillator will start its oscillations. the time required for the oscillator to start oscillating depends on many factors. these include: crystal / resonator frequency capacitor values used ( c1 and c2 in figure 2-1 ) device v dd rise time system temperature series resistor value (and type) if used ( rs in figure 2-1 ) oscillator mode selection of device (which selects the gain of the internal oscillator inverter) crystal quality oscillator circuit layout system noise figure 2-2 graphs an example oscillator / resonator start-up. the peak-to-peak voltage of the oscillator waveform can be quite low (less than 50% of device v dd ) where the waveform is cen- tered at v dd /2 (refer to parameters d033 and d043 in the ?lectrical speci?ations section). figure 2-2: example oscillator / resonator start-up characteristics voltage crystal start-up time time device v dd maximum v dd of system 0v
picmicro mid-range mcu family ds31002a-page 2-6 1997 microchip technology inc. 2.3.2 component selection figure 2-1 is a diagram of the devices crystal or ceramic resonator circuitry. the resistance for the feedback resistor, r f , is typically within the 2 to 10 m w range. this varies with device voltage, temperature, and process variations. a series resistor, rs , may be required if an at strip cut crys- tal is used. be sure to include the devices operating voltage and the devices manufacturing pro- cess when determining resistor requirements. as you can see in figure 2-1 , the connection to the devices internal logic is device dependent. see the applicable data sheet for device speci?s. the typical values of capacitors ( c1 , c2 ) are given in table 2-3 and table 2-4 . each devices data sheet will give the speci? values that microchip tested. table 2-3: typical capacitor selection for ceramic resonators ranges tested: mode frequency c1 / c2 (1) xt 455 khz 2.0 mhz 4.0 mhz 22 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 20.0 mhz 10 - 68 pf 10 - 22 pf tbd resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% 20.0 mhz tbd tbd note 1: recommended values of c1 and c2 are identical to the ranges tested above. higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appro- priate values of external component or verify oscillator performance. 2: all resonators tested required external capacitors.
1997 microchip technology inc. ds31002a-page 2-7 section 2. oscillator oscillator 2 table 2-4: typical capacitor selection for crystal oscillator mode freq c1 (1) c2 (1) lp 32 khz 200 khz 68 - 100 pf 15 - 30 pf 68 - 100 pf 15 - 30 pf xt 100 khz 2 mhz 4 mhz 68 - 150 pf 15 - 30 pf 15 - 30 pf 150 - 200 pf 15 - 30 pf 15 - 30 pf hs 8 mhz 10 mhz 20 mhz 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf crystals used: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm 2.0 mhz ecs ecs-20-s-2 50 ppm 4.0 mhz ecs ecs-40-s-4 50 ppm 10.0 mhz ecs ecs-100-s-4 50 ppm 20.0 mhz ecs ecs-200-s-4 50 ppm note 1: higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for design guidance only. a series resistor, rs , may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level speci?ation. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external compo- nents or verify oscillator performance.
picmicro mid-range mcu family ds31002a-page 2-8 1997 microchip technology inc. 2.3.3 tuning the oscillator circuit since microchip devices have wide operating ranges (frequency, voltage, and temperature; depending on the part and version ordered) and external components (crystals, capacitors,...), of varying quality and manufacture; validation of operation needs to be performed to ensure that the component selection will comply with the requirements of the application. there are many factors that go into the selection and arrangement of these external components. these factors include: ampli?r gain desired frequency resonant frequency(s) of the crystal temperature of operation supply voltage range start-up time stability crystal life power consumption simpli?ation of the circuit use of standard components combination which results in fewest components
1997 microchip technology inc. ds31002a-page 2-9 section 2. oscillator oscillator 2 2.3.3.1 determining best values for crystals, clock mode, c1 , c2, and rs the best method for selecting components is to apply a little knowledge and a lot of trial, mea- surement, and testing. crystals are usually selected by their parallel resonant frequency only, however other parame- ters may be important to your design, such as temperature or frequency tolerance. application note an588 is an excellent reference if you would like to know more about crystal operation and their ordering information. the picmicros internal oscillator circuit is a parallel oscillator circuit, which requires that a par- allel resonant crystal be selected. the load capacitance is usually speci?d in the 20 pf to 32 pf range. the crystal will oscillate closest to the desired frequency with capacitance in this range. it may be necessary to sometimes juggle these values a bit, as described later, in order to achieve other bene?s. clock mode is primarily chosen by using the f osc parameter speci?ation ( parameter 1a ) in the devices data sheet, based on frequency. clock modes (except rc) are simply gain selections, lower gain for lower frequencies, higher gain for higher frequencies. it is possible to select a higher or lower gain, if desired, based on the speci? needs of the oscillator circuit. c1 and c2 should also be initially selected based on the load capacitance as suggested by the crystal manufacturer and the tables supplied in the device data sheet. the values given in the microchip data sheet can only be used as a starting point, since the crystal manufacturer, supply voltage, and other factors already mentioned may cause your circuit to differ from the one used in the factory characterization process. ideally, the capacitance is chosen (within the range of the recommended crystal load preferably) so that it will oscillate at the highest temperature and lowest v dd that the circuit will be expected to perform under. high temperature and low v dd both have a limiting affect on the loop gain, such that if the circuit functions at these extremes, the designer can be more assured of proper oper- ation at other temperatures and supply voltage combinations. the output sine wave should not be clipped in the highest gain environment (highest v dd and lowest temperature) and the sine output amplitude should be great enough in the lowest gain environment (lowest v dd and highest temperature) to cover the logic input requirements of the clock as listed in the device data sheet. a method for improving start-up is to use a value of c2 greater than c1 . this causes a greater phase shift across the crystal at power-up, which speeds oscillator start-up. besides loading the crystal for proper frequency response, these capacitors can have the effect of lowering loop gain if their value is increased. c2 can be selected to affect the overall gain of the circuit. a higher c2 can lower the gain if the crystal is being over driven (see also discussion on rs ). capacitance values that are too high can store and dump too much current through the crystal, so c1 and c2 should not become excessively large. unfortunately, measuring the watt- age through a crystal is tricky business, but if you do not stray too far from the suggested values you should not have to be concerned with this. a series resistor, rs , is added to the circuit if, after all other external components are selected to satisfaction, the crystal is still being over driven. this can be determined by looking at the osc2 pin, which is the driven pin, with an oscilloscope. connecting the probe to the osc1 pin will load the pin too much and negatively affect performance. remember that a scope probe adds its own capacitance to the circuit, so this may have to be accounted for in your design, i.e. if the circuit worked best with a c2 of 20 pf and scope probe was 10 pf, a 30 pf capacitor may actually be called for. the output signal should not be clipping or squashed. overdriving the crystal can also lead to the circuit jumping to a higher harmonic level or even crystal damage.
picmicro mid-range mcu family ds31002a-page 2-10 1997 microchip technology inc. the osc2 signal should be a nice clean sine wave that easily spans the input minimum and max- imum of the clock input pin (4v to 5v peak to peak for a 5v v dd is usually good). an easy way to set this is to again test the circuit at the minimum temperature and maximum v dd that the design will be expected to perform in, then look at the output. this should be the maximum ampli- tude of the clock output. if there is clipping or the sine wave is squashing near v dd and v ss at the top and bottom, and increasing load capacitors will risk too much current through the crystal or push the value too far from the manufacturers load speci?ation, then add a trimpot between the output pin and c2 , and adjust it until the sine wave is clean. keeping it fairly close to maximum amplitude at the low temperature and high v dd combination will assure this is the maximum amplitude the crystal will see and prevent overdriving. a series resistor, rs , of the closest stan- dard value, can now be inserted in place of the trimpot. if rs is too high, perhaps more than 20k ohms, the input will be too isolated from the output, making the clock more susceptible to noise. if you ?d a value this high is needed to prevent overdriving the crystal, try increasing c2 to compensate. try to get a combination where rs is around 10k or less, and load capacitance is not too far from the 20 pf or 32 pf manufacturer speci?ation. 2.3.3.1.1 start-up the most dif?ult time for the oscillator to start-up is when waking up from sleep. this is because the load capacitors have both partially charged to some quiescent value, and phase differential at wake-up is minimal. thus, more time is required to achieve stable oscillation. remember also that low voltage, high temperatures, and the lower frequency clock modes also impose limitations on loop gain, which in turn affects start-up. each of the following factors makes thing worse: a low frequency design (with its low gain clock mode) a quiet environment (such as a battery operated device) operating outside the noisy rf area (such as in a shielded box) low voltage high temperature waking up from sleep. noise actually helps a design for oscillator start-up, since it helps kick start the oscillator. 2.3.4 external clock input if the picmicros internal oscillator is not being used, and the device will be driven from an exter- nal clock, be sure to set the oscillator mode to one of the crystal modes (lp, xt, or hs). that is, something other than one of the rc modes, since rc mode will ?ht with the injected input. ide- ally you would select the mode that corresponds to the frequency injected, but this is of less importance here since the clock is only driving its internal logic, and not a crystal loop circuit. it may be possible to select a clock mode lower than would be needed by an oscillator circuit, and thereby save some of the power that would be used exercising the inverting ampli?r. make sure the osc2 signal amplitude covers the needed logic thresholds of the device. figure 2-3: external device clock input operation (hs, xt or lp oscillator modes) clock from external system pic16cxxx osc1 osc2 open note 1: a resistor to ground may be used to reduce system noise. this may increase system current. (1)
1997 microchip technology inc. ds31002a-page 2-11 section 2. oscillator oscillator 2 2.3.5 external crystal oscillator circuit for device clock sometimes more than one device needs to be clocked from a single crystal. since microchip does not recommend connecting other logic to the picmicros internal oscillator circuit, an exter- nal crystal oscillator circuit is recommended. each device will then have an external clock source, and the number of devices that can be driven will depend on the buffer drive capability. this circuit is also useful when more than one device (picmicro) needs to operate synchronously to each other. either a prepackaged oscillator can be used or a simple oscillator circuit with ttl gates can be built. prepackaged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator cir- cuits can be used; one with series resonance, or one with parallel resonance. figure 2-4 shows implementation of an external parallel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k w resistor provides the nega- tive feedback for stability. the 10 k w potentiometer biases the 74as04 in the linear region. figure 2-4: external parallel resonant crystal oscillator circuit figure 2-5 shows an external series resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the crystal. the inverter performs a 180-degree phase shift in a series resonant oscillator circuit. the 330 k w resistors provide the negative feedback to bias the inverters in their linear region. figure 2-5: external series resonant crystal oscillator circuit when the device is clocked from an external clock source (as in figure 2-4 or figure 2-5 ) then the microcontrollers oscillator must be con?ured for lp, xt or hs mode ( figure 2-3 ). 20 pf +5v 20 pf 10k w 4.7 k w 10 k w 74as04 xtal 10 k w 74as04 clkin to other devices pic16cxxx 330 k w 74as04 74as04 pic16cxxx clkin to other devices xtal 330 k w 74as04 0.1 m f
picmicro mid-range mcu family ds31002a-page 2-12 1997 microchip technology inc. 2.4 external rc oscillator for timing insensitive applications the ?xtrc device option offers additional cost savings. the rc oscillator frequency is a function of; the supply voltage, the resistor (r ext ) and capacitor (c ext ) values, and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r ext and c ext components used. figure 2-6 shows how the rc combination is connected to a pic16cxxx. for r ext values below 2.2 k w , oscillator operation may become unstable, or stop completely. for very high r ext values (e.g. 1 m w ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping r ext between 3 k w and 100 k w . figure 2-6: extrc oscillator mode although the oscillator will operate with no external capacitor (c ext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance and package lead frame capacitance. see characterization data for rc frequency variation from part to part due to normal process variation. the variation is larger for larger resistance (since leakage current variation will affect rc frequency more for large r) and for smaller capacitance (since variation of input capacitance will affect rc frequency more). see characterization data for variation of oscillator frequency due to v dd for given r ext /c ext values as well as frequency variation due to operating temperature for given r ext , c ext , and v dd values. the oscillator frequency, divided by 4, is available on the osc2/clkout pin, and can be used for test purposes or to synchronize other logic (see figure 4-3: "clock/instruction cycle" in the ?rchitecture section, for waveform). 2.4.1 rc start-up as the device voltage increases, the rc will start its oscillations immediately after the pin voltage levels meet the input threshold speci?ations ( parameters d032 and d042 in the ?lectrical speci?ations section). the time required for the rc to start oscillating depends on many fac- tors. these include: resistor value used capacitor value used device v dd rise time system temperature osc2/clkout c ext v dd r ext v ss pic16cxxx osc1 fosc/4 (1) internal clock fosc note 1: this output may also be able to be con?ured as a general purpose i/o pin.
1997 microchip technology inc. ds31002a-page 2-13 section 2. oscillator oscillator 2 2.5 internal 4 mhz rc oscillator the internal rc oscillator (not on all devices) provides a ?ed 4 mhz (nominal) system clock at v dd = 5v and 25 c, see the device data sheets ?lectrical speci?ations section for information on variation over voltage and temperature. the value in the osccal register is used to tune the frequency of the internal rc oscillator. the calibration value that microchip programs into the device will ?rim the internal oscillator to remove process variation from the oscillator frequency. the cal3:cal0 bits are used for ?e cal- ibration within a frequency window. higher values of cal3:cal0 (from 0000 to 1111) yields higher clock speeds. when a 4 mhz internal rc oscillator frequency cannot be achieved by a cal3:cal0 value, the rc oscillator frequency can be increased or decreased by an offset frequency. the calfst and calslw bits are used to enable a positive or negative frequency offset to place the internal rc frequency within the cal3:cal0 trim window. setting the calfst bit offsets the internal rc for a higher frequency, while setting the calslw bit offsets the internal rc for a lower frequency. upon a device reset, the osccal register is forced to the midpoint value (cal3:cal0 = 7h, calfst and calslw providing no offset). register 2-1: osccal register r/w-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 u-0 u-0 cal3 cal2 cal1 cal0 calfst calslw bit 7 bit 0 bit 7:4 cal3:cal0: internal rc oscillator calibration bits 0000 = lowest clock frequency within the trim range 1111 = highest clock frequency within the trim range bit 3 calfst: oscillator range offset bit 1 = increases the frequency of the internal rc oscillator into the cal3:cal0 trim window 0 = no offset provided bit 2 calslw: oscillator range offset bit 1 = decreases the frequency of the internal rc oscillator into the cal3:cal0 trim window 0 = no offset provided note: when both bits are set, the calfst bit overrides the calslw bit. bit 1:0 unimplemented: read as '0' note: these bits should be written as ? when modifying the osccal register, for com- patibility with future devices. legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset note: osccal is used to remove process variation from the internal rc oscillator of the device. the osccal value should not be modi?d from the microchip supplied value, and all timing critical functions should be adjusted by the application software.
picmicro mid-range mcu family ds31002a-page 2-14 1997 microchip technology inc. figure 2-7 shows the possible device frequencies from the uncalibrated point (at v dd = 5v, 25 c, and osccal = 70h), and the changes achievable by the osccal register. figure 2-7: ideal internal rc oscillator frequency vs. osccal register value figure 2-8 shows an example of a device where by selecting one of the cal3:cal0 values, the frequency can corrected to 4 mhz. these bits can be considered the ?e trimming of the frequency. sometimes the device frequency at the uncalibrated point cannot be corrected to 4 mhz by the ?e trimming of the cal3:cal0 bits value. therefore two additional bits are available which give a large frequency offset (positive and negative) to move the frequency within the range where the ?e trimming can work. these bits are the calslw and calfst bits, which offset the internal rc frequency. the action of these bits are shown in figure 2-9 , and figure 2-10 . figure 2-8: cal3:cal0 trimming of internal rc oscillator frequency offset frequency cal3:cal0 = 07h calfst = 0 calslw = 0 see x-axis cal3:cal0 trim window cal3:cal0 = fh calfst = 1 calslw = x cal3:cal0 = 0h calfst = 0 calslw = 1 cal3:cal0 = 0h calfst = 0 calslw = 0 cal3:cal0 = fh calfst = 0 calslw = 0 4 mhz (slowest frequency) (fastest frequency) frequency cal3:cal0 trim window 4 mhz 1.5% cal3:cal0 = 0000 cal3:cal0 = 1111 internal rc frequency at > 4 mhz < 4 mhz one of the 16 possible calibration points (@ 5v, 25?c) device reset calfst = 0 calflw = 0 cal3:cal0 = 7h
1997 microchip technology inc. ds31002a-page 2-15 section 2. oscillator oscillator 2 figure 2-9: calfst positive internal rc oscillator frequency offset figure 2-10: calslw negative internal rc oscillator frequency offset cal3:cal0 trim window cal3:cal0 = 0000 cal3:cal0 = 1111 internal rc frequency at calfst offset internal rc frequency with calfst = 1 calslw = x frequency 4 mhz 1.5% < 4 mhz (@ 5v, 25?c) one of the 16 possible cal3:cal0 calibration points device reset calfst = 0 calflw = 0 frequency cal3:cal0 trim window cal3:cal0 = 0000 cal3:cal0 = 1111 internal rc frequency at internal rc frequency with calslw = 1 calfst = 0 calslw offset device reset one of the 16 possible cal3:cal0 calibration points 4 mhz 1.5% > 4 mhz (@ 5v, 25?c) calslw = 0 calfst = 0
picmicro mid-range mcu family ds31002a-page 2-16 1997 microchip technology inc. a calibration instruction is programmed into the last address of the implemented program memory. this instruction contains the calibration value for the internal rc oscillator. this value is programmed as a retlw xx instruction where xx is the calibration value. in order to retrieve the calibration value, issue a call yy instruction where yy is the last location in the devices user accessible program memory. the calibration value is now loaded in the w register. the program should then perform a movwf osccal instruction to load the value into the internal rc oscillator calibration register. table 2-5 shows the location of the calibration value depending on the size of the program memory. table 2-5: calibration value location 2.5.1 clock out the internal rc oscillator can be con?ured to provide a clock out signal on the clkout pin when the con?uration word address (2007h) is programmed with fosc2, fosc1, fosc0 equal to 101 for internal rc or 111 for external rc. clkout, which is divided by 4, can be used for test purposes or to synchronize other logic. when the calibration value of the internal rc oscillator is accidently erased, the clock out feature allows the user to determine what the calibration value should be. this is achieved by writing a program which modi?s (increments/decrements) the value of the osccal register. when the clkout pin is at 4 mhz ( 1.5%) at 5v and 25?c, the osccal register has the correct calibra- tion value. this value then needs to be written to a port or shifted out serially, so that the value can be written down and programmed into the calibration location. program memory size (words) calibration value location 512 1ffh 1k 3ffh 2k 7ffh 4k fffh 8k 1fffh note 1: erasing the device (windowed devices) will also erase the factory programmed calibration value for the internal oscillator. prior to erasing a windowed device, the internal oscillator calibration value must be saved. it is a good idea to write this value on the package of the device to ensure that the calibration value is not accidently lost. this saved valued must be restored into program memory calibration location before programming the device. note 2: osccal<1:0> are unimplemented and should be written as ?? this will help ensure compatibility with future devices.
1997 microchip technology inc. ds31002a-page 2-17 section 2. oscillator oscillator 2 2.6 effects of sleep mode on the on-chip oscillator when the device executes a sleep instruction, the on-chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (q1 state). with the oscillator off, the osc1 and osc2 signals will stop oscillating. since all the transistor switching currents have been removed, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the user can wake from sleep through external reset, watchdog timer reset or through an interrupt. table 2-6: osc1 and osc2 pin states in sleep mode 2.7 effects of device reset on the on-chip oscillator device resets have no effect on the on-chip crystal oscillator circuitry. the oscillator will continue to operate as it does under normal execution. while in reset, the device logic is held at the q1 state so that when the device exits reset, it is at the beginning of an instruction cycle. the osc2 pin, when used as the external clockout (extrc mode), will be held low during reset, and as soon as the mclr pin is at v ih (input high voltage), the rc will start to oscillate. see table 3-1 , in the ?eset section, for time-outs due to sleep and mclr reset. 2.7.1 power-up delays there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer, ost, intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a ?ed delay of 72 ms (nominal) on power-up only (por and bor). the pwrt is designed to keep the part in reset while the power supply sta- bilizes. with these two timers on-chip, most applications need no external reset circuitry. for additional information on reset operation, see the ?eset section. osc mode osc1 pin osc2 pin extrc floating, external resistor should pull high at logic low intrc n.a. n.a. lp, xt, and hs feedback inverter disabled, at quiescent voltage level feedback inverter disabled, at quiescent voltage level see table 3-1 , in the ?eset section, for time-outs due to sleep and mclr reset.
picmicro mid-range mcu family ds31002a-page 2-18 1997 microchip technology inc. 2.8 design tips question 1: when looking at the osc2 pin after power-up with an oscilloscope, there is no clock. what can cause this? answer 1: 1. executing a sleep instruction with no source for wake-up (such as, wdt, mclr , or an interrupt). verify that the code does not put device to sleep without providing for wake-up. if it is possible, try waking it up with a low pulse on mclr . powering up with mclr held low will also give the crystal oscillator more time to start-up, but the program counter will not advance until the mclr pin is high. 2. the wrong clock mode is selected for the desired frequency. for a blank device, the default oscillator is extrc. most parts come with the clock selected in the default rc mode, which will not start oscillation with a crystal or resonator. verify that the clock mode has been programmed correctly. 3. the proper power-up sequence has not been followed. if a cmos part is powered through an i/o pin prior to power-up, bad things can happen (latch up, improper start-up etc.) it is also possible for brown-out conditions, noisy power lines at start-up, and slow v dd rise times to cause problems. try powering up the device with nothing connected to the i/o, and power-up with a known, good, fast-rise, power supply. it is not as much of a problem as it may sound, but the possibility exists. refer to the power-up information in the device data sheet for considerations on brown-out and power-up sequences. 4. the c1 and c2 capacitors attached to the crystal have not been connected properly or are not the correct values. make sure all connections are correct. the device data sheet val- ues for these components will almost always get the oscillator running, they just might not be the optimal values for your design. question 2: the picmicro starts, but runs at a frequency much higher than the resonant frequency of the crystal. answer 2: the gain is too high for this oscillator circuit. refer to subsection 2.3 ?rystal oscillators / ceramic resonators to aid in the selection of c2 (may need to be higher) rs (may be needed) and clock mode (wrong mode may be selected). this is especially possible for low frequency crystals, like the common 32.768 khz. question 3: the design runs ?e, but the frequency is slightly off, what can be done to adjust this? answer 3: changing the value of c1 has some affect on the oscillator frequency. if a series resonant crys- tal is used, it will resonate at a different frequency than a parallel resonant crystal of the same frequency call-out. question 4: the board works ?e, then suddenly quits, or loses time. answer 4: other than the obvious software checks that should be done to investigate losing time, it is pos- sible that the amplitude of the oscillator output is not high enough to reliably trigger the oscillator input. question 5: i? using a device with the internal rc oscillator and i have accidently erased the calibration value. what can i do? answer 5: if the frequency of the device does not matter, you can continue to use the device. if the frequency of the device does matter, you can purchase a new windowed device, or follow the suggestion in subsection 2.5.1 ?lock out.
1997 microchip technology inc. ds31002a-page 2-19 section 2. oscillator oscillator 2 2.9 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the oscillator are: title application note # pic16/17 oscillator design guide an588 low power design using pic16/17 an606
picmicro mid-range mcu family ds31002a-page 2-20 1997 microchip technology inc. 2.10 revision history revision a this is the initial released revision of the picmicro oscillators description.
1997 microchip technology inc. ds31003a page 3-1 m reset 3 section 3. reset highlights this section of the manual contains the following major topics: 3.1 introduction ................................................................................................................ ....3-2 3.2 power-on reset (por), power-up timer (pwrt), oscillator start-up timer (ost), brown-out reset (bor), and parity error reset (per).................................................3-4 3.3 registers and status bit values ...................................................................................3-10 3.4 design tips ................................................................................................................. .3-16 3.5 related application notes............................................................................................3-17 3.6 revision history ...........................................................................................................3 -18
picmicro mid-range mcu family ds31003a-page 3-2 1997 microchip technology inc. 3.1 introduction the reset logic is used to place the device into a known state. the source of the reset can be determined by using the device status bits. the reset logic is designed with features that reduce system cost and increase system reliability. devices differentiate between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) wdt reset during normal operation e) brown-out reset (bor) f) parity error reset (per) most registers are unaffected by a reset; their status is unknown on por and unchanged by all other resets. the other registers are forced to a ?eset state on power-on reset, mclr , wdt reset, brown-out reset, parity error reset, and on mclr reset during sleep. the on-chip parity bits that can be used to verify the contents of program memory. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of nor- mal operation. status bits t o , pd , por , bor , and per are set or cleared differently in different reset situations as indicated in table 3-2 . these bits are used in software to determine the nature of the reset. see table 3-4 for a full description of the reset states of all registers. a simpli?d block diagram of the on-chip reset circuit is shown in figure 3-1 . this block diagram is a superset of reset features. to determine the features that are available on a speci? device, please refer to the devices data sheet. all new devices will have a noise ?ter in the mclr reset path to detect and ignore small pulses. see parameter 30 in the ?lectrical speci?ations section for pulse width speci?ation. note: while the picmicro is in a reset state, the internal phase clock is held at q1 (beginning of an instruction cycle).
1997 microchip technology inc. ds31003a-page 3-3 section 3. reset reset 3 figure 3-1: simpli?d block diagram of a super-set on-chip reset circuit s r q mclr / v pp pin (3) v dd osc1/ wdt module v dd rise detect ost/pwrt on-chip (1) rc osc wdt time-out power-on reset ost pwrt chip_reset 10-bit ripple-counter enable ost enable pwrt (4) sleep see table 3-1 for time-out situations. note 1: this is a separate oscillator from the rc oscillator of the clkin pin or the intrc oscillator. 2: features in dashed boxes not available on all devices, see devices data sheet. 3: in some devices, this pin may be con?ured as a general purpose input. 4: the early picmicro devices have the con?uration bit de?ed as pwrte = 1 is enabled, while all other devices the con?uration bit is de?ed as pwr te = 0 is enabled. brown-out reset boden clkin pin 10-bit ripple-counter program memory parity mpeen mclre weak pull-up (2) v dd mclre i/o pull-up enable (2) (2) (2)
picmicro mid-range mcu family ds31003a-page 3-4 1997 microchip technology inc. 3.2 power-on reset (por), power-up timer (pwrt), oscillator start-up timer (ost), brown-out reset (bor), and parity error reset (per) 3.2.1 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected. to take advantage of the por, just tie the mclr pin directly (or through a resistor) to v dd as shown in figure 3-2 . this will eliminate external rc components usually needed to create a power-on reset. a minimum rise time for v dd is required. see parameter d003 and parameter d004 in the ?lectrical spec- i?ations section for details. figure 3-2: using on-chip por when the device exits the reset condition (begins normal operation), the device operating param- eters (voltage, frequency, temperature, etc.) must be within their operating ranges, otherwise the device will not function correctly. ensure the delay is long enough to get all operating parameters within speci?ation. figure 3-3 shows a possible por circuit for a slow power supply ramp up. the external power-on reset circuit is only required if v dd power-up time is too slow. the diode, d , helps discharge the capacitor quickly when v dd powers down. figure 3-3: external power-on reset circuit (for slow v dd power-up) v dd mclr pic16cxxx v dd r (1) note: the resistor is optional. c r d v dd mclr pic16cxxx v dd note: r < 40 k w is recommended to ensure that the voltage drop across r does not exceed 0.2v. a larger voltage drop will degrade v ih level on the mclr/ v pp pin. v dd
1997 microchip technology inc. ds31003a-page 3-5 section 3. reset reset 3 3.2.2 power-up timer (pwrt) the power-up timer provides a nominal 72 ms delay on power-on reset (por) or brown-out reset (bor), see parameter 33 in the ?lectrical speci?ations section. the power-up timer operates on a dedicated internal rc oscillator. the device is kept in reset as long as the pwrt is active. the pwrt delay allows v dd to rise to an acceptable level. the power-up timer enable con?uration bit can enable/disable the power-up timer. the power-up timer should always be enabled when brown-out reset is enabled. the polarity of the power-up timer con?uration bit is now pwr te = 0 for enabled, while the initial de?ition of the bit was pwrte = 1 for enabled. since all new devices will use the pwr te = 0 for enabled, the text will describe the operation for such devices. please refer to the individual data sheet to ensure the correct polarity for this bit. the power-up time delay will vary from device to device due to v dd , temperature, and process variations. see dc parameters for details. 3.2.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle delay (from osc1 input) after the pwrt delay is over. this ensures that the crystal oscillator or resonator has started and is stable. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset, brown-out reset, or wake-up from sleep. the ost counts the oscillator pulses on the osc1/clkin pin. the counter only starts increment- ing after the amplitude of the signal reaches the oscillator input thresholds. this delay allows the crystal oscillator or resonator to stabilize before the device exits the ost delay. the length of the time-out is a function of the crystal/resonator frequency. figure 3-4 shows the operation of the ost circuit in conjunction with the power-up timer. for low frequency crystals this start-up time can become quite long. that is because the time it takes the low frequency oscillator to start oscillating is longer than the power-up timers delay. so the time from when the power-up timer times-out, to when the oscillator starts to oscillate is a dead time. there is no minimum or maximum time for this dead time ( t deadtime ). figure 3-4: oscillator start-up time v dd mclr oscillator ost time_out pwrt time_out internal reset t osc 1 t ost t pwrt por or bor trip point tosc1 = time for the crystal oscillator to react to an oscillation level detectable by the oscillator start-up timer (ost). t ost = 1024t osc . t deadtime
picmicro mid-range mcu family ds31003a-page 3-6 1997 microchip technology inc. 3.2.4 power-up sequence on power-up, the time-out sequence is as follows: first the internal por is detected, then, if enabled, the pwrt time-out is invoked. after the pwrt time-out is over, the ost is activated. the total time-out will vary based on oscillator con?uration and pwr te bit status. for example, in rc mode with the pwr te bit set (pwrt disabled), there will be no time-out at all. figure 3-5 , figure 3-6 and figure 3-7 depict time-out sequences. since the time-outs occur from the internal por pulse, if mclr is kept low long enough, the time-outs will expire. then bringing mclr high will begin execution immediately ( figure 3-7 ). this is useful for testing purposes or to synchronize more than one device operating in parallel. if the device voltage is not within the electrical speci?ations by the end of a time-out, the mclr/ v pp pin must be held low until the voltage is within the device speci?ation. the use of an external rc delay is suf?ient for many of these applications. table 3-1 shows the time-outs that occur in various situations, while figure 3-5 through figure 3-8 show four different cases that can happen on powering up the device. table 3-1: time-out in various situations figure 3-5: time-out sequence on power-up (mclr tied to v dd ) oscillator con?uration power-up timer brown-out reset wake-up from sleep enabled disabled xt, hs, lp 72 ms + 1024t osc 1024t osc 72 ms + 1024t osc 1024t osc rc 72 ms ? (1) 72 ms ? (1) note 1: devices with the internal/external rc option have a nominal 250 m s delay. t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset
1997 microchip technology inc. ds31003a-page 3-7 section 3. reset reset 3 figure 3-6: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 3-7: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 3-8: slow rise time (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset v dd mclr internal por pwr t time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset 0v 5v t pwrt t ost
picmicro mid-range mcu family ds31003a-page 3-8 1997 microchip technology inc. 3.2.5 brown-out reset (bor) on-chip brown-out reset circuitry places the device into reset when the device voltage falls below a trip point (bv dd ). this ensures that the device does not continue program execution out- side the valid operation range of the device. brown-out resets are typically used in ac line appli- cations or large battery applications where large loads may be switched in (such as automotive), and cause the device voltage to temporarily fall below the speci?d operating minimum. the boden con?uration bit can disable (if clear/programmed) or enable (if set) the brown-out reset circuitry. if v dd falls below bv dd (typically 4.0v, parameter d005 in the ?lectrical spec- i?ations section), for greater than parameter 35 , the brown-out situation will reset the chip. a reset is not guaranteed to occur if v dd falls below bv dd for less than parameter 35 . the chip will remain in brown-out reset until v dd rises above bv dd . the power-up timer will now be invoked and will keep the chip in reset an additional 72 ms. if v dd drops below bv dd while the power-up timer is running, the chip will go back into reset and the power-up timer will be re-initialized. once v dd rises above bv dd , the power-up timer will again start a 72 ms time delay. figure 3-9 shows typical brown-out situations. with the boden bit set, all voltages below bv dd will hold the device in the reset state. this includes during the power-up sequence. figure 3-9: brown-out situations note: before using the on-chip brown-out for a voltage supervisory function (monitor bat- tery decay), please review the electrical speci?ations to ensure that they meet your requirements. 72 ms v dd internal reset bv dd v dd internal reset 72 ms <72 ms 72 ms bv dd v dd internal reset bv dd
1997 microchip technology inc. ds31003a-page 3-9 section 3. reset reset 3 some devices do not have the on-chip brown-out circuit, and in other cases there are some appli- cations where the brown-out reset trip point of the device may not be at the desired level. figure 3-10 and figure 3-11 are two examples of external circuitry that may be implemented. each needs to be evaluated to determine if they match the requirements of the application. figure 3-10: external brown-out protection circuit 1 figure 3-11: external brown-out protection circuit 2 this circuit will activate reset when v dd goes below (vz + 0.7v) where vz = zener voltage. note 1: internal brown-out reset circuitry should be disabled when using this circuit. 2: resistors should be adjusted for the characteristics of the transistor. v dd 33 k w 10 k w 40 k w v dd mclr pic16cxxx q1 r2 40 k w v dd mclr pic16cxxx r1 q1 v dd note 1: this brown-out circuit is less expensive, albeit less accurate. transistor q1 turns off when v dd is below a certain level such that: 2: internal brown-out reset circuitry should be disabled when using this circuit. 3: resistors should be adjusted for the characteristics of the transistor. v dd r1 r1 + r2 = 0.7v
picmicro mid-range mcu family ds31003a-page 3-10 1997 microchip technology inc. 3.3 registers and status bit values table 3-2: status bits and their signi?ance por bor (1) t o pd condition 0x11 power-on reset 0x0x illegal, t o is set on por 0xx0 illegal, pd is set on por 1 (2) 011 brown-out reset 1 (2) 1 (2) 01 wdt reset 1 (2) 1 (2) 00 wdt wake-up 1 (2) 1 (2) uu mclr reset during normal operation 1 (2) 1 (2) 10 mclr reset during sleep legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?? note 1: not all devices have bor circuitry. 2: these bits are unchanged for the given conditions, and when initialized (set) after a por or a bor will read as a '1'.
1997 microchip technology inc. ds31003a-page 3-11 section 3. reset reset 3 table 3-3: initialization condition for special registers condition program counter status register pcon register power-on reset 000h 0001 1xxx u--- -10x mclr reset during normal operation 000h 000u uuuu u--- -uuu mclr reset during sleep 000h 0001 0uuu u--- -uuu wdt reset 000h 0000 1uuu u--- -uuu wdt wake-up pc + 1 uuu0 0uuu u--- -uuu brown-out reset 000h 0001 1uuu u--- -uu0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu u--- -uuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?? note 1: when the wake-up is due to an interrupt and global enable bit, gie, is set the pc is loaded with the interrupt vector (0004h) after execution of pc+1. 2: if a status bit is not implemented, that bit will be read as ??
picmicro mid-range mcu family ds31003a-page 3-12 1997 microchip technology inc. table 3-4: initialization conditions for special function registers register power-on reset brown-out reset mclr reset during: - normal operation - sleep or wdt reset wake-up from sleep through: - interrupt - wdt time-out adcapl 0000 0000 0000 0000 uuuu uuuu adcaph 0000 0000 0000 0000 uuuu uuuu adcon0 0000 00-0 0000 00-0 uuuu uu-u adcon1 ---- -000 ---- -000 ---- -uuu adres xxxx xxxx uuuu uuuu uuuu uuuu adtmrl 0000 0000 0000 0000 uuuu uuuu admrh 0000 0000 0000 0000 uuuu uuuu ccp1con --00 0000 --00 0000 --uu uuuu ccp2con 0000 0000 0000 0000 uuuu uuuu ccpr1l xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h xxxx xxxx uuuu uuuu uuuu uuuu ccpr2l xxxx xxxx uuuu uuuu uuuu uuuu ccpr2h xxxx xxxx uuuu uuuu uuuu uuuu cmcon 00-- 0000 00-- 0000 uu-- uuuu eeadr xxxx xxxx uuuu uuuu uuuu uuuu eecon1 ---0 x000 ---0 q000 ---0 uuuu eecon2 -- - eedata xxxx xxxx uuuu uuuu uuuu uuuu fsr xxxx xxxx uuuu uuuu uuuu uuuu gpio --xx xxxx --uu uuuu --uu uuuu i2cadd 0000 0000 0000 0000 uuuu uuuu i2cbuf xxxx xxxx uuuu uuuu uuuu uuuu i2ccon 0000 0000 0000 0000 uuuu uuuu i2cstat --00 0000 --00 0000 --uu uuuu indf -- - intcon 0000 000x 0000 000u uuuu uuuu (1) lcdcon 00-0 0000 00-0 0000 uu-u uuuu lcdd00 to lcdd15 xxxx xxxx uuuu uuuu uuuu uuuu lcdps ---- 0000 ---- 0000 ---- uuuu lcdse 1111 1111 1111 1111 uuuu uuuu option_reg 1111 1111 1111 1111 uuuu uuuu osccal 0111 00-- uuuu uu-- uuuu uu-- pcl 0000 0000 0000 0000 pc + 1 (2) pclath ---0 0000 ---0 0000 ---u uuuu pcon ---- --0u ---- --uu ---- --uu pie1 0000 0000 0000 0000 uuuu uuuu pie2 ---- ---0 ---- ---0 ---- ---u pir1 0000 0000 0000 0000 uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?? q = value depends on condition. note 1: one or more bits in intcon and/or pir1 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 3-3 for reset value for speci? condition.
1997 microchip technology inc. ds31003a-page 3-13 section 3. reset reset 3 pir2 ---- ---0 ---- ---0 ---- ---u porta --xx xxxx --uu uuuu --uu uuuu portb xxxx xxxx uuuu uuuu uuuu uuuu portc xxxx xxxx uuuu uuuu uuuu uuuu portd xxxx xxxx uuuu uuuu uuuu uuuu porte ---- -xxx ---- -uuu ---- -uuu portf 0000 0000 0000 0000 uuuu uuuu portg 0000 0000 0000 0000 uuuu uuuu pr2 1111 1111 1111 1111 1111 1111 prefa 0000 0000 0000 0000 uuuu uuuu prefb 0000 0000 0000 0000 uuuu uuuu rcsta 0000 -00x 0000 -00x uuuu -uuu rcreg 0000 0000 0000 0000 uuuu uuuu slpcon 0011 1111 0011 1111 uuuu uuuu spbrg 0000 0000 0000 0000 uuuu uuuu sspbuf xxxx xxxx uuuu uuuu uuuu uuuu sspcon 0000 0000 0000 0000 uuuu uuuu sspadd 0000 0000 0000 0000 uuuu uuuu sspstat 0000 0000 0000 0000 uuuu uuuu status 0001 1xxx 000q quuu (3) uuuq quuu (3) t1con --00 0000 --uu uuuu --uu uuuu t2con -000 0000 -000 0000 -uuu uuuu tmr0 xxxx xxxx uuuu uuuu uuuu uuuu tmr1l xxxx xxxx uuuu uuuu uuuu uuuu tmr1h xxxx xxxx uuuu uuuu uuuu uuuu tmr2 0000 0000 0000 0000 uuuu uuuu tris --11 1111 --11 1111 --uu uuuu trisa --11 1111 --11 1111 --uu uuuu trisb 1111 1111 1111 1111 uuuu uuuu trisc 1111 1111 1111 1111 uuuu uuuu trisd 1111 1111 1111 1111 uuuu uuuu trise 0000 -111 0000 -111 uuuu -uuu trisf 1111 1111 1111 1111 uuuu uuuu trisg 1111 1111 1111 1111 uuuu uuuu txreg 0000 0000 0000 0000 uuuu uuuu txsta 0000 -010 0000 -010 uuuu -uuu vrcon 000- 0000 000- 0000 uuu- uuuu w xxxx xxxx uuuu uuuu uuuu uuuu table 3-4: initialization conditions for special function registers (cont.d) register power-on reset brown-out reset mclr reset during: - normal operation - sleep or wdt reset wake-up from sleep through: - interrupt - wdt time-out legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?? q = value depends on condition. note 1: one or more bits in intcon and/or pir1 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 3-3 for reset value for speci? condition.
picmicro mid-range mcu family ds31003a-page 3-14 1997 microchip technology inc. 3.3.1 power control (pcon) and status registers the power control (pcon) register contains a status bit to allow differentiation between a power-on reset (por) to an external mclr reset or wdt reset. it also contains a status bit to determine if a brown-out reset (bor ) occurred. the power control/status register, pcon has up to four bits. the bor (brown-out reset) bit, is unknown on a power-on-reset. it must initially be set by the user and checked on subsequent resets to see if bor = '0' indicating that a brown-out reset has occurred. the bor status bit is a ?on? care bit and is not necessarily predictable if the brown-out circuit is disabled (by clearing the boden bit in the con?uration word). the por (power-on reset) bit, is cleared on a power-on reset and is unaffected otherwise. the user sets this bit following a power-on reset. on subsequent resets if por is ?? it will indicate that a power-on reset must have occurred. the per (parity error reset) bit, is cleared on a parity error reset and must be set by user soft- ware. it will also be set on a power-on reset. the mpeen (memory parity error enable) bit, re?cts the status of the mpeen bit in con?ura- tion word. it is unaffected by any reset or interrupt. register 3-1: pcon register note: bor is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. the bor status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the boden bit in the con?uration word). r-u u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 mpeen per por bor bit 7 bit 0 bit 7 mpeen : memory parity error circuitry status bit this bit re?cts the value of the mpeen con?uration bit. bit 6:3 unimplemented: read as '0' bit 2 per : memory parity error reset status bit 1 = no parity error reset occurred 0 = a program memory fetch parity error occurred (must be set in software after a power-on reset or parity error reset occurs) bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset or power-on reset occurs) legend r = readable bit w = writable bit u = unchanged bit u = unimplemented bit, read as ? - n = value at por reset note: not all bits may be implemented.
1997 microchip technology inc. ds31003a-page 3-15 section 3. reset reset 3 the status register contains two bits (t o and pd ), which when used in conjunction with the pcon register bits provide the user with enough information to determine the cause of the reset. register 3-2: status register r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 t o pd zdc c bit 7 bit 0 bit 7 irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) for devices with only bank0 and bank1 the irp bit is reserved, always maintain this bit clear. bit 6:5 rp1:rp0 : register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes. for devices with only bank0 and bank1 the irp bit is reserved, always maintain this bit clear. bit 4 t o : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borro w bit ( addwf , addlw, sublw, subwf instructions) (for borro w the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0 c : carry/borro w bit ( addwf , addlw,sublw,subwf instructions) 1 = a carry-out from the most signi?ant bit of the result occurred 0 = no carry-out from the most signi?ant bit of the result occurred note: for borro w the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31003a-page 3-16 1997 microchip technology inc. 3.4 design tips question 1: when my system is subjected to an environment with esd and emi, it oper- ates erratically. answer 1: if the device you are using does not have ?tering to the on-chip master clear circuit ( appendix c ), ensure that proper external ?tering is placed on the mclr pin to remove narrow pulses. electri- cal speci?ation parameter 35 speci?s the pulse width required to cause a reset. question 2: with jw (windowed) devices my system resets and operates properly. with an otp device, my system does not operate properly. answer 2: the most common reason for this is that the windowed device (jw) has not had its window cov- ered. the background light causes the device to power-up in a different state than would typically be seen in a device where no light is present. in most cases all the general purpose ram and special function registers were not initialized properly.
1997 microchip technology inc. ds31003a-page 3-17 section 3. reset reset 3 3.5 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to resets are: title application note # power-up trouble shooting an607 power-up considerations an522
picmicro mid-range mcu family ds31003a-page 3-18 1997 microchip technology inc. 3.6 revision history revision a this is the initial released revision of the reset description.
1997 microchip technology inc. ds31004a page 4-1 m architecture 4 section 4. architecture highlights this section of the manual contains the following major topics: 4.1 introduction ................................................................................................................ ....4-2 4.2 clocking scheme/instruction cycle ...............................................................................4-5 4.3 instruction flow/pipelining .............................................................................................4-6 4.4 i/o descriptions ............................................................................................................ .4-7 4.5 design tips ................................................................................................................. .4-12 4.6 related application notes............................................................................................4-13 4.7 revision history ...........................................................................................................4 -14
picmicro mid-range mcu family ds31004a-page 4-2 1997 microchip technology inc. 4.1 introduction the high performance of the picmicro devices can be attributed to a number of architectural features commonly found in risc microprocessors. these include: harvard architecture long word instructions single word instructions single cycle instructions instruction pipelining reduced instruction set register file architecture orthogonal (symmetric) instructions figure 4-2 shows a simple core memory bus arrangement for mid-range mcu devices. harvard architecture: harvard architecture has the program memory and data memory as separate memories and are accessed from separate buses. this improves bandwidth over traditional von neumann architec- ture in which program and data are fetched from the same memory using the same bus. to exe- cute an instruction, a von neumann machine must make one or more (generally more) accesses across the 8-bit bus to fetch the instruction. then data may need to be fetched, operated on, and possibly written. as can be seen from this description, that bus can be extremely conjested. while with a harvard architecture, the instruction is fetched in a single instruction cycle (all 14-bits). while the program memory is being accessed, the data memory is on an independent bus and can be read and written. these separated buses allow one instruction to execute while the next instruction is fetched. a comparison of harvard vs. von-neumann architectures is shown in figure 4-1 . figure 4-1: harvard vs. von neumann block architectures long word instructions: long word instructions have a wider (more bits) instruction bus than the 8-bit data memory bus. this is possible because the two buses are separate. this further allows instructions to be sized differently than the 8-bit wide data word which allows a more ef?ient use of the program mem- ory, since the program memory width is optimized to the architectural requirements. single word instructions: single word instruction opcodes are 14-bits wide making it possible to have all single word instructions. a 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. with single word instructions, the number of words of program memory locations equals the number of instructions for the device. this means that all locations are valid instructions. typically in the von neumann architecture, most instructions are multi-byte. in general, a device with 4-kbytes of program memory would allow approximately 2k of instructions. this 2:1 ratio is generalized and dependent on the application code. since each instruction may take multiple bytes, there is no assurance that each location is a valid instruction. program memory data memory program memory and data cpu cpu 8 8 14 harvard von-neumann
1997 microchip technology inc. ds31004a-page 4-3 section 4. architecture architecture 4 instruction pipeline: the instruction pipeline is a two-stage pipeline which overlaps the fetch and execution of instruc- tions. the fetch of the instruction takes one t cy , while the execution takes another t cy . however, due to the overlap of the fetch of current instruction and execution of previous instruction, an instruction is fetched and another instruction is executed every single t cy . single cycle instructions: with the program memory bus being 14-bits wide, the entire instruction is fetched in a single machine cycle (t cy ). the instruction contains all the information required and is executed in a single cycle. there may be a one cycle delay in execution if the result of the instruction modi?d the contents of the program counter. this requires the pipeline to be ?shed and a new instruc- tion to be fetched. reduced instruction set: when an instruction set is well designed and highly orthogonal (symmetric), fewer instructions are required to perform all needed tasks. with fewer instructions, the whole set can be more rap- idly learned. register file architecture: the register ?es/data memory can be directly or indirectly addressed. all special function regis- ters, including the program counter, are mapped in the data memory. orthogonal (symmetric) instructions: orthogonal instructions make it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ?pecial instructions make programming simple yet ef?ient. in addition, the learning curve is reduced signi?antly. the mid-range instruc- tion set uses only two non-register oriented instructions, which are used for two of the cores fea- tures. one is the sleep instruction which places the device into the lowest power use mode. the other is the clrwdt instruction which veri?s the chip is operating properly by preventing the on-chip watchdog timer (wdt) from over?wing and resetting the device.
picmicro mid-range mcu family ds31004a-page 4-4 1997 microchip technology inc. figure 4-2: general mid-range picmicro block diagram eprom program memory 8k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 368 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss porta portb portc portd porte ra4 ra5 rc0 rc1 rc2 rc3 rc4 rc5 rc6 rc7 8 8 brown-out reset (2) note 1: the high order bits of the direct address for the ram are from the status register. 2: not all devices have this feature, please refer to device data sheet. 3: many of the general purpose i/o pins are multiplexed with one or more peripheral module functions. the multiplexing combinations are device dependent. usarts ccps comparators synchronous a/d timer0 timer1 timer2 serial port ra3 ra2 ra1 ra0 8 3 up to up to rb0/int rb1 rb2 rb3 rb4 rb5 rb6 rb7 rd0 rd1 rd2 rd3 rd4 rd5 rd6 rd7 data eeprom up to 256 x 8 other lcd drivers voltage reference modules peripheral modules (note 3) portf rf0 rf1 rf2 rf3 rf4 rf5 rf6 rf7 portg rg0 rg1 rg2 rg3 rg4 rg5 rg6 rg7 parallel slave port general purpose i/o re0 re1 re2 re3 re4 re5 re6 re7 internal rc clock (2) (note 3)
1997 microchip technology inc. ds31004a-page 4-5 section 4. architecture architecture 4 4.2 clocking scheme/instruction cycle the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3, and q4. internally, the program counter (pc) is incre- mented every q1, and the instruction is fetched from the program memory and latched into the instruction register in q4. the instruction is decoded and executed during the following q1 through q4. the clocks and instruction execution ?w are illustrated in figure 4-3 , and example 4-1 . figure 4-3: clock/instruction cycle q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock t cy 1t cy 2t cy 3
picmicro mid-range mcu family ds31004a-page 4-6 1997 microchip technology inc. 4.3 instruction flow/pipelining an ?nstruction cycle consists of four q cycles (q1, q2, q3, and q4). fetch takes one instruction cycle while decode and execute takes another instruction cycle. however, due to pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g. goto ) then an extra cycle is required to complete the instruction ( example 4-1 ). the instruction fetch begins with the program counter incrementing in q1. in the execution cycle, the fetched instruction is latched into the ?nstruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). example 4-1 shows the operation of the two stage pipeline for the instruction sequence shown. at time t cy 0, the ?st instruction is fetched from program memory. during t cy 1, the ?st instruc- tion executes while the second instruction is fetched. during t cy 2, the second instruction exe- cutes while the third instruction is fetched. during t cy 3, the fourth instruction is fetched while the third instruction ( call sub_1 ) is executed. when the third instruction completes execution, the cpu forces the address of instruction four onto the stack and then changes the program counter (pc) to the address of sub_1 . this means that the instruction that was fetched during t cy 3 needs to be ushed from the pipeline. during t cy 4, instruction four is ?shed (executed as a nop ) and the instruction at address sub_1 is fetched. finally during t cy 5, instruction ?e is executed and the instruction at address sub_1 + 1 is fetched. example 4-1: instruction pipeline flow all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ushed from the pipeline while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush 5. instruction @ address sub_1 fetch sub_1 execute sub_1 fetch sub_1 + 1
1997 microchip technology inc. ds31004a-page 4-7 section 4. architecture architecture 4 4.4 i/o descriptions table 4-1 gives a brief description of the functions that may be multiplexed to a port pin. multiple functions may exist on one port pin. when multiplexing occurs, the peripheral modules functional requirements may force an override of the data direction (tris bit) of the port pin (such as in the a/d and lcd modules). table 4-1: i/o descriptions pin name pin type buffer type description analog input channels an0 i analog an1 i analog an2 i analog an3 i analog an4 i analog an5 i analog an6 i analog an7 i analog an8 i analog an9 i analog an10 i analog an11 i analog an12 i analog an13 i analog an14 i analog an15 i analog a vdd p p analog power a vss p p analog ground c1 i analog lcd voltage generation c2 i analog lcd voltage generation ccp1 i/o st capture1 input/compare1 output/pwm1 output ccp2 i/o st capture2 input/compare2 output/pwm2 output. cdac o analog a/d ramp current source output. normally connected to external capacitor to generate a linear voltage ramp. ck i/o st usart synchronous clock, always associated with tx pin function (see related tx, rx, dt) clkin i st/cmos external clock source input. always associated with pin function osc1. (see related osc1/clkin, osc2/clkout pins) clkout o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. always associated with osc2 pin function. (see related osc2, osc1) cmpa o comparator a output cmpb o comparator b output legend: ttl = ttl-compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels sm = smbus compatible input. an external resistor is required if this pin is used as an output npu = n-channel pull-up pu = weak internal pull-up no-p diode = no p-diode to v dd an = analog input or output i = input o = output p = power l = lcd driver
picmicro mid-range mcu family ds31004a-page 4-8 1997 microchip technology inc. com0 l lcd common driver0 com1 l lcd common driver1 com2 l lcd common driver2 com3 l lcd common driver3 cs i ttl chip select control for parallel slave port (see related rd and wr ) dt i/o st usart synchronous data. always associated rx pin function. (see related rx, tx, ck) gp is a bi-directional i/o port. some pins of port gp can be software programmed for internal weak pull-ups on the inputs. gp0 i/o ttl/st ttl input buffer as general purpose i/o, schmitt trigger input buffer when used as the serial programming mode. gp1 i/o ttl/st ttl input buffer as general purpose i/o, schmitt trigger input buffer when used as the serial programming mode. gp2 i/o st gp3 i ttl gp4 i/o ttl gp5 i/o ttl int i st external interrupt mclr /v pp i/p st master clear (reset) input or programming voltage input. this pin is an active low reset to the device. nc these pins should be left unconnected. osc1 i st/cmos oscillator crystal input or external clock source input. st buffer when con?ured in rc mode. cmos otherwise. osc2 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. pbtn i st input with weak pull-up resistor, can be used to generate an interrupt. psp0 i/o ttl parallel slave port for interfacing to a microprocessor port. these pins have ttl input buffers when psp module is enabled. psp1 i/o ttl psp2 i/o ttl psp3 i/o ttl psp4 i/o ttl psp5 i/o ttl psp6 i/o ttl psp7 i/o ttl porta is a bi-directional i/o port. ra0 i/o ttl ra1 i/o ttl ra2 i/o ttl ra3 i/o ttl ra4 i/o st ra4 is an open drain when con?ured as output. ra5 i/o ttl table 4-1: i/o descriptions (cont.d) pin name pin type buffer type description legend: ttl = ttl-compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels sm = smbus compatible input. an external resistor is required if this pin is used as an output npu = n-channel pull-up pu = weak internal pull-up no-p diode = no p-diode to v dd an = analog input or output i = input o = output p = power l = lcd driver
1997 microchip technology inc. ds31004a-page 4-9 section 4. architecture architecture 4 portb is a bi-directional i/o port. portb can be software pro- grammed for internal weak pull-ups on all inputs. rb0 i/o ttl rb1 i/o ttl rb2 i/o ttl rb3 i/o ttl rb4 i/o ttl interrupt on change pin. rb5 i/o ttl interrupt on change pin. rb6 i/o ttl/st interrupt on change pin. serial programming clock. ttl input buffer as general purpose i/o, schmitt trigger input buffer when used as the serial programming clock. rb7 i/o ttl/st interrupt on change pin. serial programming data. ttl input buffer as general purpose i/o, schmitt trigger input buffer when used as the serial programming data. portc is a bi-directional i/o port. rc0 i/o st rc1 i/o st rc2 i/o st rc3 i/o st rc4 i/o st rc5 i/o st rc6 i/o st rc7 i/o st rd i ttl read control for parallel slave port (see also wr and cs pins) portd is a bi-directional i/o port. rd0 i/o st rd1 i/o st rd2 i/o st rd3 i/o st rd4 i/o st rd5 i/o st rd6 i/o st rd7 i/o st porte is a bi-directional i/o port. re0 i/o st re1 i/o st re2 i/o st re3 i/o st re4 i/o st re5 i/o st re6 i/o st re7 i/o st table 4-1: i/o descriptions (cont.d) pin name pin type buffer type description legend: ttl = ttl-compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels sm = smbus compatible input. an external resistor is required if this pin is used as an output npu = n-channel pull-up pu = weak internal pull-up no-p diode = no p-diode to v dd an = analog input or output i = input o = output p = power l = lcd driver
picmicro mid-range mcu family ds31004a-page 4-10 1997 microchip technology inc. refa o cmos programmable reference a output. refb o cmos programmable reference b output. portf is a digital input or lcd segment driver port rf0 i/o st rf1 i/o st rf2 i/o st rf3 i/o st rf4 i/o st rf5 i/o st rf6 i/o st rf7 i/o st portg is a digital input or lcd segment driver port rg0 i/o st rg1 i/o st rg2 i/o st rg3 i/o st rg4 i/o st rg5 i/o st rg6 i/o st rg7 i/o st rx i st usart asynchronous receive scl i/o st synchronous serial clock input/output for i 2 c mode. scla i/o st synchronous serial clock for i 2 c interface. sclb i/o st synchronous serial clock for i 2 c interface. sda i/o st i 2 c data i/o sdaa i/o st synchronous serial data i/o for i 2 c interface sdab i/o st synchronous serial data i/o for i 2 c interface sck i/o st synchronous serial clock input/output for spi mode. sdi i st spi data in sdo o spi data out (spi mode) ss i st spi slave select input seg00 to seg31 i/l st lcd segment driver00 through driver31. sum o an an1 summing junction output. this pin can be connected to an exter- nal capacitor for averaging small duration pulses. t0cki i st timer0 external clock input t1cki i st timer1 external clock input t1oso o cmos timer1 oscillator output t1osi i cmos timer1 oscillator input tx o usart asynchronous transmit (see related rx) table 4-1: i/o descriptions (cont.d) pin name pin type buffer type description legend: ttl = ttl-compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels sm = smbus compatible input. an external resistor is required if this pin is used as an output npu = n-channel pull-up pu = weak internal pull-up no-p diode = no p-diode to v dd an = analog input or output i = input o = output p = power l = lcd driver i 2 c is a trademark of philips corporation.
1997 microchip technology inc. ds31004a-page 4-11 section 4. architecture architecture 4 v lcd 1 p lcd voltage v lcd 2 p lcd voltage v lcd 3 p lcd voltage vlcdadj i analog lcd voltage generation v ref i analog analog high voltage reference input. dr reference voltage output on devices with comparators. v ref + i analog analog high voltage reference input. usually multiplexed onto an analog pin. v ref - i analog analog low voltage reference input. usually multiplexed onto an analog pin. vreg o this pin is an output to control the gate of an external n-fet for voltage regulation. v ss p ground reference for logic and i/o pins. v dd p positive supply for logic and i/o pins. wr i ttl write control for parallel slave port (see cs and rd pins also). table 4-1: i/o descriptions (cont.d) pin name pin type buffer type description legend: ttl = ttl-compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels sm = smbus compatible input. an external resistor is required if this pin is used as an output npu = n-channel pull-up pu = weak internal pull-up no-p diode = no p-diode to v dd an = analog input or output i = input o = output p = power l = lcd driver
picmicro mid-range mcu family ds31004a-page 4-12 1997 microchip technology inc. 4.5 design tips no related design tips at this time.
1997 microchip technology inc. ds31004a-page 4-13 section 4. architecture architecture 4 4.6 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to architecture are: title application note # no related application notes at this time.
picmicro mid-range mcu family ds31004a-page 4-14 1997 microchip technology inc. 4.7 revision history revision a this is the initial released revision of the picmicros architecture description.
1997 microchip technology inc. ds31005a page 5-1 m cpu and alu 5 section 5. cpu and alu highlights this section of the manual contains the following major topics: 5.1 introduction ................................................................................................................ ....5-2 5.2 general instruction format ............................................................................................5-4 5.3 central processing unit (cpu) ......................................................................................5-4 5.4 instruction clock ........................................................................................................... .5-4 5.5 arithmetic logical unit (alu).........................................................................................5-5 5.6 status register ...........................................................................................................5- 6 5.7 option_reg register .................................................................................................5-8 5.8 pcon register ..............................................................................................................5 -9 5.9 design tips ................................................................................................................. .5-10 5.10 related application notes............................................................................................5-11 5.11 revision history ........................................................................................................... 5-12
picmicro mid-range mcu family ds31005a-page 5-2 1997 microchip technology inc. 5.1 introduction the central processing unit (cpu) is responsible for using the information in the program mem- ory (instructions) to control the operation of the device. many of these instructions operate on data memory. to operate on data memory, the arithmetic logical unit (alu) is required. in addi- tion to performing arithmetical and logical operations, the alu controls status bits (which are found in the status register). the result of some instructions force status bits to a value depend- ing on the state of the result. the machine codes that the cpu recognizes are show in table 5-1 (as well as the instruction mnemonics that the mpasm uses to generate these codes).
1997 microchip technology inc. ds31005a-page 5-3 section 5. cpu and alu cpu and alu 5 table 5-1: mid-range mcu instruction set mnemonic, operands description cycles 14-bit instruction word status bits affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff- bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z t o , pd z t o , pd c,dc,z z note 1: when an i/o register is modi?d as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin con?ured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modi?d or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop.
picmicro mid-range mcu family ds31005a-page 5-4 1997 microchip technology inc. 5.2 general instruction format the mid-range mcu instructions can be broken down into four general formats as shown in figure 5-1 . as can be seen the opcode for the instruction varies from 3-bits to 6-bits. this variable opcode size is what allows 35 instructions to be implemented. figure 5-1: general format for instructions 5.3 central processing unit (cpu) the cpu can be thought of as the ?rains of the device. it is responsible for fetching the correct instruction for execution, decoding that instruction, and then executing that instruction. the cpu sometimes works in conjunction with the alu to complete the execution of the instruc- tion (in arithmetic and logical operations). the cpu controls the program memory address bus, the data memory address bus, and accesses to the stack. 5.4 instruction clock each instruction cycle (t cy ) is comprised of four q cycles (q1-q4). the q cycle time is the same as the device oscillator cycle time (t osc ). the q cycles provide the timing/designation for the decode, read, process data, write, etc., of each instruction cycle. the following diagram shows the relationship of the q cycles to the instruction cycle. the four q cycles that make up an instruction cycle (t cy ) can be generalized as: q1: instruction decode cycle or forced no operation q2: instruction read data cycle or no operation q3: process the data q4: instruction write data cycle or no operation each instruction will show a detailed q cycle operation for the instruction. figure 5-2: q cycle activity byte-oriented ?e register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit ?e register address bit-oriented ?e register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit ?e register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 t cy 1t cy 2t cy 3 tosc
1997 microchip technology inc. ds31005a-page 5-5 section 5. cpu and alu cpu and alu 5 5.5 arithmetic logical unit (alu) picmicro mcus contain an 8-bit alu and an 8-bit working register. the alu is a general pur- pose arithmetic and logical unit. it performs arithmetic and boolean functions between the data in the working register and any register ?e. figure 5-3: operation of the alu and w register the alu is 8-bits wide and is capable of addition, subtraction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's complement in nature. in two-operand instructions, typically one operand is the working register (w register). the other operand is a ?e register or an immediate constant. in single operand instructions, the operand is either the w reg- ister or a ?e register. the w register is an 8-bit working register used for alu operations. it is not an addressable reg- ister. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borro w bit and a digit borro w out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. w register register file 8 d bit, or from instruction 8 8 8-bit literal (from instruction word) d = '0' or d = '1' (sfrs) and general purpose ram (gpr) alu literal instructions 8 8 special function registers 8-bit register value (from direct or indirect address of instruction)
picmicro mid-range mcu family ds31005a-page 5-6 1997 microchip technology inc. 5.6 status register the status register, shown in figure 5-1 , contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. since the selection of the data memory banks is controlled by this register, it is required to be present in every bank. also, this register is in the same relative position (offset) in each bank (see figure 6-5: ?egister file map in the ?em- ory organization section). the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. fur- thermore, the t o and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register because these instructions do not affect the z, c or dc bits from the status register. for other instructions, not affecting any status bits, see table 5-1 . note 1: some devices do not require the irp and rp1 (status<7:6>) bits. these bits are not used by the section 5. cpu and alu and should be maintained clear. use of these bits as general purpose r/w bits is not recommended, since this may affect upward code compatibility with future products. note 2: the c and dc bits operate as a borro w and digit borro w bit, respectively, in subtrac- tion.
1997 microchip technology inc. ds31005a-page 5-7 section 5. cpu and alu cpu and alu 5 register 5-1: status register r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 t o pd zdc c bit 7 bit 0 bit 7 irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) for devices with only bank0 and bank1 the irp bit is reserved, always maintain this bit clear. bit 6:5 rp1:rp0 : register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes. for devices with only bank0 and bank1 the irp bit is reserved, always maintain this bit clear. bit 4 t o : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borro w bit ( addwf , addlw, sublw, subwf instructions) (for borro w the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0 c : carry/borro w bit ( addwf , addlw,sublw,subwf instructions) 1 = a carry-out from the most signi?ant bit of the result occurred 0 = no carry-out from the most signi?ant bit of the result occurred note: for borro w the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31005a-page 5-8 1997 microchip technology inc. 5.7 option_reg register the option_reg register is a readable and writable register which contains various control bits to con?ure the tmr0/wdt prescaler, the external int interrupt, tmr0, and the weak pull-ups on portb. register 5-2: option_reg register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg : interrupt edge select bit 1 = interrupt on rising edge of int pin 0 = interrupt on falling edge of int pin bit 5 t0cs : tmr0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0 : prescaler rate select bits legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer.
1997 microchip technology inc. ds31005a-page 5-9 section 5. cpu and alu cpu and alu 5 5.8 pcon register the power control (pcon) register contains ?g bit(s), that together with the to and pd bits, allows the user to differentiate between the device resets. register 5-3: pcon register note 1: bor is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. the bor status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the boden bit in the con?uration word). note 2: it is recommended that the por bit be cleared after a power-on reset has been detected, so that subsequent power-on resets may be detected. r-u u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 mpeen per por bor bit 7 bit 0 bit 7 mpeen : memory parity error circuitry status bit this bit re?cts the value of the mpeen con?uration bit. bit 6:3 unimplemented: read as '0' bit 2 per : memory parity error reset status bit 1 = no error occurred 0 = a program memory fetch parity error occurred (must be set in software after a power-on reset occurs) bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31005a-page 5-10 1997 microchip technology inc. 5.9 design tips question 1: my program algorithm does not seem to function correctly. answer 1: 1. the destination of the instruction may be specifying the w register (d = 0) instead of the ?e register (d = 1). 2. the register bank select bits (rp1:rp0 or irp) may not be properly selected. also if inter- rupts are used, the register bank select bits may not be properly restored when exiting the interrupt handler. question 2: i cannot seem to modify the status register ?gs. answer 2: if the status register is the destination for an instruction that affects the z, dc, or c bits, the write to these bits is disabled. these bits are set or cleared based on device logic. therefore, to modify bits in the status register it is recommended to use the bcf and bsf instructions.
1997 microchip technology inc. ds31005a-page 5-11 section 5. cpu and alu cpu and alu 5 5.10 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the cpu or the alu are: title application note # fixed point routines an617 ieee 754 compliant floating point routines an575 digital signal processing with the pic16c74 an616 math utility routines an544 implementing iir digital filters an540 implementation of fast fourier transforms an542 tone generation an543 servo control of a dc brushless motor an532 implementation of the data encryption standard using the pic17c42 an583 pic16c5x / pic16cxx utility math routines an526 real time operating system for pic16/17 an585
picmicro mid-range mcu family ds31005a-page 5-12 1997 microchip technology inc. 5.11 revision history revision a this is the initial released revision of the cpu and alu description.
1997 microchip technology inc. ds31006a page 6-1 memory organization 6 m section 6. memory organization highlights this section of the manual contains the following major topics: 6.1 introduction ................................................................................................................ ....6-2 6.2 program memory organization......................................................................................6-2 6.3 data memory organization ............................................................................................6-8 6.4 initialization .............................................................................................................. ....6-14 6.5 design tips ................................................................................................................. .6-16 6.6 related application notes............................................................................................6-17 6.7 revision history ...........................................................................................................6 -18
picmicro mid-range mcu family ds31006a-page 6-2 1997 microchip technology inc. 6.1 introduction there are two memory blocks in the section 6. memory organization; program memory and data memory. each block has its own bus, so that access to each block can occur during the same oscillator cycle. the data memory can further be broken down into general purpose ram and the special func- tion registers (sfrs). the operation of the sfrs that control the ?ore are described here. the sfrs used to control the peripheral modules are described in the section discussing each indi- vidual peripheral module. 6.2 program memory organization mid-range mcu devices have a 13-bit program counter capable of addressing an 8k x 14 pro- gram memory space. the width of the program memory bus (instruction word) is 14-bits. since all instructions are a single word, a device with an 8k x 14 program memory has space for 8k of instructions. this makes it much easier to determine if a device has suf?ient program memory for a desired application. this program memory space is divided into four pages of 2k words each (0h - 7ffh, 800h - fffh, 1000h - 17ffh, and 1800h - 1fffh). figure 6-1 shows the program memory map as well as the 8 level deep hardware stack. depending on the device, only a portion of this memory may be implemented. please refer to the device data sheet for the available memory. to jump between the program memory pages, the high bits of the program counter (pc) must be modi?d. this is done by writing the desired value into a sfr called pclath ( p rogram c ounter lat ch h igh). if sequential instructions are executed, the program counter will cross the page boundaries without any user intervention. for devices that have less than 8k words, accessing a location above the physically implemented address will cause a wraparound. that is, in a 4k-word device accessing 17ffh actually addresses 7ffh. 2k-word devices (or less) do not require paging.
1997 microchip technology inc. ds31006a-page 6-3 section 6. memory organization memory organization 6 figure 6-1: architectural program memory map and stack pc<12:8> 13 0000h 0004h 0005h 07ffh 0800h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program on-chip program memory (page 1) memory (page 0) call, return retfie, retlw on-chip program memory (page 2) on-chip program memory (page 3) 0fffh 1000h 17ffh 1800h 2k 4k 6k 8k pc<12:0> pcl pclath note 1: not all devices implement the entire program memory space 2: calibration data may be programmed into program memory locations.
picmicro mid-range mcu family ds31006a-page 6-4 1997 microchip technology inc. 6.2.1 reset vector on any device, a reset forces the program counter (pc) to address 0h. we call this address the ?eset vector address since this is the address that program execution will branch to when a device reset occurs. any reset will also clear the contents of the pclath register. this means that any branch at the reset vector address (0h) will jump to that location in page0 of the program memory. 6.2.2 interrupt vector when an interrupt is acknowledged the pc is forced to address 0004h. we call this the ?nterrupt vector address? when the pc is forced to the interrupt vector, the pclath register is not mod- i?d. once in the service interrupt routine (isr), this means that before any write to the pc, the pclath register should be written with the value that will specify the desired location in program memory. before the pclath register is modi?d by the interrupt service routine (isr) the con- tents of the pclath may need to be saved, so it can be restored before returning from the isr. 6.2.3 calibration information some devices have calibration information stored in their program memory. this information is programmed by microchip when the device is under ?al test. the use of these values allows the application to achieve better results. the calibration information is typically at the end of program memory, and is implemented as a retlw instruction with the literal value being the speci?d cal- ibration information. note: for windowed devices, write down all calibration values before erasing. this allows the devices calibration values to be restored when the device is re-pro- grammed. when possible writing the values on the package is recommended.
1997 microchip technology inc. ds31006a-page 6-5 section 6. memory organization memory organization 6 6.2.4 program counter (pc) the program counter (pc) speci?s the address of the instruction to fetch for execution. the pc is 13-bits wide. the low byte is called the pcl register. this register is readable and writable. the high byte is called the pch register. this register contains the pc<12:8> bits and is not directly readable or writable. all updates to the pch register go through the pclath register. figure 6-2 shows the four situations for the loading of the pc. situation 1 shows how the pc is loaded on a write to pcl (pclath<4:0> ? pch). situation 2 shows how the pc is loaded during a goto instruction (pclath<4:3> ? pch). situation 3 shows how the pc is loaded during a call instruction (pclath<4:3> ? pch), with the pc loaded (pushed) onto the top of stack. situation 4 shows how the pc is loaded during one of the return instructions where the pc loaded (poped) from the top of stack. figure 6-2: loading of pc in different situations pc 12 8 7 0 5 pclath<4:0> pclath alu result opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl situation 1 - instruction with pcl as destination situation 2 - goto instruction stack (13-bits x 8) top of stack stack (13-bits x 8) top of stack opcode <10:0> pc 12 11 10 0 11 pclath<4:3> 87 2 pclath pch pcl situation 3 - call instruction stack (13-bits x 8) top of stack opcode <10:0> pc 12 11 10 0 11 87 pclath pch pcl situation 4 - return , retfie , or retlw instruction stack (13-bits x 8) top of stack 13 13 note: pclath is never updated with the contents of pch.
picmicro mid-range mcu family ds31006a-page 6-6 1997 microchip technology inc. 6.2.4.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256 byte block). 6.2.5 stack the stack allows a combination of up to 8 program calls and interrupts to occur. the stack con- tains the return address from this branch in program execution. mid-range mcu devices have an 8-level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not modi?d when the stack is pushed or poped. after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the ?st push. the tenth push overwrites the second push (and so on). an example of the overwriting of the stack is shown in figure 6-3 . figure 6-3: stack modi?ation note: any write to the program counter (pcl), will cause the lower ?e bits of the pclath to be loaded into pch. push1 push9 push2 push10 push3 push4 push5 push6 push7 push8 top of stack stack note 1: there are no status bits to indicate stack over?w or stack under?w conditions. note 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw, and retfie instructions, or the vectoring to an interrupt address.
1997 microchip technology inc. ds31006a-page 6-7 section 6. memory organization memory organization 6 6.2.6 program memory paging some devices have program memory sizes greater then 2k words, but the call and goto instructions only have a 11-bit address range. this 11-bit address range allows a branch within a 2k program memory page size. to allow call and goto instructions to address the entire 1k program memory address range, there must be another two bits to specify the program memory page. these paging bits come from the pclath<4:3> bits ( figure 6-2 ). when doing a call or goto instruction, the user must ensure that page bits (pclath<4:3>) are programmed so that the desired program memory page is addressed ( figure 6-2 ). when one of the return instruc- tions is executed, the entire 13-bit pc is poped from the stack. therefore, manipulation of the pclath<4:3> is not required for the return instructions. example 6-1 shows the calling of a subroutine in page 1 of the program memory. this example assumes that pclath is saved and restored by the interrupt service routine (if interrupts are used). example 6-1: call of a subroutine in page1 from page0 note: devices with program memory sizes 2k words and less, ignore both paging bits (pclath<4:3>), which are used to access program memory when more than one page is available. the use of pclath<4:3> as general purpose read/write bits (for these devices) is not recommended since this may affect upward compatibility with future products. devices with program memory sizes between 2k words and 4k words, ignore the paging bit (pclath<4>), which is used to access program memory pages 2 and 3 (1000h - 1fffh). the use of pclath<4> as a general purpose read/write bit (for these devices) is not recommended since this may affect upward compatibility with future products. org 0x500 bsf pclath,3 ; select page1 (800h-fffh) call sub1_p1 ; call subroutine in page1 (800h-fffh) : ; : ; org 0x900 ; sub1_p1: ; called subroutine page1 (800h-fffh) : ; return ; return to call subroutine in page0 (000h-7ffh) ;
picmicro mid-range mcu family ds31006a-page 6-8 1997 microchip technology inc. 6.3 data memory organization data memory is made up of the special function registers (sfr) area, and the general pur- pose registers (gpr) area. the sfrs control the operation of the device, while gprs are the general area for data storage and scratch pad operations. the data memory is banked for both the gpr and sfr areas. the gpr area is banked to allow greater than 96 bytes of general purpose ram to be addressed. sfrs are for the registers that control the peripheral and core functions. banking requires the use of control bits for bank selec- tion. these control bits are located in the status register (status<7:5>). figure 6-5 shows one of the data memory map organizations, this organization is device dependent. to move values from one register to another register, the value must pass through the w register. this means that for all register-to-register moves, two instruction cycles are required. the entire data memory can be accessed either directly or indirectly. direct addressing may require the use of the rp1:rp0 bits. indirect addressing requires the use of the file select reg- ister (fsr). indirect addressing uses the indirect register pointer (irp) bit of the status regis- ter for accesses into the bank0 / bank1 or the bank2 / bank3 areas of data memory. 6.3.1 general purpose registers (gpr) some mid-range mcu devices have banked memory in the gpr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. the register ?e can be accessed either directly, or using the file select register fsr, indirectly. some devices have areas that are shared across the data memory banks, so a read / write to that area will appear as the same location (value) regardless of the current bank. we refer to this area as the common ram. 6.3.2 special function registers (sfr) the sfrs are used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. the sfrs can be classi?d into two sets, those associated with the ?ore function and those related to the peripheral functions. those registers related to the ?ore are described in this sec- tion, while those related to the operation of the peripheral features are described in the section of that peripheral feature. all mid-range mcu devices have banked memory in the sfr area. switching between these banks requires the rp0 and rp1 bits in the status register to be con?ured for the desired bank. some sfrs are initialized by a power-on reset and other resets, while other sfrs are unaffected. the register ?e can be accessed either directly, or using the file select register fsr, indirectly. note: the special function register (sfr) area may have general purpose registers (gprs) mapped in these locations.
1997 microchip technology inc. ds31006a-page 6-9 section 6. memory organization memory organization 6 6.3.3 banking the data memory is partitioned into four banks. each bank contains general purpose registers and special function registers. switching between these banks requires the rp0 and rp1 bits in the status register to be con?ured for the desired bank when using direct addressing. the irp bit in the status register is used for indirect addressing. table 6-1: direct and indirect addressing of banks each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function registers are general purpose regis- ters. all data memory is implemented as static ram. all banks may contain special function reg- isters. some ?igh use special function registers from bank0 are mirrored in the other banks for code reduction and quicker access. through the evolution of the products, there are a few variations in the layout of the data memory. the data memory organization that will be the standard for all new devices is shown in figure 6-5 . this memory map has the last 16-bytes mapped across all memory banks. this is to reduce the software overhead for context switching. the registers in bold will be in every device. the other registers are peripheral dependent. not every peripherals registers are shown, because some ?e addresses have a different registers from those shown. as with all the ?ures, tables, and speci?ations presented in this reference guide, verify the details with the device spe- ci? data sheet. figure 6-4: direct addressing accessed bank direct (rp1:rp0) indirect (irp) 00 0 0 10 1 21 0 1 31 1 data memory direct addressing bank select location select rp1 rp0 6 0 from opcode 00 01 10 11 7fh 00h 7fh bank0 bank1 bank2 bank3
picmicro mid-range mcu family ds31006a-page 6-10 1997 microchip technology inc. figure 6-5: register file map file address file address file address file address indf 00h indf 80h indf 100h indf 180h tmr0 01h option_reg 81h tmr0 101h option_reg 181h pcl 02h pcl 82h pcl 102h pcl 182h status 03h status 83h status 103h status 183h fsr 04h fsr 84h fsr 104h fsr 184h porta 05h trisa 85h 105h 185h portb 06h trisb 86h portb 106h trisb 186h portc 07h trisc 87h portf 107h trisf 187h portd 08h trisd 88h portg 108h trisg 188h porte 09h trise 89h 109h 189h pclath 0ah pclath 8ah pclath 10ah pclath 18ah intcon 0bh intcon 8bh intcon 10bh intcon 18bh pir1 0ch pie1 8ch 10ch 18ch pir2 0dh pie2 8dh 10dh 18dh tmr1l 0eh pcon 8eh 10eh 18eh tmr1h 0fh osccal 8fh 10fh 18fh t1con 10h 90h 110h 190h tmr2 11h 91h 111h 191h t2con 12h pr2 92h 112h 192h sspbuf 13h sspadd 93h 113h 193h sspcon 14h ss patat 9 4 h 114h 194h ccpr1l 15h 95h 115h 195h ccpr1h 16h 96h 116h 196h ccp1con 17h 97h 117h 197h rcsta 18h txsta 98h 118h 198h txreg 19h spbrg 99h 119h 199h rcreg 1ah 9ah 11ah 19ah ccpr2l 1bh 9bh 11bh 19bh ccpr2h 1ch 9ch 11ch 19ch ccp2con 1dh 9dh 11dh 19dh adres 1eh 9eh 11eh 19eh adcon0 1fh adcon1 9fh 11fh 19fh general purpose registers (2) 20h general purpose registers (3) a0h efh general purpose registers (3) 120h 16fh general purpose registers (3) 1a0h 1efh 7fh mapped in bank0 70h - 7fh (4) f0h ffh mapped in bank0 70h - 7fh (4) 170h 17fh mapped in bank0 70h - 7fh (4) 1f0h 1ffh bank0 bank1 bank2 (5) bank3 (5) note 1: registers in bold will be present in every device. 2: not all locations may be implemented. unimplemented locations will read as '0'. 3: these locations may not be implemented. depending on the device, accesses to the unimplemented loca- tions operate differently. please refer to the speci? device data sheet for details. 4: some device do not map these registers into bank0. in devices where these registers are mapped into bank0, these registers are referred to as common ram 5: some devices may not implement these banks. locations in unimplemented banks will read as ?? 6: general purpose registers (gprs) may be located in the special function register (sfr) area.
1997 microchip technology inc. ds31006a-page 6-11 section 6. memory organization memory organization 6 the map in figure 6-6 shows the register ?e memory map of some 18-pin devices. unimplemented registers will read as '0'. figure 6-6: register file map file address file address indf 00h indf 80h tmr0 01h option_reg 81h pcl 02h pcl 82h status 03h status 83h fsr 04h fsr 84h porta 05h trisa 85h portb 06h trisb 86h 07h pcon 87h adcon0 / eedata (2) 08h adcon1 / eecon1 (2) 88h adres / eeadr (2) 09h adres / eecon2 (2) 89h pclath 0ah pclath 8ah intcon 0bh intcon 8bh general purpose registers (3) 0ch 7fh general purpose registers (4) 8ch ffh bank0 bank1 note 1: registers in bold will be present in every device. 2: these registers may not be implemented, or are implemented as other registers in some devices. 3: not all locations may be implemented. unimplemented locations will read as ?? 4: these locations are unimplemented in bank1. access to these unimplemented locations will access the corresponding bank0 register.
picmicro mid-range mcu family ds31006a-page 6-12 1997 microchip technology inc. 6.3.4 indirect addressing, indf, and fsr registers indirect addressing is a mode of addressing data memory where the data memory address in the instruction is not ?ed. an sfr register is used as a pointer to the data memory location that is to be read or written. since this pointer is in ram, the contents can be modi?d by the pro- gram. this can be useful for data tables in the data memory. figure 6-7 shows the operation of indirect addressing. this shows the moving of the value to the data memory address speci?d by the value of the fsr register. indirect addressing is possible by using the indf register. any instruction using the indf register actually accesses the register pointed to by the file select register, fsr. reading the indf reg- ister itself indirectly (fsr = '0') will read 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). an effective 9-bit address is generated by the concatenation of the irp bit (status<7>) with the 8-bit fsr register, as shown in figure 6-8 . figure 6-7: indirect addressing opcode address file address = indf fsr instruction executed instruction fetched ram opcode file irp rp1:rp0 9 9 7 2 9 address = 0h address != 0
1997 microchip technology inc. ds31006a-page 6-13 section 6. memory organization memory organization 6 figure 6-8: indirect addressing example 6-2 shows a simple use of indirect addressing to clear ram (locations 20h-2fh) in a minimum number of instructions. a similar concept could be used to move a de?ed number of bytes (block) of data to the usart transmit register (txreg). the starting address of the block of data to be transmitted could easily be modi?d by the program. example 6-2: indirect addressing data memory indirect addressing irp fsr register 7 0 bank select location select 00 01 10 11 00h 7fh 00h 7fh bank0 bank1 bank2 bank3 bcf status, irp ; indirect addressing bank0/1 movlw 0x20 ; initialize pointer to ram movwf fsr ; next clrf indf ; clear indf register incf fsr,f ; inc pointer btfss fsr,4 ; all done? goto next ; no, clear next continue ; : ; yes, continue
picmicro mid-range mcu family ds31006a-page 6-14 1997 microchip technology inc. 6.4 initialization example 6-3 shows how the bank switching occurs for direct addressing, while example 6-4 shows some code to do initialization (clearing) of general purpose ram. example 6-3: bank switching clrf status ; clear status register (bank0) : ; bsf status, rp0 ; bank1 : ; bcf status, rp0 ; bank0 : ; movlw 0x60 ; set rp0 and rp1 in status register, other xorwf status, f ; bits unchanged (bank3) : ; bcf status, rp0 ; bank2 : ; bcf status, rp1 ; bank0
1997 microchip technology inc. ds31006a-page 6-15 section 6. memory organization memory organization 6 example 6-4: ram initialization clrf status ; clear status register (bank0) movlw 0x20 ; 1st address (in bank) of gpr area movwf fsr ; move it to indirect address register bank0_lp clrf indf0 ; clear gpr at address pointed to by fsr incf fsr ; next gpr (ram) address btfss fsr, 7 ; end of current bank ? (fsr = 80h, c = 0) goto bank0_lp ; no, clear next location ; ; next bank (bank1) ; (** only required if device has a bank1 **) ; movlw 0xa0 ; 1st address (in bank) of gpr area movwf fsr ; move it to indirect address register bank1_lp clrf indf0 ; clear gpr at address pointed to by fsr incf fsr ; next gpr (ram) address btfss status, c ; end of current bank? (fsr = 00h, c = 1) goto bank1_lp ; no, clear next location ; ; next bank (bank2) ; (** only required if device has a bank2 **) ; bsf status, irp ; select bank2 and bank3 ; for indirect addressing movlw 0x20 ; 1st address (in bank) of gpr area movwf fsr ; move it to indirect address register bank2_lp clrf indf0 ; clear gpr at address pointed to by fsr incf fsr ; next gpr (ram) address btfss fsr, 7 ; end of current bank? (fsr = 80h, c = 0) goto bank2_lp ; no, clear next location ; ; next bank (bank3) ; (** only required if device has a bank3 **) ; movlw 0xa0 ; 1st address (in bank) of gpr area movwf fsr ; move it to indirect address register bank3_lp clrf indf0 ; clear gpr at address pointed to by fsr incf fsr ; next gpr (ram) address btfss status, c ; end of current bank? (fsr = 00h, c = 1) goto bank3_lp ; no, clear next location : ; yes, all gprs (ram) is cleared
picmicro mid-range mcu family ds31006a-page 6-16 1997 microchip technology inc. 6.5 design tips question 1: program execution seems to get lost. answer 1: when a device with more then 2k words of program memory is used, the calling of subroutines may require that the pclath register be loaded prior to the call (or goto ) instruction to specify the correct program memory page that the routine is located on. the following instructions will correctly load pclath register, regardless of the program memory location of the label sub_1 . movlw high (sub_1) ; select program memory page of movwf pclath ; routine. call sub_1 ; call the desired routine : : sub_1 : ; start of routine : return ; return from routine question 2: i need to initialize ram to ?s. what is an easy way to do that? answer 2: example 6-4 shows this. if the device you are using does not use all 4 data memory banks, some of the code may be removed.
1997 microchip technology inc. ds31006a-page 6-17 section 6. memory organization memory organization 6 6.6 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to memory are: title application note # implementing a table read an556
picmicro mid-range mcu family ds31006a-page 6-18 1997 microchip technology inc. 6.7 revision history revision a this is the initial released revision of the memory organization description.
1997 microchip technology inc. ds31007a page 7-1 m data eeprom 7 section 7. data eeprom highlights this section of the manual contains the following major topics: 7.1 introduction ................................................................................................................ ....7-2 7.2 control register ............................................................................................................ .7-3 7.3 eeadr....................................................................................................................... ....7-4 7.4 eecon1 and eecon2 registers .................................................................................7-4 7.5 reading the eeprom data memory ............................................................................7-5 7.6 writing to the eeprom data memory...........................................................................7-5 7.7 write verify................................................................................................................ .....7-6 7.8 protection against spurious writes ...............................................................................7-7 7.9 data eeprom operation during code protected con?uration ..................................7-7 7.10 initialization ............................................................................................................. .......7-7 7.11 design tips ................................................................................................................ ....7-8 7.12 related application notes..............................................................................................7-9 7.13 revision history ........................................................................................................... 7-10
picmicro mid-range mcu family ds31007a-page 7-2 1997 microchip technology inc. 7.1 introduction the eeprom data memory is readable and writable during normal operation (full v dd range). this memory is not directly mapped in the register ?e space. instead it is indirectly addressed through the special function registers. there are four sfrs used to read and write this memory. these registers are: eecon1 eecon2 (not a physically implemented register) eedata eeadr eedata holds the 8-bit data for read/write, and eeadr holds the address of the eeprom loca- tion being accessed. the 8-bit eeadr register can access up to 256 locations of data eeprom. the eeadr register can be thought of as the indirect addressing register of the data eeprom. eecon1 contains the control bits, while eecon2 is the register used to initiate the read/write. some devices will implement less then the entire memory map. the address range always starts at 0h, and goes throughout the memory available. table 7-1 shows some of the possible common device memory sizes and the address range for those sizes. table 7-1: possible data eeprom memory sizes the eeprom data memory allows byte read and write. a byte write automatically erases the location and writes the new data (erase before write). the eeprom data memory is rated for high erase/write cycles. the write time is controlled by an on-chip timer. the write-time will vary with voltage and temperature as well as from chip to chip. please refer to the ac speci?ations for exact limits. when the device is code protected, the cpu may continue to read and write the data eeprom memory. the device programmer can no longer access this memory. data eeprom size (1) address range 64 0h - 3fh 128 0h - 7fh 256 0h - ffh note 1: presently, devices are only offered with 64 bytes of data eeprom.
1997 microchip technology inc. ds31007a-page 7-3 section 7. data eeprom data eeprom 7 7.2 control register register 7-1: eecon1 register u-0 u-0 u-0 r/w-1 r/w-1 r/w-x r/s-0 r/s-x eeif (1) wrerr wren wr rd bit 7 bit 0 bit 7:5 unimplemented: read as '0' bit 4 eeif : eeprom write operation interrupt flag bit 1 = the write operation completed (must be cleared in software) 0 = the write operation is not complete or has not been started bit 3 wrerr : eeprom error flag bit 1 = a write operation is prematurely terminated (any mclr reset or any wdt reset during normal operation) 0 = the write operation completed bit 2 wren : eeprom write enable bit 1 = allows write cycles 0 = inhibits write to the data eeprom bit 1 wr : write control bit 1 = initiates a write cycle. the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software. 0 = write cycle to the data eeprom is complete bit 0 rd : read control bit 1 = initiates an eeprom read. read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = does not initiate an eeprom read legend r = readable bit w = writable bit s = settable bit u = unimplemented bit, read as ? - n = value at por reset note 1: future devices will have this bit in the pir register.
picmicro mid-range mcu family ds31007a-page 7-4 1997 microchip technology inc. 7.3 eeadr the eeadr register can address up to a maximum of 256 bytes of data eeprom. the unused address bits are decoded. this means that these bits must always be '0' to ensure that the address is in the data eeprom memory space. 7.4 eecon1 and eecon2 registers eecon1 is the control register with ?e low order bits physically implemented. the upper-three bits are unimplemented and read as '0's. control bits rd and wr initiate read and write, respectively. these bits cannot be cleared, only set, in software. they are cleared in hardware at completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental, premature termination of a write operation. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset or a wdt time-out reset during normal operation. in these situations, following reset, the user can check the wrerr bit and rewrite the location. the data and address will be unchanged in the eedata and eeadr registers. interrupt ?g bit eeif is set when write is complete. it must be cleared in software. eecon2 is not a physical register. reading eecon2 will read all '0's. the eecon2 register is used exclusively in the data eeprom write sequence.
1997 microchip technology inc. ds31007a-page 7-5 section 7. data eeprom data eeprom 7 7.5 reading the eeprom data memory to read a data memory location, the user must write the address to the eeadr register and then set control bit rd (eecon1<0>). the data is available, in the very next instruction cycle, in the eedata register; therefore it can be read by the next instruction. eedata will hold this value until another read or until it is written to by the user (during a write operation). example 7-1: data eeprom read 7.6 writing to the eeprom data memory to write an eeprom data location, the user must ?st write the address to the eeadr register and the data to the eedata register. then the user must follow a speci? sequence to initiate the write for each byte. example 7-2: data eeprom write the write will not initiate if the above sequence is not exactly followed (write 55h to eecon2, write aah to eecon2, then set wr bit) for each byte. we strongly recommend that interrupts be disabled during this code segment. additionally, the wren bit in eecon1 must be set to enable write. this mechanism prevents accidental writes to data eeprom due to errant (unexpected) code execution (i.e., lost pro- grams). the user should keep the wren bit clear at all times, except when updating eeprom. the wren bit is not cleared by hardware after a write sequence has been initiated, clearing the wren bit will not affect this write cycle. the wr bit will be inhibited from being set unless the wren bit is set. at the completion of the write cycle, the wr bit is cleared in hardware and the ee write complete interrupt flag bit (eeif) is set. the user can either enable this interrupt or poll this bit. eeif must be cleared by software. bcf status, rp0 ; bank0 movlw config_addr ; any location in data eeprom memory space movwf eeadr ; address to read bsf status, rp0 ; bank1 bsf eecon1, rd ; ee read bcf status, rp0 ; bank0 movf eedata, w ; w = eedata bsf status, rp0 ; bank1 bcf intcon, gie ; disable ints. bsf eecon1, wren ; enable write required sequence movlw 55h ; movwf eecon2 ; 55h must be written to eecon2 movlw aah ; to start write sequence movwf eecon2 ; write aah bsf eecon1,wr ; set wr bit begin write bsf intcon, gie ; enable ints.
picmicro mid-range mcu family ds31007a-page 7-6 1997 microchip technology inc. 7.7 write verify depending on the application, good programming practice may dictate that the value written to the data eeprom be veri?d ( example 7-3 ) as the value that was intended to be written. this should be used in applications where an eeprom bit will be stressed near the speci?ation limit. the total endurance disk will help determine your comfort level. example 7-3: write verify bcf status, rp0 ; bank0 : ; any code can go here : ; movf eedata, w ; must be in bank0 bsf status, rp0 ; bank1 read bsf eecon1, rd ; yes, read the value written bcf status, rp0 ; bank0 ; ; is the value written (in w reg) and read (in eedata) the same? ; subwf eedata, w ; btfss status, z ; is difference 0? goto write_err ; no, write error : ; yes, good write : ; continue program
1997 microchip technology inc. ds31007a-page 7-7 section 7. data eeprom data eeprom 7 7.8 protection against spurious writes there are conditions when the device may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built-in. on power-up, wren is cleared. also, the power-up timer (72 ms duration) prevents eeprom write. the write initiate sequence and the wren bit together help prevent an accidental write during brown-outs, power glitches, and software malfunction. 7.9 data eeprom operation during code protected con?uration when the device is code protected, the cpu is able to read and write data to the data eeprom. for rom devices, there are two code protection bits. one for the rom program memory and one for the data eeprom memory. see the device programming speci?ation for more information about these bits. 7.10 initialization the data eeprom module does not have an initialization sequence such as other modules. to do a read of the data eeprom refer to example 7-1 . to do a write to the data eeprom refer to example 7-2 , and to verify that the write completed successfully refer to example 7-3 . as for the general purpose ram, it is a good idea to initialize all data eeprom locations to a known state. this initialization may take place at the time of device programming or an applica- tion diagnostic mode, since on reset you may not want the data eeprom to be cleared. an application diagnostic mode may be a condition on the i/o pins that the device tests for after the device power-ups. then depending on this mode, the device would do some diagnostic func- tion. the state for the i/o pins would need to be something that would not be possible without the injected levels to force this diagnostic mode.
picmicro mid-range mcu family ds31007a-page 7-8 1997 microchip technology inc. 7.11 design tips question 1: why do the data eeprom locations not contain the data that i wrote? answer 1: there are a few possibilities, but the most likely is that you did not exactly follow the write sequence as shown in example 7-2 . if you are using this code segment ensure that all interrupts are disabled during this sequence. question 2: why is the data in the data eeprom is getting corrupted? answer 2: the data will only change when a data eeprom write occurs. inadvertent writes may occur when the device is in a brown-out condition (out of operating speci?ation) and the device is not being forced to the reset state. during a brown-out, either the internal brown-out circuitry should be enabled (when available) or external circuitry should be used to reset the picmicro mcu to ensure that no data eeprom writes occur when the device is out of the valid operating range.
1997 microchip technology inc. ds31007a-page 7-9 section 7. data eeprom data eeprom 7 7.12 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to data eeprom are: title application note # eeprom endurance tutorial an601 how to get 10 million cycles out of your microchip serial eeprom an602 basic serial eeprom operation an536 everything a system engineer needs to know about serial eeprom endurance an537 using the microchip endurance predictive software an562
picmicro mid-range mcu family ds31007a-page 7-10 1997 microchip technology inc. 7.13 revision history revision a this is the initial released revision of the data eeprom description.
1997 microchip technology inc. ds31008a page 8-1 m interrupts 8 section 8. interrupts highlights this section of the manual contains the following major topics: 8.1 introduction ................................................................................................................ ....8-2 8.2 control registers ........................................................................................................... 8-5 8.3 interrupt latency ..........................................................................................................8 -10 8.4 int and external interrupts..........................................................................................8-10 8.5 context saving during interrupts .................................................................................8-11 8.6 initialization .............................................................................................................. ....8-14 8.7 design tips ................................................................................................................. .8-16 8.8 related application notes............................................................................................8-17 8.9 revision history ...........................................................................................................8 -18
picmicro mid-range mcu family ds31008a-page 8-2 1997 microchip technology inc. 8.1 introduction picmicro mcus can have many sources of interrupt. these sources generally include one inter- rupt source for each peripheral module, though some modules may generate multiple interrupts (such as the usart module). the current interrupts are: int pin interrupt (external interrupt) tmr0 over?w interrupt portb change interrupt (pins rb7:rb4) comparator change interrupt parallel slave port interrupt usart interrupts receive interrupt transmit interrupt a/d conversion complete interrupt lcd interrupt. data eeprom write complete interrupt timer1 over?w interrupt timer2 over?w interrupt ccp interrupt ssp interrupt there is a minimum of one register used in the control and status of the interrupts. this register is: intcon additionally, if the device has peripheral interrupts, then it will have registers to enable the periph- eral interrupts and registers to hold the interrupt ?g bits. depending on the device, the registers are: pie1 pir1 pie2 pir2 we will generically refer to these registers as pir and pie. if future devices provide more inter- rupt sources, they will be supported by additional register pairs, such as pir3 and pie3. the interrupt control register, intcon, records individual ?g bits for core interrupt requests. it also has various individual enable bits and the global interrupt enable bit.
1997 microchip technology inc. ds31008a-page 8-3 section 8. interrupts interrupts 8 the global interrupt enable bit, gie (intcon<7>), enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. individual interrupts can be disabled through their correspond- ing enable bits in the intcon register. the gie bit is cleared on reset. the ?eturn from interrupt instruction, retfie , exits the interrupt routine as well as sets the gie bit, which allows any pending interrupt to execute. the intcon register contains these interrupts: int pin interrupt, the rb port change interrupt, and the tmr0 over?w interrupt. the intcon register also contains the peripheral interrupt enable bit, peie. the peie bit will enable/disable the peripheral interrupts from vectoring when the peie bit is set/cleared. when an interrupt is responded to, the gie bit is cleared to disable any further interrupt, the return address is pushed into the stack and the pc is loaded with 0004h. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ?g bits. generally the interrupt ?g bit(s) must be cleared in software before re-enabling the global inter- rupt to avoid recursive interrupts. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ?g bits. individual interrupt ?g bits are set regardless of the status of their corresponding mask bit or the gie bit. note 1: individual interrupt ?g bits are set regardless of the status of their corresponding mask bit or the gie bit. note 2: when an instruction that clears the gie bit is executed, any interrupts that were pending for execution in the next cycle are ignored. the cpu will execute a nop in the cycle immediately following the instruction which clears the gie bit. the inter- rupts which were ignored are still pending to be serviced when the gie bit is set again.
picmicro mid-range mcu family ds31008a-page 8-4 1997 microchip technology inc. figure 8-1: interrupt logic tmr1ie tmr1if tmr2ie tmr2if intf inte rbif rbie t0if t0ie gie peie wake-up (if in sleep mode) interrupt to cpu intcon register pir/pie registers adcie adcif adie adif ccp1ie ccp1if ccp2ie ccp2if cmie cmif eeie eeif lcdie lcdif pbie pbif pspie pspif rcie rcif sspie sspif ovfie ovfif txie txif gpif gpie (eeie 2 ) note 1: this shows all current interrupt bits (at time of manual printing) for all picmicro mid-range mcus. which bits pertain to a speci? device is dependent upon the device type and peripherals imple- mented. see speci? device data sheet. 2: some of the original mid-range devices had only one peripheral module. these devices do not have the peie bit, and have the mod- ule enable bit in the intcon register. (adie 2 ) clear gie bit
1997 microchip technology inc. ds31008a-page 8-5 section 8. interrupts interrupts 8 8.2 control registers generally devices have a minimum of three registers associated with interrupts. the intcon register which contains global interrupt enable bit, gie, as well as the peripheral interrupt enable bit, peie, and the pie / pir register pair which enable the peripheral interrupts and dis- play the interrupt ?g status. 8.2.1 intcon register the intcon register is a readable and writable register which contains various enable and ?g bits. register 8-1: intcon register note: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>).this feature allows for software polling. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gie peie (3) t0ie inte (2) rbie (1, 2) t0if intf (2) rbif (1, 2) bit 7 bit 0 bit 7 gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts bit 5 t0ie: tmr0 over?w interrupt enable bit 1 = enables the tmr0 over?w interrupt 0 = disables the tmr0 over?w interrupt bit 4 inte: int external interrupt enable bit 1 = enables the int external interrupt 0 = disables the int external interrupt bit 3 rbie (1) : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 t0if: tmr0 over?w interrupt flag bit 1 = tmr0 register has over?wed (must be cleared in software) 0 = tmr0 register did not over?w bit 1 intf: int external interrupt flag bit 1 = the int external interrupt occurred (must be cleared in software) 0 = the int external interrupt did not occur bit 0 rbif (1) : rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset note 1: in some devices, the rbie bit may also be known as gpie and the rbif bit may be know as gpif. note 2: some devices may not have this feature. for those devices this bit is reserved. note 3: in devices with only one peripheral interrupt, this bit may be eeie or adie.
picmicro mid-range mcu family ds31008a-page 8-6 1997 microchip technology inc. 8.2.2 pie register(s) depending on the number of peripheral interrupt sources, there may be multiple peripheral inter- rupt enable registers (pie1, pie2). these registers contain the individual enable bits for the peripheral interrupts. these registers will be generically referred to as pie. if the device has a pie register, the peie bit must be set to enable any of these peripheral interrupts. although, the pie register bits have a general bit location with each register, future devices may not have consistent placement. bit location inconsistencies will not be a problem if you use the supplied microchip include ?es for the symbolic use of these bits. this will allow the assem- bler/compiler to automatically take care of the placement of these bits by specifying the correct register and bit name. note: bit peie (intcon<6>) must be set to enable any of the peripheral interrupts.
1997 microchip technology inc. ds31008a-page 8-7 section 8. interrupts interrupts 8 register 8-2: pie register r/w-0 (note 1) bit 7 bit 0 bit tmr1ie : tmr1 over?w interrupt enable bit 1 = enables the tmr1 over?w interrupt 0 = disables the tmr1 over?w interrupt bit tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt bit sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit rcie : usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit txie : usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit adie : a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit adcie : slope a/d converter comparator trip interrupt enable bit 1 = enables the slope a/d interrupt 0 = disables the slope a/d interrupt bit ovfie : slope a/d tmr over?w interrupt enable bit 1 = enables the slope a/d tmr over?w interrupt 0 = disables the slope a/d tmr over?w interrupt bit pspie: parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit eeie : ee write complete interrupt enable bit 1 = enables the ee write complete interrupt 0 = disables the ee write complete interrupt bit lcdie : lcd interrupt enable bit 1 = enables the lcd interrupt 0 = disables the lcd interrupt bit cmie : comparator interrupt enable bit 1 = enables the comparator interrupt 0 = disables the comparator interrupt legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset note 1: the bit position of the enable bits is device dependent. please refer to the device data sheet for bit placement.
picmicro mid-range mcu family ds31008a-page 8-8 1997 microchip technology inc. 8.2.3 pir register(s) depending on the number of peripheral interrupt sources, there may be multiple peripheral inter- rupt flag registers (pir1, pir2). these registers contain the individual ?g bits for the peripheral interrupts. these registers will be generically referred to as pir. although, the pir bits have a general bit location within each register, future devices may not be able to be consistent with that. it is recommended that you use the supplied microchip include ?es for the symbolic use of these bits. this will allow the assembler/compiler to automatically take care of the placement of these bits within the speci?d register. note 1: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). note 2: user software should ensure the appropriate interrupt ?g bits are cleared (by soft- ware) prior to enabling an interrupt, and after servicing that interrupt. register 8-3: pir register r/w-0 (note 1) bit 7 bit 0 bit tmr1if : tmr1 over?w interrupt flag bit 1 = tmr1 register over?wed (must be cleared in software) 0 = tmr1 register did not over?w bit tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit ccp2if : ccp2 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit sspif : synchronous serial port interrupt flag bit 1 = the transmission/reception is complete 0 = waiting to transmit/receive bit rcif : usart receive interrupt flag bit 1 = the usart receive buffer, rcreg, is full (cleared when rcreg is read) 0 = the usart receive buffer is empty bit txif : usart transmit interrupt flag bit 1 = the usart transmit buffer, txreg, is empty (cleared when txreg is written) 0 = the usart transmit buffer is full bit adif : a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete
1997 microchip technology inc. ds31008a-page 8-9 section 8. interrupts interrupts 8 bit adcif : slope a/d converter comparator trip interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit ovfif : slope a/d tmr over?w interrupt flag bit 1 = slope a/d tmr over?wed (must be cleared in software) 0 = slope a/d tmr did not over?w bit pspif: parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit eeif : ee write complete interrupt flag bit 1 = the data eeprom write operation is complete (must be cleared in software) 0 = the data eeprom write operation is not complete bit lcdif : lcd interrupt flag bit 1 = lcd interrupt has occurred (must be cleared in software) 0 = lcd interrupt has not occurred bit cmif : comparator interrupt flag bit 1 = comparator input has changed (must be cleared in software) 0 = comparator input has not changed register 8-3: pir register (contd) legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset note 1: the bit position of the ?g bits is device dependent. please refer to the device data sheet for bit placement.
picmicro mid-range mcu family ds31008a-page 8-10 1997 microchip technology inc. 8.3 interrupt latency interrupt latency is de?ed as the time from the interrupt event (the interrupt ?g bit gets set) to the time that the instruction at address 0004h starts execution (when that interrupt is enabled). for synchronous interrupts (typically internal), the latency is 3t cy . for asynchronous interrupts (typically external), such as the int or port rb change interrupt, the interrupt latency will be 3 - 3.75t cy (instruction cycles). the exact latency depends upon when the interrupt event occurs ( figure 8-2 ) in relation to the instruction cycle. the latency is the same for both one and two cycle instructions. 8.4 int and external interrupts the external interrupt on the int pin is edge triggered: either rising if the intedg bit (option<6>) is set, or falling, if the intedg bit is clear. when a valid edge appears on the int pin, the intf ?g bit (intcon<1>) is set. this interrupt can be enabled/disabled by setting/clear- ing the inte enable bit (intcon<4>). the intf bit must be cleared in software in the interrupt service routine before re-enabling this interrupt. the int interrupt can wake-up the processor from sleep, if the inte bit was set prior to going into sleep. the status of the gie bit decides whether or not the processor branches to the interrupt vector following wake-up. see the ?atchdog timer and sleep mode section for details on sleep and for timing of wake-up from sleep through int interrupt. figure 8-2: int pin and other external interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf ?g (intcon<1>) gie bit (intcon<7>) instr uction flo w pc instruction fetched instruction executed interrupt latency pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dummy cycle inst (pc) 1 4 5 1 note 1: intf ?g is sampled here (every q1). 2: interrupt latency = 3-4 t cy where t cy = instruction cycle time. latency is the same whether instruction (pc) is a single cycle or a 2-cycle instruction. 3: clkout is available only in rc oscillator mode. 4: for minimum width of int pulse, refer to ac specs. 5: intf is enabled to be set anytime during the q4-q1 cycles. 2 3 note: any interrupts caused by external signals (such as timers, capture, change on port) will have similar timing.
1997 microchip technology inc. ds31008a-page 8-11 section 8. interrupts interrupts 8 8.5 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key registers during an interrupt e.g. w register and status register. this has to be imple- mented in software. the action of saving information is commonly referred to as ?ushing, while the action of restor- ing the information before the return is commonly referred to as ?oping. these (push, pop) are not instruction mnemonics, but are conceptual actions. this action can be implemented by a sequence of instructions. for ease of code transportability, these code segments can be made into macros (see mpasm assembler users guide for details on creating macros). example 8-1 stores and restores the status and w registers for devices with common ram (such as the pic16c77). the user register, w_temp, must be de?ed across all banks and must be de?ed at the same offset from the bank base address (i.e., w_temp is de?ed at 0x70 - 0x7f in bank0). the user register, status_temp, must be de?ed in bank0, in this example status_temp is also in bank0. the steps of example 8-1 : 1. stores the w register regardless of current bank. 2. stores the status register in bank0. 3. executes the interrupt service routine (isr) code. 4. restores the status (and bank select bit register). 5. restores the w register. if additional locations need to be saved before executing the interrupt service routine (isr) code, they should be saved after the status register is saved (step 2), and restored before the status register is restored (step 4). example 8-1: saving the status and w registers in ram (for devices with common ram) movwf w_temp ; copy w to a temporary register ; regardless of current bank swapf status,w ; swap status nibbles and place ; into w register movwf status_temp ; save status to a temporary register ; in bank0 : : (interrupt service routine (isr) ) : swapf status_temp,w ; swap original status register value ; into w (restores original bank) movwf status ; restore status register from ; w register swapf w_temp,f ; swap w_temp nibbles and return ; value to w_temp swapf w_temp,w ; swap w_temp to w to restore original ; w value without affecting status
picmicro mid-range mcu family ds31008a-page 8-12 1997 microchip technology inc. example 8-2 stores and restores the status and w registers for devices without common ram (such as the pic16c74a). the user register, w_temp, must be de?ed across all banks and must be de?ed at the same offset from the bank base address (i.e., w_temp is de?ed at 0x70 - 0x7f in bank0). the user register, status_temp, must be de?ed in bank0. within the 70h - 7fh range (bank0), wherever w_temp is expected the corresponding locations in the other banks should be dedicated for the possible saving of the w register. the steps of example 8-2 : 1. stores the w register regardless of current bank. 2. stores the status register in bank0. 3. executes the interrupt service routine (isr) code. 4. restores the status (and bank select bit register). 5. restores the w register. if additional locations need to be saved before executing the interrupt service routine (isr) code, they should be saved after the status register is saved (step 2), and restored before the status register is restored (step 4). example 8-2: saving the status and w registers in ram (for devices without common ram) movwf w_temp ; copy w to a temporary register ; regardless of current bank swapf status,w ; swap status nibbles and place ; into w register bcf status,rp0 ; change to bank0 regardless of ; current bank movwf status_temp ; save status to a temporary register ; in bank0 : : (interrupt service routine (isr) ) : swapf status_temp,w ; swap original status register value ; into w (restores original bank) movwf status ; restore status register from ; w register swapf w_temp,f ; swap w_temp nibbles and return ; value to w_temp swapf w_temp,w ; swap w_temp to w to restore original ; w value without affecting status
1997 microchip technology inc. ds31008a-page 8-13 section 8. interrupts interrupts 8 example 8-3 stores and restores the status and w registers for devices with general purpose ram only in bank0 (such as the pic16c620). the bank must be tested before saving any of the user registers. , w_temp, must be de?ed across all banks and must be de?ed at the same offset from the bank base address. the user register, status_temp, must be de?ed in bank0. the steps of example 8-3 : 1. test current bank. 2. stores the w register regardless of current bank. 3. stores the status register in bank0. 4. executes the interrupt service routine (isr) code. 5. restores the status (and bank select bit register). 6. restores the w register. if additional locations need to be saved before executing the interrupt service routine (isr) code, they should be saved after the status register is saved (step 2), and restored before the status register is restored (step 4). example 8-3: saving the status and w registers in ram (for devices with general purpose ram only in bank0) push btfss status, rp0 ; in bank 0? goto rp0clear ; yes, bcf status, rp0 ; no, force to bank 0 movwf w_temp ; store w register swapf status, w ; swap status register and movwf status_temp ; store in status_temp bsf status_temp, 1 ; set the bit that corresponds to rp0 goto isr_code ; push completed rp0clear movwf w_temp ; store w register swapf status, w ; swap status register and movwf status_temp ; store in status_temp ; isr_code : : (interrupt service routine (isr) ) : ; pop swapf status_temp, w ; restore status register movwf status ; btfss status, rp0 ; in bank 1? goto restore_wreg ; no, bcf status, rp0 ; yes, force bank 0 swapf w_temp, f ; restore w register swapf w_temp, w ; bsf status, rp0 ; back to bank 1 retfie ; pop completed restore_wreg swapf w_temp, f ; restore w register swapf w_temp, w ; retfie ; pop completed
picmicro mid-range mcu family ds31008a-page 8-14 1997 microchip technology inc. 8.6 initialization example 8-4 shows the initialization and enabling of device interrupts, where pie1_mask1 value is the value to write into the interrupt enable register. example 8-5 shows how to create macro de?itions for functions. macros must be de?ed before they are used. for debugging ease, it may help if macros are placed in other ?es that are included at assembly time. this allows the source to be viewed without all the clutter of the required macros. these ?es must be included before the macro is used, but it simpli?s debug- ging, if all include ?es are done at the top of the source ?e. example 8-6 shows this structure. example 8-7 shows a typical interrupt service routine structure. this isr uses macros for the saving and restoring of registers before the execution of the interrupt code. example 8-4: initialization and enabling of interrupts example 8-5: register saving / restoring as macros pie1_mask1 equ b?1101010? ; this is the interrupt enable : ; register mask value : clrf status ; bank0 clrf intcon ; disable interrupts and clear some flags clrf pir1 ; clear all flag bits bsf status, rp0 ; bank1 movlw pie1_mask1 ; this is the initial masking for pie1 movwf pie1 ; bcf status, rp0 ; bank0 bsf intcon, gie ; enable interrupts push_macro macro ; this macro saves register contents movwf w_temp ; copy w to a temporary register ; regardless of current bank swapf status,w ; swap status nibbles and place ; into w register movwf status_temp ; save status to a temporary register ; in bank0 endm ; end this macro ; pop_macro macro ; this macro restores register contents swapf status_temp,w ; swap original status register value ; into w (restores original bank) movwf status ; restore status register from ; w register swapf w_temp,f ; swap w_temp nibbles and return ; value to w_temp swapf w_temp,w ; swap w_temp to w to restore original ; w value without affecting status endm ; end this macro
1997 microchip technology inc. ds31008a-page 8-15 section 8. interrupts interrupts 8 example 8-6: source file template example 8-7: typical interrupt service routine (isr) list p = p16c77 ; list directive, ; revision history ; #include ; microchip device header file ; #include ; include my standard macros #include ; file which includes macros specific ; to this application ; specify device configuration bits __config _xt_osc & _pwrte_on & _boden_off & _cp_off & _wdt_on ; org 0x00 ; start of program memory reset_addr : ; first instruction to execute after a reset end org isr_addr ; push_macro ; macro that saves required context registers, ; or in-line code clrf status ; bank0 btfsc pir1, tmr1if ; timer1 overflow interrupt? goto t1_int ; yes btfsc pir1, adif ; no, a/d interrupt? goto ad_int ; yes, do a/d thing : ; no, do this for all sources : ; btfsc pir1, lcdif ; no, lcd interrupt goto lcd_int ; yes, do lcd thing btfsc intcon, rbif ; no, change on portb interrupt? goto portb_int ; yes, do portb change thing int_error_lp1 ; no, do error recovery goto int_error_lp1 ; this is the trap if you enter the isr ; but there were no expected ; interrupts t1_int ; routine when the timer1 overflows : ; bcf pir1, tmr1if ; clear the timer1 overflow interrupt flag goto end_isr ; ready to leave isr (for this request) ad_int ; routine when the a/d completes : ; bcf pir1, adif ; clear the a/d interrupt flag goto end_isr ; ready to leave isr (for this request) lcd_int ; routine when the lcd frame begins : ; bcf pir1, lcdif ; clear the lcd interrupt flag goto end_isr ; ready to leave isr (for this request) portb_int ; routine when portb has a change : ; end_isr ; pop_macro ; macro that restores required registers, ; or in-line code retfie ; return and enable interrupts
picmicro mid-range mcu family ds31008a-page 8-16 1997 microchip technology inc. 8.7 design tips question 1: an algorithm does not give the correct results. answer 1: assuming that the algorithm is correct and that interrupts are enabled during the algorithm, ensure that are registers that are used by the algorithm and by the interrupt service routine are saved and restored. if not some registers may be corrupted by the execution of the isr. question 2: my system seems to lock up. answer 2: if interrupts are being used, ensure that the interrupt ?g is cleared after servicing that interrupt (but before executing the retfie instruction). if the interrupt ?g remains set when the retfie instruction is executed, program execution immediately returns to the interrupt vector, since there is an outstanding enabled interrupt.
1997 microchip technology inc. ds31008a-page 8-17 section 8. interrupts interrupts 8 8.8 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to this section are: title application note # using the portb interrupt on change as an external interrupt an566
picmicro mid-range mcu family ds31008a-page 8-18 1997 microchip technology inc. 8.9 revision history revision a this is the initial released revision of the interrupt description.
1997 microchip technology inc. ds31009a page 9-1 m i/o ports 9 section 9. i/o ports highlights this section of the manual contains the following major topics: 9.1 introduction ................................................................................................................ ....9-2 9.2 porta and the trisa register ....................................................................................9-4 9.3 portb and the trisb register ....................................................................................9-6 9.4 portc and the trisc register....................................................................................9-8 9.5 portd and the trisd register....................................................................................9-9 9.6 porte and the trise register ..................................................................................9-10 9.7 portf and the trisf register ..................................................................................9-11 9.8 portg and the trisg register .................................................................................9-12 9.9 gpio and the trisgp register ..................................................................................9-13 9.10 i/o programming considerations.................................................................................9-14 9.11 initialization ............................................................................................................. .....9-16 9.12 design tips ................................................................................................................ ..9-17 9.13 related application notes............................................................................................9-19 9.14 revision history ........................................................................................................... 9-20
picmicro mid-range mcu family ds31009a-page 9-2 1997 microchip technology inc. 9.1 introduction general purpose i/o pins can be considered the simplest of peripherals. they allow the picmicro to monitor and control other devices. to add ?xibility and functionality to a device, some pins are multiplexed with an alternate function(s). these functions depend on which peripheral features are on the device. in general, when a peripheral is functioning, that pin may not be used as a general purpose i/o pin. for most ports, the i/o pins direction (input or output) is controlled by the data direction register, called the tris register. tris controls the direction of port. a ? in the tris bit corre- sponds to that pin being an input, while a ? corresponds to that pin being an output. an easy way to remember is that a ? looks like an i (input) and a ? looks like an o (output). the port register is the latch for the data to be output. when the port is read, the device reads the levels present on the i/o pins (not the latch). this means that care should be taken with read-modify-write commands on the ports and changing the direction of a pin from an input to an output. figure 9-1 shows a typical i/o port. this does not take into account peripheral functions that may be multiplexed onto the i/o pin. reading the port register reads the status of the pins whereas writing to it will write to the port latch. all write operations (such as bsf and bcf instructions) are read-modify-write operations. therefore a write to a port implies that the port pins are read, this value is modi?d, and then written to the port data latch. figure 9-1: typical i/o port data bus wr port wr tris rd port data latch tris latch p v ss i/o pin note: i/o pin has protection diodes to v dd and v ss . q d q ck q d q ck qd en n v dd rd tris schmitt trigger ttl or
1997 microchip technology inc. ds31009a-page 9-3 section 9. i/o ports i/o ports 9 when peripheral functions are multiplexed onto general i/o pins, the functionality of the i/o pins may change to accommodate the requirements of the peripheral module. examples of this are the analog-to-digital (a/d) converter and lcd driver modules, which force the i/o pin to the peripheral function when the device is reset. in the case of the a/d, this prevents the device from consuming excess current if any analog levels were on the a/d pins after a reset occurred. with some peripherals, the tris bit is overridden while the peripheral is enabled. therefore, read-modify-write instructions ( bsf, bcf, xorwf ) with tris as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings. port pins may be multiplexed with analog inputs and analog v ref input. the operation of each of these pins is selected, to be an analog input or digital i/o, by clearing/setting the control bits in the adcon1 register (a/d control register1). when selected as an analog input, these pins will read as ?s. the tris registers control the direction of the port pins, even when they are being used as ana- log inputs. the user must ensure the tris bits are maintained set when using the pins as analog inputs. note 1: if pins are multiplexed with analog inputs, then on a power-on reset these pins are con?ured as analog inputs, as controlled by the adcon1 register. reading port pins con?ured as analog inputs read a ?? note 2: if pins are multiplexed with comparator inputs, then on a power-on reset these pins are con?ured as analog inputs, as controlled by the cmcon register. reading port pins con?ured as analog inputs read a ?? note 3: if pins are multiplexed with lcd driver segments, then on a power-on reset these pins are con?ured as lcd driver segments, as controlled by the lcdse register. to con?ure the pins as a digital port, the corresponding bits in the lcdse register must be cleared. any bit set in the lcdse register overrides any bit settings in the corresponding tris register. note 4: pins may be multiplexed with the parallel slave port (psp). for the psp to function, the i/o pins must be con?ured as digital inputs and the pspmode bit must be set. note 5: at present the parallel slave port (psp) is only multiplexed onto portd and porte. the microprocessor port becomes enabled when the pspmode bit is set. in this mode, the user must make sure that the trise bits are set (pins are con?- ured as digital inputs) and that porte is con?ured for digital i/o. portd will over- ride the values in the trisd register. in this mode the portd and porte input buffers are ttl. the control bits for the psp operation are located in trise.
picmicro mid-range mcu family ds31009a-page 9-4 1997 microchip technology inc. 9.2 porta and the trisa register the ra4 pin is a schmitt trigger input and an open drain output. all other ra port pins have ttl input levels and full cmos output drivers. all pins have data direction bits (tris registers) which can con?ure these pins as output or input. setting a trisa register bit puts the corresponding output driver in a hi-impedance mode. clear- ing a bit in the trisa register puts the contents of the output latch on the selected pin(s). example 9-1: initializing porta figure 9-2: block diagram of ra3:ra0 and ra5 pins clrf status ; bank0 clrf porta ; initialize porta by clearing output ; data latches bsf status, rp0 ; select bank1 movlw 0xcf ; value used to initialize data direction movwf trisa ; porta<3:0> = inputs porta<5:4> = outputs ; trisa<7:6> always read as '0' data bus wr port wr tris rd port data latch tris latch p v ss i/o pin to peripheral module(s) note: i/o pin has protection diodes to v dd and v ss . q d q ck q d q ck qd en n analog input mode ttl v dd rd tris or st input buffer
1997 microchip technology inc. ds31009a-page 9-5 section 9. i/o ports i/o ports 9 figure 9-3: block diagram of ra4 pin data bus wr port wr tris rd port data latch tris latch schmitt trigger input buffer n v ss to peripheral module note: i/o pin has protection diodes to v ss only. q d q ck q d q ck qd en rd tris ra4 pin
picmicro mid-range mcu family ds31009a-page 9-6 1997 microchip technology inc. 9.3 portb and the trisb register portb is an 8-bit wide bi-directional port. the corresponding data direction register is trisb. setting a bit in the trisb register puts the corresponding output driver in a high-impedance input mode. clearing a bit in the trisb register puts the contents of the output latch on the selected pin(s). example 9-2: initializing portb each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is performed by clearing bit rbpu (option<7>). the weak pull-up is automati- cally turned off when the port pin is con?ured as an output. the pull-ups are disabled on a power-on reset. figure 9-4: block diagram of rb3:rb0 pins clrf status ; bank0 clrf portb ; initialize portb by clearing output ; data latches bsf status, rp0 ; select bank1 movlw 0xcf ; value used to initialize data direction movwf trisb ; portb<3:0> = inputs, portb<5:4> = outputs ; portb<7:6> = inputs data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port to peripheral module i/o pin (1) ttl input buffer schmitt trigger buffer tris latch note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option<7>).
1997 microchip technology inc. ds31009a-page 9-7 section 9. i/o ports i/o ports 9 four of portbs pins, rb7:rb4, have an interrupt on change feature. only pins con?ured as inputs can cause this interrupt to occur (i.e. any rb7:rb4 pin con?ured as an output is excluded from the interrupt on change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?ismatch outputs of rb7:rb4 are or?d together to generate the rb port change interrupt with ?g bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear ?g bit rbif. a mismatch condition will continue to set ?g bit rbif. reading portb will end the mismatch condition, and allow ?g bit rbif to be cleared. this interrupt on mismatch feature, together with software con?urable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-depression. the interrupt on change feature is recommended for wake-up on key depression and operations where portb is only used for the interrupt on change feature. polling of portb is not recom- mended while using the interrupt on change feature. figure 9-5: block diagram of rb7:rb4 pins data latch from other rbpu (2) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer pin (1) st buffer rb7:rb6 in serial programming mode q3 q1 note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option<7>). 3: in sleep mode the device is in q1 state.
picmicro mid-range mcu family ds31009a-page 9-8 1997 microchip technology inc. 9.4 portc and the trisc register portc is an 8-bit bi-directional port. each pin is individually con?urable as an input or output through the trisc register. portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in de?ing tris bits for each portc pin. some peripherals override the tris bit to make a pin an output, while other peripherals over- ride the tris bit to make a pin an input. example 9-3: initializing portc figure 9-6: portc block diagram (peripheral output override) clrf status ; bank0 clrf portc ; initialize portc by clearing output ; data latches bsf status, rp0 ; select bank1 movlw 0xcf ; value used to initialize data direction movwf trisc ; portc<3:0> = inputs, portc<5:4> = outputs ; portc<7:6> = inputs data latch tris latch rd tris p v ss q d q ck q d q ck qd en n v dd 0 1 rd port wr port wr tris schmitt trigger peripheral input peripheral oe (2) data bus port/peripheral select (1) p er ipher al data-out rd port note 1: port/peripheral select signal selects between port data and peripheral output. 2: peripheral oe (output enable) is only activated if peripheral select is active. 3: i/o pins have diode protection to v dd and v ss . i/o pin
1997 microchip technology inc. ds31009a-page 9-9 section 9. i/o ports i/o ports 9 9.5 portd and the trisd register portd is an 8-bit port with schmitt trigger input buffers. each pin is individually con?urable as an input or output. example 9-4: initializing portd figure 9-7: typical portd block diagram (in i/o port mode) clrf status ; bank0 clrf portd ; initialize portd by clearing output ; data latches bsf status, rp0 ; select bank1 movlw 0xcf ; value used to initialize data direction movwf trisd ; portd<3:0> = inputs, portd<5:4> = outputs ; portd<7:6> = inputs data bus wr port wr tris rd port data latch tris latch schmitt trigger input buffer note: i/o pins have protection diodes to v dd and v ss . q d q ck q d q ck qd en i/o pin rd tris
picmicro mid-range mcu family ds31009a-page 9-10 1997 microchip technology inc. 9.6 porte and the trise register porte can be up to an 8-bit port with schmitt trigger input buffers. each pin is individually con- ?urable as an input or output. example 9-5: initializing porte figure 9-8: typical porte block diagram (in i/o port mode) clrf status ; bank0 clrf porte ; initialize porte by clearing output ; data latches bsf status, rp0 ; select bank1 movlw 0x03 ; value used to initialize data direction movwf trise ; porte<1:0> = inputs, porte<7:2> = outputs data bus wr port wr tris rd port data latch tris latch schmitt trigger input buffer q d q ck q d q ck qd en i/o pin rd tris note: i/o pins have protection diodes to v dd and v ss . note: on some devices with porte, the upper bits of the trise register are used for the parallel slave port control and status bits.
1997 microchip technology inc. ds31009a-page 9-11 section 9. i/o ports i/o ports 9 9.7 portf and the trisf register portf is a digital input only port. each pin is multiplexed with an lcd segment driver. these pins have schmitt trigger input buffers. example 9-6: initializing portf figure 9-9: portf lcd block diagram bcf status, rp0 ; select bank2 bsf status, rp1 ; bcf lcdse, se16 ; make all portf bcf lcdse, se12 ; digital inputs rd port schmitt trigger input buffer qd en digital input/ lcdse lcd segment data lcd segment lcd output pin data bus rd tris v dd output enable note: i/o pins have protection diodes to v dd and v ss .
picmicro mid-range mcu family ds31009a-page 9-12 1997 microchip technology inc. 9.8 portg and the trisg register portg is a digital input only port. each pin is multiplexed with an lcd segment driver. these pins have schmitt trigger input buffers. example 9-7: initializing portg figure 9-10: portg lcd block diagram bcf status, rp0 ; select bank2 bsf status, rp1 ; bcf lcdse, se27 ; make all portg bcf lcdse, se20 ; and porte<7> digital inputs rd port schmitt trigger input buffer qd en digital input/ lcdse lcd segment data lcd segment output enable lcd output pin data bus rd tris v dd
1997 microchip technology inc. ds31009a-page 9-13 section 9. i/o ports i/o ports 9 9.9 gpio and the trisgp register gpio is an 8-bit i/o register. only the low order six bits are implemented (gp5:gp0). bits 7 and 6 are unimplemented and read as ?s. any gpio pin (except gp3) can be programmed individually as input or output. the gp3 pin is an input only pin. the trisgp register controls the data direction for gpio pins. a ? in a trisgp register bit puts the corresponding output driver in a hi-impedance mode. a ? puts the contents of the output data latch on the selected pins, enabling the output buffer. the exceptions are gp3 which is input only and its tris bit will always read as '1'. upon reset, the trisgp register is all ?s, making all pins inputs. a read of the gpio port, reads the pins not the output data latches. any input must be present until read by an input instruction (e.g., movf gpio,w ). the outputs are latched and remain unchanged until the output latch is rewritten. example 9-8: initializing gpio figure 9-11: block diagram of gp5:gp0 pins the con?uration word can set several i/os to alternate functions. when acting as alternate functions the pins will read as ? during port read. the gp0, gp1, and gp3 pins can be con?- ured with weak pull-ups and also with interrupt on change. the interrupt on change and weak pull-up functions are not pin selectable. interrupt on change is enabled by setting intcon<3>. if the device con?uration bits select one of the external oscillator modes, the gp4 and gp5 pins gpio functions are overridden and these pins are used for the oscillator. clrf status ; bank0 clrf gpio ; initialize gpio by clearing output ; data latches bsf status, rp0 ; select bank1 movlw 0xcf ; value used to initialize data direction movwf trisgp ; gp<3:0> = inputs gp<5:4> = outputs ; trisgp<7:6> always read as '0' note 1: i/o pins have protection diodes to v dd and v ss . data bus q d q ck q d q ck p n wr port tris ? data tris rd port v ss v dd i/o pin (1) w reg latch latch reset gp3 is input only with no data latch and no output drivers.
picmicro mid-range mcu family ds31009a-page 9-14 1997 microchip technology inc. 9.10 i/o programming considerations when using the ports (and gpio) as i/o, design considerations need to be taken into account to ensure that the operation is as intended. 9.10.1 bi-directional i/o ports any instruction which performs a write operation actually does a read followed by a write opera- tion. the bcf and bsf instructions, for example, read the register into the cpu, execute the bit operation, and write the result back to the register. caution must be used when these instructions are applied to a port with both inputs and outputs de?ed. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu. then the bsf operation takes place on bit5 and portb is written to the output latches. if another bit of portb is used as a bi-directional i/o pin (e.g., bit0) and it is de?ed as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this partic- ular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched to an output, the content of the data latch may now be unknown. reading the port register, reads the values of the port pins. writing to the port register writes the value to the port latch. when using read-modify-write instructions (ex. bcf, bsf , etc.) on a port, the value of the port pins is read, the desired operation is performed on this value, and the value is then written to the port latch. example 9-9 shows the effect of two sequential read-modify-write instructions on an i/o port. example 9-9: read-modify-write instructions on an i/o port a pin con?ured as an output, actively driving a low or high should not be driven from external devices at the same time in order to change the level on this pin (?ired-or, ?ired-and?. the resulting high output currents may damage the chip. ; initial port settings: portb<7:4> inputs ; portb<3:0> outputs ; portb<7:6> have external pull-ups and are not connected to other circuitry ; ; port latch port pins ; ---------- --------- bcf portb, 7 ; 01pp pppp 11pp pppp bcf portb, 6 ; 10pp pppp 11pp pppp bsf status, rp0 ; bcf trisb, 7 ; 10pp pppp 11pp pppp bcf trisb, 6 ; 10pp pppp 10pp pppp ; ; note that the user may have expected the pin values to be 00pp ppp. ; the 2nd bcf caused rb7 to be latched as the pin value (high).
1997 microchip technology inc. ds31009a-page 9-15 section 9. i/o ports i/o ports 9 9.10.2 successive operations on an i/o port the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle ( figure 9-12 ). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that ?e to be read into the cpu is executed. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. figure 9-12: successive i/o operation figure 9-13 shows the i/o model which causes this situation. as the effective capacitance (c) becomes larger, the rise/fall time of the i/o pin increases. as the device frequency increases or the effective capacitance increases, the possibility of this subsequent portx read-modify-write instruction issue increases. this effective capacitance includes the effects of the board traces. the best way to address this is to add an series resistor at the i/o pin. this resistor allows the i/o pin to get to the desired level before the next instruction. the use of nop instructions between the subsequent portx read-modify-write instructions, is a lower cost solution, but has the issue that the number of nop instructions is dependent on the effective capacitance c and the frequency of the device. figure 9-13: i/o connection issues pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb7:rb0 movwf portb write to portb nop port pin sampled here nop movf portb,w instruction executed movwf portb write to portb nop movf portb,w pc t pd this example shows a write to portb followed by a read from portb. note: data setup time = (0.25t cy - t pd ) wheret cy = instruction cycle t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be problematic due to external capacitance. pic16cxxx i/o c (1) q4 q1 q2 q3 q4 q1 v il bsf portx, piny q2 q3 bsf portx, pinz portx, piny read portx, piny as low bsf portx, pinz clears the value to be driven on the portx, piny pin. note: this is not a capacitor to ground, but the effective capac- itive loading on the trace.
picmicro mid-range mcu family ds31009a-page 9-16 1997 microchip technology inc. 9.11 initialization see the section describing each port for examples of initialization of the ports. note: it is recommended that when initializing the port, the data latch (port register) should be initialized ?st, and then the data direction (tris register). this will elim- inate a possible pin glitch, since the port data latch values power up in a random state.
1997 microchip technology inc. ds31009a-page 9-17 section 9. i/o ports i/o ports 9 9.12 design tips question 1: code will not toggle any i/o ports, but the oscillator is running. what can i be doing wrong? answer 1: 1. have the tris registers been initialized properly? these registers can be written to directly in the second bank (bank1). in most cases the user is not switching to bank1 ( bsf status,rp0 ) before writing zeros to the tris register. 2. if you are setting up the tris registers properly in bank1 (rp0 = 1), you may not be returning to bank0 before writing to the ports ( bcf status,rp0 ). 3. is there a peripheral multiplexed onto those pins that are enabled? 4. is the watchdog timer enabled (done at programming)? if it is enabled, is it being cleared properly with a clrwdt instruction at least every 9 ms (or more if prescaled)? 5. are you using the correct instructions to write to the port? more than one person has used the movf command when they should have used movwf . 6. for parts with interrupts, are the interrupts disabled? if not, try disabling them to verify they are not interfering. question 2: when my program reads a port, i get a different value than what i put in the port register. what can cause this? answer 2: 1. when a port is read, it is always the pin that is read, regardless of its being set to input or output. so if a pin is set to an input, you will read the value on the pin regardless of the register value. 2. if a pin is set to output, say it has a one in the data latch; if it is shorted to ground you will still read a zero on the pin. this is very useful for building fault tolerant systems, or han- dling i 2 c bus con?cts. (the i 2 c bus is only driven low, and the pin is tristated for a one. if the pin is low and you are not driving it, some other device is trying to take the bus). 3. mid-range mcu devices all have at least one open drain (or open collector) pin. these pins can only drive a zero or tristate. for most mid-range devices this is pin ra4. open drain pins must have a pull-up resistor to have a high state. this pin is useful for driving odd voltage loads. the pull-up can be connected to a voltage (typically less than v dd ) which becomes the high state. question 3: i have a pic16cxxx with pin rb0 con?ured as an interrupt input, but am not getting interrupted. when i change my routine to poll the pin, it reads the high input and operates ?e. what is the problem? answer 3: portb accepts ttl input levels (on most parts), so when you have an input of say 3v (with v dd = 5v), you will read a one. however the buffer to the interrupt structure from pin rb0 is schmitt trigger, which requires a higher voltage (than ttl input) before the high input is regis- tered. so it is possible to read a one, but not get the interrupt. the interrupt was given a schmitt trigger input with hysteresis to minimize noise problems. it is one thing to have short noise spikes on a pin that is a data input that can potentially cause bad data, but quite another to permit noise to cause an interrupt, hence the difference. i 2 c is a trademark of philips corporation.
picmicro mid-range mcu family ds31009a-page 9-18 1997 microchip technology inc. question 4: when i perform a bcf instruction, other pins get cleared in the port. why? answer 4: 1. another case where a read-modify-write instruction may seem to change other pin values unexpectedly can be illustrated as follows: suppose you make portc all outputs and drive the pins low. on each of the port pins is an led connected to ground, such that a high output lights it. across each led is a 100 m f capacitor. let's also suppose that the processor is running very fast, say 20 mhz. now if you go down the port setting each pin in order; bsf portc,0 then bsf portc,1 then bsf portc,2 and so on, you may see that only the last pin was set, and only the last led actually turns on. this is because the capacitors take a while to charge. as each pin was set, the pin before it was not charged yet and so was read as a zero. this zero is written back out to the port latch (r-m-w, remember) which clears the bit you just tried to set the instruction before. this is usually only a concern at high speeds and for successive port operations, but it can happen, so take it into consideration. 2. if this is on a pic16c7xx device, you have not con?ured the i/o pins properly in the adcon1 register. if a pin is con?ured for analog input, any read of that pin will read a zero, regardless of the voltage on the pin. this is an exception to the normal rule that the pin state is always read. you can still con?ure an analog pin as an output in the tris reg- ister, and drive the pin high or low by writing to it, but you will always read a zero. therefore if you execute a read-modify-write instruction (see previous question) all analog pins are read as zero, and those not directly modi?d by the instruction will be written back to the port latch as zero. a pin con?ured as analog is expected to have values that may be nei- ther high nor low to a digital pin, or ?ating. floating inputs on digital pins are a no-no, and can lead to high current draw in the input buffer, so the input buffer is disabled.
1997 microchip technology inc. ds31009a-page 9-19 section 9. i/o ports i/o ports 9 9.13 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to i/o ports are: title application note # improving the susceptibility of an application to esd an595 clock design using low power/cost techniques an615 implementing wake-up on keystroke an528 interfacing to ac power lines an521 multiplexing led drive and a 4 x 4 keypad sampling an529 using pic16c5x as an lcd drivers an563 serial port routines without using tmr0 an593 implementation of an asynchronous serial i/o an510 using the portb interrupt on change feature as an external interrupt an566 implementing wake-up on keystroke an522 apple desktop bus an591 software implementation of asynchronous serial i/o an555 communicating with the i 2 c bus using the pic16c5x an515 interfacing 93cx6 serial eeproms to the pic16c5x microcontrollers an530 logic powered serial eeproms an535 interfacing 24lcxxb serial eeproms to the pic16c54 an567 using the 24xx65 and 24xx32 with stand-alone pic16c54 code an558
picmicro mid-range mcu family ds31009a-page 9-20 1997 microchip technology inc. 9.14 revision history revision a this is the initial released revision of the i/o ports description.
1997 microchip technology inc. ds31010a page 10-1 m parallel slave port 10 section 10. parallel slave port highlights this section of the manual contains the following major topics: 10.1 introduction ............................................................................................................... ...10-2 10.2 control register ........................................................................................................... 10-3 10.3 operation .................................................................................................................. ...10-4 10.4 operation in sleep mode .............................................................................................10-5 10.5 effect of a reset.......................................................................................................... .10-5 10.6 psp waveforms ...........................................................................................................10- 5 10.7 design tips ................................................................................................................ ..10-6 10.8 related application notes............................................................................................10-7 10.9 revision history ........................................................................................................... 10-8
picmicro mid-range mcu family ds31010a-page 10-2 1997 microchip technology inc. 10.1 introduction some devices have an 8-bit wide parallel slave port (psp). this port is multiplexed onto one of the devices i/o ports. the port operates as an 8-bit wide parallel slave port, or microprocessor port, when the pspmode control bit is set. in this mode, the input buffers are ttl. in slave mode the module is asynchronously readable and writable by the external world through rd control input pin and the wr control input pin. it can directly interface to an 8-bit microprocessor data bus. the external microprocessor can read or write the port latch as an 8-bit latch. setting the pspmode bit enables port pins to be the rd input, the wr input, and the cs (chip select) input. there are actually two 8-bit latches, one for data-out (from the picmicro) and one for data input. the user writes 8-bit data to port data latch and reads data from the port pin latch (note that they have the same address). in this mode, the tris register is ignored, since the microproces- sor is controlling the direction of data ?w. figure 10-1 shows the block diagram for the psp. figure 10-1: portd and porte block diagram (parallel slave port) note 1: at present the parallel slave port (psp) is only multiplexed onto portd and porte. the microprocessor port becomes enabled when the pspmode bit is set. in this mode, the user must make sure that portd and porte are con?ured as digital i/o. that is, peripheral modules multiplexed onto the psp functions are dis- abled (such as the a/d). when porte is con?ured for digital i/o. portd will override the values in the trisd register. note 2: in this mode the portd and porte input buffers are ttl. the control bits for the psp operation are located in trise. en q d ck data bus wr port rd port one bit of portd set interrupt ?g pspif psp7:psp0 ttl ttl read chip select write rd cs wr note: i/o pins have protection diodes to v dd and v ss . en qd en ttl ttl
1997 microchip technology inc. ds31010a-page 10-3 section 10. parallel slave port parallel slave port 10 10.2 control register register 10-1: trise register r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode trise2 trise1 trise0 bit 7 bit 0 bit 7 ibf: input buffer full status bit 1 = a word has been received and waiting to be read by the cpu 0 = no word has been received bit 6 obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov : input buffer over?w detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no over?w occurred bit 4 pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3 unimplemented: read as '0' bit 2 trise2 : re2 direction control bit 1 = input 0 = output bit 1 trise1 : re1 direction control bit 1 = input 0 = output bit 0 trise0 : re0 direction control bit 1 = input 0 = output legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31010a-page 10-4 1997 microchip technology inc. 10.3 operation a write to the psp from the external system, occurs when both the cs and wr lines are ?st detected low. when either the cs or wr lines become high (edge triggered), the input buffer full status ?g bit ibf (trise<7>) is set on the q4 clock cycle, following the next q2 cycle, to signal the write is complete. the interrupt ?g bit, pspif, is also set on the same q4 clock cycle. the ibf ?g bit is inhibited from being cleared for additional t cy cycles (see parameter 66 ). if the ibf ?g bit is cleared by reading the portd input latch, and this has to be a read-only instruction (i.e., movf ) and not a read-modify-write instruction. the input buffer over?w status ?g bit ibov (trise<5>) is set if a second write to the parallel slave port is attempted when the previous byte has not been read out of the buffer. a read from the psp from the external system, occurs when both the cs and rd lines are ?st detected low. the output buffer full status ?g bit obf (trise<6>) is cleared immediately indi- cating that the portd latch was read by the external bus. when either the cs or rd pin becomes high (edge triggered), the interrupt ?g bit pspif is set on the q4 clock cycle, following the next q2 cycle, indicating that the read is complete. obf remains low until data is written to portd by the user ?mware. input buffer full status flag bit ibf, is set if a received word is waiting to be read by the cpu. once the port input latch is read, the ibf bit is cleared. the ibf bit is a read only status bit. output buffer full status flag bit obf, is set if a word written to port latch is waiting to be read by the external bus. once the portd output latch is read by the microprocessor, obf is cleared. input buffer over?w status flag bit ibov is set if a second write to the microprocessor port is attempted when the previous word has not been read by the cpu (the ?st word is retained in the buffer). when not in parallel slave port mode, the ibf and obf bits are held clear. however, if ?g bit ibov was previously set, it must be cleared in the software. an interrupt is generated and latched into ?g bit pspif when a read or a write operation is com- pleted. interrupt ?g bit pspif must be cleared by user software and the interrupt can be dis- abled by clearing interrupt enable bit pspie. table 10-1: porte functions name function rd read control input in parallel slave port mode: rd 1 = not a read operation 0 = read operation. reads portd register (if chip selected) wr write control input in parallel slave port mode: wr 1 = not a write operation 0 = write operation. writes portd register (if chip selected) cs chip select control input in parallel slave port mode: cs 1 = device is not selected 0 = device is selected note: the psp may have other functions multiplexed onto the same pins. for the psp to operate, the pins must be con?ured as digital i/o.
1997 microchip technology inc. ds31010a-page 10-5 section 10. parallel slave port parallel slave port 10 10.4 operation in sleep mode when in sleep mode the microprocessor may still read and write the parallel slave port. these actions will set the pspif bit. if the psp interrupts are enabled, this will wake the processor from sleep mode so that the psp data latch may be either read, or written with the next value for the microprocessor. 10.5 effect of a reset after any reset the psp is disabled and portd and porte are forced to their default mode. 10.6 psp waveforms figure 10-2 shows the waveform for a write from the microprocessor to the psp, while figure 10-3 shows the waveform for a read of the psp by the microprocessor. figure 10-2: parallel slave port write waveforms figure 10-3: parallel slave port read waveforms q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0> note: the ibf ?g bit is inhibited from being cleared until after this point. q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0>
picmicro mid-range mcu family ds31010a-page 10-6 1997 microchip technology inc. 10.7 design tips question 1: migrating from the pic16c74 to the pic16c74a, the operation of the psp seems to have changed. answer 1: yes, a design change was made so the pic16c74a is edge sensitive (while the pic16c74 was level sensitive). see appendix c.9 for more information.
1997 microchip technology inc. ds31010a-page 10-7 section 10. parallel slave port parallel slave port 10 10.8 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the parallel slave port are: title application note # using the 8-bit parallel slave port an579
picmicro mid-range mcu family ds31010a-page 10-8 1997 microchip technology inc. 10.9 revision history revision a this is the initial released revision of the parallel slave port description.
1997 microchip technology inc. ds31011a page 11-1 timer0 11 m section 11. timer0 highlights this section of the manual contains the following major topics: 11.1 introduction ............................................................................................................... ...11-2 11.2 control register ........................................................................................................... 11-3 11.3 operation .................................................................................................................. ...11-4 11.4 tmr0 interrupt............................................................................................................. 11-5 11.5 using timer0 with an external clock ...........................................................................11-6 11.6 tmr0 prescaler ...........................................................................................................11 -7 11.7 design tips ................................................................................................................ 11-10 11.8 related application notes..........................................................................................11-11 11.9 revision history .........................................................................................................11 -12
picmicro mid-range mcu family ds31011a-page 11-2 1997 microchip technology inc. 11.1 introduction the timer0 module has the following features: 8-bit timer/counter readable and writable 8-bit software programmable prescaler clock source selectable to be external or internal interrupt on over?w from ffh to 00h edge select for external clock figure 11-1 shows a simpli?d block diagram of the timer0 module. figure 11-1: timer0 block diagram note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. note 1: t0cs, t0se, psa, ps2:ps0 (option_reg<5:0>). 2: the prescaler is shared with watchdog timer (refer to figure 11-6 for detailed block diagram). t0cki pin t0se 0 1 1 0 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 psout (2 cycle delay) psout data bus 8 psa ps2, ps1, ps0 set interrupt ?g bit t0if on over?w 3
1997 microchip technology inc. ds31011a-page 11-3 section 11. timer0 timer0 11 11.2 control register the option_reg register is a readable and writable register which contains various control bits to con?ure the tmr0/wdt prescaler, the external int interrupt, tmr0, and the weak pull-ups on portb. register 11-1: option_reg register note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu (1) intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu (1) : weak pull-up enable bit 1 = weak pull-ups are disabled 0 = weak pull-ups are enabled by individual port latch values bit 6 intedg : interrupt edge select bit 1 = interrupt on rising edge of int pin 0 = interrupt on falling edge of int pin bit 5 t0cs : tmr0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2:0 ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset note 1: some devices call this bit gppu . devices that have the rbpu bit, have the weak pull-ups on portb, while devices that have the gppu have the weak pull-ups on the gpio port.
picmicro mid-range mcu family ds31011a-page 11-4 1997 microchip technology inc. 11.3 operation timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the timer0 mod- ule will increment every instruction cycle (without prescaler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles ( figure 11-2 and figure 11-3 ). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit (option<5>). in counter mode, timer0 will increment either on every rising or falling edge of the t0cki pin. the incrementing edge is deter- mined by the timer0 source edge select the t0se bit (option<4>). clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed in detail in subsec- tion 11.5 ?sing timer0 with an external clock . the prescaler is mutually exclusively shared between the timer0 module and the watchdog timer. the prescaler assignment is controlled in software by the psa control bit (option<3>). clearing the psa bit will assign the prescaler to the timer0 module. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. subsection 11.6 ?mr0 prescaler details the operation of the prescaler. any write to the tmr0 register will cause a 2 instruction cycle (2t cy ) inhibit. that is, after the tmr0 register has been written with the new value, tmr0 will not be incremented until the third instruction cycle later ( figure 11-2 ). when the prescaler is assigned to the timer0 module, any write to the tmr0 register will immediately update the tmr0 register and clear the prescaler. the incrementing of timer0 (tmr0 and prescaler) will also be inhibited 2 instruction cycles (t cy ). so if the prescaler is con?ured as 2, then after a write to the tmr0 register tmr0 will not increment for 4 timer0 clocks ( figure 11-3 ). after that, tmr0 will increment every prescaler number of clocks later. figure 11-2: timer0 timing: internal clock/no prescale figure 11-3: timer0 timing: internal clock/prescale 1:2 pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 t 0 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute
1997 microchip technology inc. ds31011a-page 11-5 section 11. timer0 timer0 11 11.4 tmr0 interrupt the tmr0 interrupt is generated when the tmr0 register over?ws from ffh to 00h. this over?w sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt service rou- tine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep since the timer is shut-off during sleep. see figure 11-4 for timer0 interrupt timing. figure 11-4: tmr0 interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 1 1 osc1 clkout(3) timer0 t0if bit feh gie bit instruction pc instruction fetched pc pc +1 pc +1 0004h 0005h instruction executed inst (pc) inst (pc-1) inst (pc+1) inst (pc) inst (0004h) inst (0005h) inst (0004h) dummy cycle dummy cycle ffh 00h 01h 02h note 1: interrupt ?g bit t0if is sampled here (every q1). 2: interrupt latency = 4t cy where t cy = instruction cycle time. 3: clkout is available only in rc oscillator mode. flow
picmicro mid-range mcu family ds31011a-page 11-6 1997 microchip technology inc. 11.5 using timer0 with an external clock when an external clock input is used for timer0, it must meet certain requirements as detailed in 11.5.1 ?xternal clock synchronization. these requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. 11.5.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the syn- chronization of t0cki with the internal phase clocks is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks ( figure 11-5 ). therefore, it is nec- essary for t0cki to be high for at least 2tosc (and a small rc delay of 20 ns) and low for at least 2tosc (and a small rc delay of 20 ns). refer to parameters 40 , 41 and 42 in the electrical spec- i?ation of the desired device. when a prescaler is used, the external clock input is divided by an asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. therefore, it is necessary for t0cki to have a period of at least 4tosc (and a small rc delay of 40 ns) divided by the pres- caler value. the only requirement on t0cki high and low time is that they do not violate the min- imum pulse width requirement of 10 ns. refer to parameters 40 , 41 and 42 in the electrical speci?ation of the desired device. 11.5.2 tmr0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 module is actually incremented. figure 11-5 shows the delay from the external clock edge to the timer incrementing. figure 11-5: timer0 timing with external clock q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 external clock input or prescaler output (2) external clock/prescaler output after sampling increment timer0 (q4) timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling note 1: delay from clock input change to timer0 increment is 3tosc to 7tosc. (duration of q = tosc). therefore, the error in measuring the interval between two edges on timer0 input = 4tosc max. 2: external clock if no prescaler selected, prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs. (3) (1)
1997 microchip technology inc. ds31011a-page 11-7 section 11. timer0 timer0 11 11.6 tmr0 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer ( figure 11-6 ). for simplicity, this counter is being referred to as ?rescaler in the timer0 description. thus, a prescaler assignment for the timer0 module means that there is no postscaler for the watchdog timer, and vice-versa. the psa and ps2:ps0 bits (option<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0, movwf tmr0, bsf tmr0,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the prescaler is not readable or writable. figure 11-6: block diagram of the timer0/wdt prescaler note: there is only one prescaler available which is mutually exclusively shared between the timer0 module and the watchdog timer. t0cki pin t0se m u x clkout (=fosc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option_reg<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set t0if ?g bit on over?w 8 psa t0cs
picmicro mid-range mcu family ds31011a-page 11-8 1997 microchip technology inc. 11.6.1 switching prescaler assignment the prescaler assignment is fully under software control, i.e., it can be changed ?n the ? during program execution. in example 11-1 , the ?st modi?ation of the option_reg does not need to be included if the ?al desired prescaler is other then 1:1. if the ?al prescaler value is to be 1:1, then a temporary prescale value is set (other than 1:!), and the ?al prescale value is set in the last modi?ation of option_reg. example 11-1: changing prescaler (timer0 ? wdt) to change prescaler from the wdt to the timer0 module use the sequence shown in example 11-2 . example 11-2: changing prescaler (wdt ? timer0) note: to avoid an unintended device reset, the following instruction sequence (shown in example 11-1 ) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled. 1) bsf status, rp0 ;bank1 lines 2 and 3 do not have to be included if the ?al desired prescale value is other than 1:1. if 1:1 is ?al desired value, then a temporary prescale value is set in lines 2 and 3 and the ?al prescale value will be set in lines 10 and 11. 2) movlw b'xx0x0xxx' ;select clock source and prescale value of 3) movwf option_reg ;other than 1:1 4) bcf status, rp0 ;bank0 5) clrf tmr0 ;clear tmr0 and prescaler 6) bsf status, rp1 ;bank1 7) movlw b'xxxx1xxx' ;select wdt, do not change prescale value 8) movwf option_reg ; 9) clrwdt ;clears wdt and prescaler 10) movlw b'xxxx1xxx' ;select new prescale value and wdt 11) movwf option_reg ; 12) bcf status, rp0 ;bank0 clrwdt ; clear wdt and prescaler bsf status, rp0 ; bank1 movlw b'xxxx0xxx' ; select tmr0, new prescale movwf option_reg ; value and clock source bcf status, rp0 ; bank0
1997 microchip technology inc. ds31011a-page 11-9 section 11. timer0 timer0 11 11.6.2 initialization since timer0 has a software programmable clock source, there are two examples to show the initialization of timer0 with each source. example 11-3 shows the initialization for the internal clock source (timer mode), while example 11-4 shows the initialization for the external clock source (counter mode). example 11-3: timer0 initialization (internal clock source) example 11-4: timer0 initialization (external clock source) clrf tmr0 ; clear timer0 register clrf intcon ; disable interrupts and clear t0if bsf status, rp0 ; bank1 movlw 0xc3 ; portb pull-ups are disabled, movwf option_reg ; interrupt on rising edge of rb0 ; timer0 increment from internal clock ; with a prescaler of 1:16. bcf status, rp0 ; bank0 ;** bsf intcon, t0ie ; enable tmr0 interrupt ;** bsf intcon, gie ; enable all interrupts ; ; the tmr0 interrupt is disabled, do polling on the overflow bit ; t0_ovfl_wait btfss intcon, t0if goto t0_ovfl_wait ; timer has overflowed clrf tmr0 ; clear timer0 register clrf intcon ; disable interrupts and clear t0if bsf status, rp0 ; bank1 movlw 0x37 ; portb pull-ups are enabled, movwf option_reg ; interrupt on falling edge of rb0 ; timer0 increment from external clock ; on the high-to-low transition of t0cki ; with a prescaler of 1:256. bcf status, rp0 ; bank0 ;** bsf intcon, t0ie ; enable tmr0 interrupt ;** bsf intcon, gie ; enable all interrupts ; ; the tmr0 interrupt is disabled, do polling on the overflow bit ; t0_ovfl_wait btfss intcon, t0if goto t0_ovfl_wait ; timer has overflowed
picmicro mid-range mcu family ds31011a-page 11-10 1997 microchip technology inc. 11.7 design tips question 1: i am implementing a counter/clock, but the clock loses time or is inaccurate. answer 1: if you are polling tmr0 to see if it has rolled over to zero. you could do this by executing: wait movf tmr0,w ; read the timer into w btfss status,z ; see if it was zero, if so, ; break from loop goto wait ; if not zero yet, keep waiting two possible scenarios to lose clock cycles are: 1. if you are incrementing tmr0 from the internal instruction clock, or an external source that is about as fast, the over?w could occur during the two cycle goto , so you could miss it. in this case the tmr0 source should be prescaled. or you could do a test to see if it has rolled over by checking for less than a nominal value: wait movlw 3 subwf tmr0,w btfsc status,c goto wait 2. when writing to tmr0, two instruction clock cycles are lost. often you have a speci? time period you want to count, say 100 decimal. in that case you might put 156 into tmr0 (256 - 100 = 156). however, since two instruction cycles are lost when you write to tmr0 (for internal logic synchronization), you should actually write 158 to the timer.
1997 microchip technology inc. ds31011a-page 11-11 section 11. timer0 timer0 11 11.8 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to timer0 are: title application note # frequency counter using pic16c5x an592 a clock design using the pic16c54 for led display and switch inputs an590
picmicro mid-range mcu family ds31011a-page 11-12 1997 microchip technology inc. 11.9 revision history revision a this is the initial released revision of the timer0 module description.
1997 microchip technology inc. ds31012a page 12-1 m timer1 12 section 12. timer1 highlights this section of the manual contains the following major topics: 12.1 introduction ............................................................................................................... ...12-2 12.2 control register ........................................................................................................... 12-3 12.3 timer1 operation in timer mode .................................................................................12-4 12.4 timer1 operation in synchronized counter mode.......................................................12-4 12.5 timer1 operation in asynchronous counter mode......................................................12-5 12.6 timer1 oscillator.......................................................................................................... 12-7 12.7 sleep operation ...........................................................................................................1 2-9 12.8 resetting timer1 using a ccp trigger output ............................................................12-9 12.9 resetting of timer1 register pair (tmr1h:tmr1l)....................................................12-9 12.10 timer1 prescaler.......................................................................................................... 12-9 12.11 initialization ............................................................................................................ ....12-10 12.12 design tips ............................................................................................................... .12-12 12.13 related application notes..........................................................................................12-13 12.14 revision history .........................................................................................................1 2-14
picmicro mid-range mcu family ds31012a-page 12-2 1997 microchip technology inc. 12.1 introduction the timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (tmr1h and tmr1l) which are readable and writable. the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the timer1 interrupt, if enabled, is generated on over?w which is latched in the tmr1if interrupt ?g bit. this interrupt can be enabled/disabled by setting/clearing the tmr1ie interrupt enable bit. timer1 can operate in one of three modes: as a synchronous timer as a synchronous counter as an asynchronous counter the operating mode is determined by clock select bit, tmr1cs (t1con<1>), and the synchro- nization bit, t1sync ( figure 12-1 ). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input on pin t1cki. timer1 can be turned on and off using thetmr1on control bit (t1con<0>). timer1 also has an internal ?eset input? which can be generated by a ccp module. timer1 has the capability to operate off an external crystal. when the timer1 oscillator is enabled (t1oscen is set), the t1osi and t1oso pins become inputs. that is, their corresponding tris values are ignored. figure 12-1: timer1 block diagram tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enable oscillator (1) f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/ t1osi note 1: when the t1oscen bit is cleared, the inverter and feedback resistor are turned off. this eliminates power drain. set tmr1if ?g bit on over?w tmr1 t1cki clr ccp special trigger
1997 microchip technology inc. ds31012a-page 12-3 section 12. timer1 timer1 12 12.2 control register register 12-1 shows the timer1 control register. register 12-1: t1con: timer1 control register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7:6 unimplemented: read as '0' bit 5:4 t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen : timer1 oscillator enable bit 1 = oscillator is enabled 0 = oscillator is shut off. the oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2 t1sync : timer1 external clock input synchronization select bit when tmr1cs = 1: 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0: this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1 tmr1cs : timer1 clock source select bit 1 = external clock from pin t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on : timer1 on bit 1 = enables timer1 0 = stops timer1 legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31012a-page 12-4 1997 microchip technology inc. 12.3 timer1 operation in timer mode timer mode is selected by clearing the tmr1cs (t1con<1>) bit. in this mode, the input clock to the timer is f osc /4. the synchronize control bit, t1sync (t1con<2>), has no effect since the internal clock is always synchronized. 12.4 timer1 operation in synchronized counter mode counter mode is selected by setting the tmr1cs bit. in this mode the timer increments on every rising edge of clock input on the t1osi pin when the oscillator enable bit (t1oscen) is set, or the t1oso/t1cki pin when the t1oscen bit is cleared. if the t1sync bit is cleared, then the external clock input is synchronized with internal phase clocks. the synchronization is done after the prescaler stage. the prescaler is an asynchronous ripple-counter. in this con?uration, during sleep mode, timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off. the prescaler however will continue to increment. 12.4.1 external clock input timing for synchronized counter mode when an external clock input is used for timer1 in synchronized counter mode, it must meet cer- tain requirements. the external clock requirement is due to internal phase clock (tosc) synchro- nization. also, there is a delay in the actual incrementing of tmr1 after synchronization. when the prescaler is 1:1, the external clock input is the same as the prescaler output. the syn- chronization of t1cki with the internal phase clocks is accomplished by sampling the prescaler output on alternating tosc clocks of the internal phase clocks. therefore, it is necessary for the t1cki pin to be high for at least 2tosc (and a small rc delay) and low for at least 2tosc (and a small rc delay). refer to parameters 45 , 46 , and 47 in the ?lectrical speci?ations section. when a prescaler other than 1:1 is used, the external clock input is divided by the asynchronous ripple-counter prescaler so that the prescaler output is symmetrical. in order for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. there- fore, it is necessary for the t1cki pin to have a period of at least 4tosc (and a small rc delay) divided by the prescaler value. another requirement on the t1cki pin high and low time is that they do not violate the minimum pulse width requirements). refer to parameters 40 , 42 , 45 , 46 , and 47 in the ?lectrical speci?ations section.
1997 microchip technology inc. ds31012a-page 12-5 section 12. timer1 timer1 12 12.5 timer1 operation in asynchronous counter mode if t1sync (t1con<2>) is set, the external clock input is not synchronized. the timer continues to increment asynchronously to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt on over?w which will wake-up the processor. however, special precautions in software are needed to read/write the timer (subsection 12.5.2 ?eading and writing timer1 in asynchronous counter mode ). since the counter can operate in sleep, timer1 can be used to implement a true real-time clock. in asynchronous counter mode, timer1 cannot be used as a time-base for capture or compare operations. 12.5.1 external clock input timing with unsynchronized clock if the t1sync control bit is set, the timer will increment completely asynchronously. the input clock must meet certain minimum high time and low time requirements. refer to the device data sheet electrical speci?ations section, timing parameters 45 , 46 , and 47 . 12.5.2 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock, will guarantee a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems since the timer may over?w between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write contention may occur by writing to the timer registers while the register is incrementing. this may produce an unpredictable value in the timer register. reading the 16-bit value requires some care, since two separate reads are required to read the entire 16-bits. example 12-1 shows why this may not be a straight forward read of the 16-bit register. example 12-1: reading 16-bit register issues tmr1 sequence 1 sequence 2 action tmph:tmpl action tmph:tmpl 04ffh read tmr1l xxxxh read tmr1h xxxxh 0500h store in tmpl xxffh store in tmph 04xxh 0501h read tmr1h xxffh read tmr1l 04xxh 0502h store in tmph 05ffh store in tmpl 0401h
picmicro mid-range mcu family ds31012a-page 12-6 1997 microchip technology inc. example 12-2 shows a routine to read the 16-bit timer value with experiencing the issues shown in example 12-1 . this is useful if the timer cannot be stopped. example 12-2: reading a 16-bit free-running timer writing a 16-bit value to the 16-bit tmr1 register is straight forward. first the tmr1l register is cleared to ensure that there are many timer1 clock/oscillator cycles before there is a rollover into the tmr1h register. the tmr1h register is then loaded, and ?ally the tmr1l register is loaded. example 12-3 shows this: example 12-3: writing a 16-bit free running timer ; all interrupts are disabled movf tmr1h, w ; read high byte movwf tmph ; movf tmr1l, w ; read low byte movwf tmpl ; movf tmr1h, w ; read high byte subwf tmph, w ; sub 1st read with 2nd read btfsc status,z ; is result = 0 goto continue ; good 16-bit read ; ; tmr1l may have rolled over between the read of the high and low bytes. ; reading the high and low bytes now will read a good value. ; movf tmr1h, w ; read high byte movwf tmph ; movf tmr1l, w ; read low byte movwf tmpl ; ; re-enable the interrupt (if required) continue ; continue with your code ; all interrupts are disabled clrf tmr1l ; clear low byte, ensures no ; rollover into tmr1h movlw hi_byte ; value to load into tmr1h movwf tmr1h, f ; write high byte movlw lo_byte ; value to load into tmr1l movwf tmr1h, f ; write low byte ; re-enable the interrupt (if required) continue ; continue with your code
1997 microchip technology inc. ds31012a-page 12-7 section 12. timer1 timer1 12 12.6 timer1 oscillator a crystal oscillator circuit is built in between pins t1osi (input) and t1oso (ampli?r output). it is enabled by setting the t1oscen control bit (t1con<3>). the oscillator is a low power oscillator, rated up to 200 khz operation. it will continue to run during sleep. it is primarily intended for a 32 khz crystal, which is an ideal frequency for real-time keeping. table 12-1 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must provide a software time delay to ensure proper oscillator start-up. table 12-1: capacitor selection for the timer1 oscillator note: this allows the counter to operate (increment) when the device is in sleep mode, which allows timer1 to be used as a real-time clock. osc type freq c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf crystals tested: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
picmicro mid-range mcu family ds31012a-page 12-8 1997 microchip technology inc. 12.6.1 typical application this feature is typically used in applications where real-time needs to be kept, but it is also desir- able to have the lowest possible power consumption. the timer1 oscillator allows the device to be placed in sleep, while the timer continues to increment. when timer1 over?ws the interrupt could wake-up the device so that the appropriate registers could be updated. figure 12-2: timer1 application 8 4 4 4 4 x 4 keypad current sink tmr1 v ss pic16cxxx v dd 32 khz backup battery power-down detect t1osi t1oso osc1
1997 microchip technology inc. ds31012a-page 12-9 section 12. timer1 timer1 12 12.7 sleep operation when timer1 is con?ured for asynchronous operation, the tmr1 registers will continue to increment for each timer clock (or prescale multiple of clocks). when the tmr1 register over- ?ws, the tmr1if bit will get set, and if enabled generate an interrupt that will wake the processor from sleep mode. the timer1 oscillator will add a delta current, due to the operation of this circuitry. that is, the power-down current will no longer only be the leakage current of the device, but also the active current of the timer1 oscillator and other timer1 circuitry. 12.8 resetting timer1 using a ccp trigger output if a ccp module is con?ured in compare mode to generate a ?pecial event trigger (ccp1m3:ccp1m0 = 1011 ), this signal resets timer1. timer1 must be con?ured for either timer or synchronized counter mode to take advantage of the special event trigger feature. if timer1 is running in asynchronous counter mode, this reset operation may not work, and should not be used. in the event that a write to timer1 coincides with a special event trigger from the ccp module, the write will take precedence. in this mode of operation, the ccprxh:ccprxl register pair effectively becomes the period register for timer1. 12.9 resetting of timer1 register pair (tmr1h:tmr1l) tmr1h and tmr1l registers are not reset on a por or any other reset, only by the ccp special event triggers. t1con register is reset to 00h on a power-on reset or a brown-out reset. in any other reset, the register is unaffected. 12.10 timer1 prescaler the prescaler counter is cleared on writes to the tmr1h or tmr1l registers. table 12-2: registers associated with timer1 as a timer/counter note: the special event trigger from the ccp module does not set interrupt ?g bit tmr1if. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets intcon gie peie t0ie inte rbie (2) t0if intf rbif (2) 0000 000x 0000 000u pir tmr1if (1) 00 pie tmr1ie (1) 00 tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer1 module. note 1: the placement of this bit is device dependent. 2: these bits may also be named gpie and gpif.
picmicro mid-range mcu family ds31012a-page 12-10 1997 microchip technology inc. 12.11 initialization since timer1 has a software programmable clock source, there are three examples to show the initialization of each mode. example 12-4 shows the initialization for the internal clock source, example 12-5 shows the initialization for the external clock source, and example 12-6 shows the initialization of the external oscillator mode. example 12-4: timer1 initialization (internal clock source) example 12-5: timer1 initialization (external clock source) clrf t1con ; stop timer1, internal clock source, ; t1 oscillator disabled, prescaler = 1:1 clrf tmr1h ; clear timer1 high byte register clrf tmr1l ; clear timer1 low byte register clrf intcon ; disable interrupts bsf status, rp0 ; bank1 clrf pie1 ; disable peripheral interrupts bcf status, rp0 ; bank0 clrf pir1 ; clear peripheral interrupts flags movlw 0x30 ; internal clock source with 1:8 prescaler movwf t1con ; timer1 is stopped and t1 osc is disabled bsf t1con, tmr1on ; timer1 starts to increment ; ; the timer1 interrupt is disabled, do polling on the overflow bit ; t1_ovfl_wait btfss pir1, tmr1if goto t1_ovfl_wait ; ; timer has overflowed ; bcf pir1, tmr1if clrf t1con ; stop timer1, internal clock source, ; t1 oscillator disabled, prescaler = 1:1 clrf tmr1h ; clear timer1 high byte register clrf tmr1l ; clear timer1 low byte register clrf intcon ; disable interrupts bsf status, rp0 ; bank1 clrf pie1 ; disable peripheral interrupts bcf status, rp0 ; bank0 clrf pir1 ; clear peripheral interrupts flags movlw 0x32 ; external clock source with 1:8 prescaler movwf t1con ; clock source is synchronized to device ; timer1 is stopped and t1 osc is disabled bsf t1con, tmr1on ; timer1 starts to increment ; ; the timer1 interrupt is disabled, do polling on the overflow bit ; t1_ovfl_wait btfss pir1, tmr1if goto t1_ovfl_wait ; ; timer has overflowed ; bcf pir1, tmr1if
1997 microchip technology inc. ds31012a-page 12-11 section 12. timer1 timer1 12 example 12-6: timer1 initialization (external oscillator clock source) clrf t1con ; stop timer1, internal clock source, ; t1 oscillator disabled, prescaler = 1:1 clrf tmr1h ; clear timer1 high byte register clrf tmr1l ; clear timer1 low byte register clrf intcon ; disable interrupts bsf status, rp0 ; bank1 clrf pie1 ; disable peripheral interrupts bcf status, rp0 ; bank0 clrf pir1 ; clear peripheral interrupts flags movlw 0x3e ; external clock source with oscillator movwf t1con ; circuitry, 1:8 prescaler, clock source ; is asynchronous to device ; timer1 is stopped bsf t1con, tmr1on ; timer1 starts to increment ; ; the timer1 interrupt is disabled, do polling on the overflow bit ; t1_ovfl_wait btfss pir1, tmr1if goto t1_ovfl_wait ; ; timer has overflowed ; bcf pir1, tmr1if
picmicro mid-range mcu family ds31012a-page 12-12 1997 microchip technology inc. 12.12 design tips question 1: timer1 does not seem to be keeping accurate time. answer 1: there are a few reasons that this could occur 1. you should never write to timer1, where that could cause the loss of time. in most cases that means you should not write to the tmr1l register, but if the conditions are ok, you may write to the tmr1h register. normally you write to the tmr1h register if you want the timer1 over?w interrupt to be sooner then the full 16-bit time-out. 2. you should ensure the your layout uses good pcb layout techniques so that noise does not couple onto the timer1 oscillator lines.
1997 microchip technology inc. ds31012a-page 12-13 section 12. timer1 timer1 12 12.13 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to timer1 are: title application note # using timer1 in asynchronous clock mode an580 low power real time clock an582 yet another clock using the pic16c92x an649
picmicro mid-range mcu family ds31012a-page 12-14 1997 microchip technology inc. 12.14 revision history revision a this is the initial released revision of the timer1 module description.
1997 microchip technology inc. ds31013a page 13-1 m timer2 13 section 13. timer2 highlights this section of the manual contains the following major topics: 13.1 introduction ............................................................................................................... ...13-2 13.2 control register ........................................................................................................... 13-3 13.3 timer clock source......................................................................................................13- 4 13.4 timer (tmr2) and period (pr2) registers..................................................................13-4 13.5 tmr2 match output.....................................................................................................13-4 13.6 clearing the timer2 prescaler and postscaler.............................................................13-4 13.7 sleep operation ...........................................................................................................1 3-4 13.8 initialization ............................................................................................................. .....13-5 13.9 design tips ................................................................................................................ ..13-6 13.10 related application notes............................................................................................13-7 13.11 revision history .......................................................................................................... .13-8
picmicro mid-range mcu family ds31013a-page 13-2 1997 microchip technology inc. 13.1 introduction timer2 is an 8-bit timer with a prescaler, a postscaler, and a period register. using the prescaler and postscaler at their maximum settings, the over?w time is the same as a 16-bit timer. timer2 is the pwm time-base when the ccp module(s) is used in the pwm mode. figure 13-1 shows a block diagram of timer2. the postscaler counts the number of times that the tmr2 register matched the pr2 register. this can be useful in reducing the overhead of the interrupt service routine on the cpu performance. figure 13-1: timer2 block diagram comparator tmr2 sets ?g tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note: tmr2 register output can be software selected by the ssp module as a baud clock. to toutps3:toutps0 t2ckps1:t2ckps0
1997 microchip technology inc. ds31013a-page 13-3 section 13. timer2 timer2 13 13.2 control register register 13-1 shows the timer2 control register. register 13-1: t2con: timer2 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as '0' bit 6:3 toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale ? ? ? 1111 = 1:16 postscale bit 2 tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1:0 t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31013a-page 13-4 1997 microchip technology inc. 13.3 timer clock source the timer2 module has one source of input clock, the device clock (f osc /4). a prescale option of 1:1, 1:4 or 1:16 is software selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). 13.4 timer (tmr2) and period (pr2) registers the tmr2 register is readable and writable, and is cleared on all device resets. timer2 incre- ments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. tmr2 is cleared when a wdt, por, mclr , or a bor reset occurs, while the pr2 register is set. timer2 can be shut off (disabled from incrementing) by clearing the tmr2on control bit (t2con<2>). this minimizes the power consumption of the module. 13.5 tmr2 match output the match output of tmr2 goes to two sources: 1. timer2 postscaler 2. ssp clock input there are four bits which select the postscaler. this allows the postscaler a 1:1 to 1:16 scaling (inclusive). after the postscaler over?ws, the tmr2 interrupt ?g bit (tmr2if) is set to indicate the timer2 over?w. this is useful in reducing the software overhead of the timer2 interrupt ser- vice routine, since it will only execute once every postscaler # of matches. the match output of tmr2 is also routed to the synchronous serial port module, which may soft- ware select this as the clock source for the shift clock. 13.6 clearing the timer2 prescaler and postscaler the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (power-on reset, mclr reset, watchdog timer reset, brown-out reset, or parity error reset) 13.7 sleep operation during sleep, tmr2 will not increment. the prescaler will retain the last prescale count, ready for operation to resume after the device wakes from sleep. table 13-1: registers associated with timer2 note: when t2con is written tmr2 does not clear. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor, per value on all other resets intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u pir tmr2if (1) 00 pie tmr2ie (1) 00 tmr2 timer2 modules register 0000 0000 0000 0000 t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as ?'. shaded cells are not used by the timer2 module. note 1: the position of this bit is device dependent.
1997 microchip technology inc. ds31013a-page 13-5 section 13. timer2 timer2 13 13.8 initialization example 13-1 shows how to initialize the timer2 module, including specifying the timer2 pres- caler and postscaler. example 13-1: timer2 initialization clrf t2con ; stop timer2, prescaler = 1:1, ; postscaler = 1:1 clrf tmr2 ; clear timer2 register clrf intcon ; disable interrupts bsf status, rp0 ; bank1 clrf pie1 ; disable peripheral interrupts bcf status, rp0 ; bank0 clrf pir1 ; clear peripheral interrupts flags movlw 0x72 ; postscaler = 1:15, prescaler = 1:16 movwf t2con ; timer2 is off bsf t2con, tmr2on ; timer2 starts to increment ; ; the timer2 interrupt is disabled, do polling on the overflow bit ; t2_ovfl_wait btfss pir1, tmr2if ; has tmr2 interrupt occurred? goto t2_ovfl_wait ; no, continue loop ; ; timer has overflowed ; bcf pir1, tmr2if ; yes, clear flag and continue.
picmicro mid-range mcu family ds31013a-page 13-6 1997 microchip technology inc. 13.9 design tips no related design tips at this time.
1997 microchip technology inc. ds31013a-page 13-7 section 13. timer2 timer2 13 13.10 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the timer2 module are: title application note # using the ccp module an594 air flow control using fuzzy logic an600 adaptive differential pulse code modulation using picmicros an643
picmicro mid-range mcu family ds31013a-page 13-8 1997 microchip technology inc. 13.11 revision history revision a this is the initial released revision of the timer2 module description.
1997 microchip technology inc. ds31014a page 14-1 m ccp 14 section 14. compare/capture/pwm (ccp) highlights this section of the manual contains the following major topics: 14.1 introduction ............................................................................................................... ...14-2 14.2 control register ........................................................................................................... 14-3 14.3 capture mode ..............................................................................................................1 4-4 14.4 compare mode ............................................................................................................14- 6 14.5 pwm mode ..................................................................................................................1 4-8 14.6 initialization ............................................................................................................. ...14-12 14.7 design tips ................................................................................................................ 14-15 14.8 related application notes..........................................................................................14-17 14.9 revision history .........................................................................................................14 -18
picmicro mid-range mcu family ds31014a-page 14-2 1997 microchip technology inc. 14.1 introduction each ccp (capture/compare/pwm) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a 10-bit pwm master/slave duty cycle register. the ccp modules are identical in operation, with the exception of the operation of the special event trigger. each ccp module has 3 registers. multiple ccp modules may exist on a single device. through- out this section we use generic names for the ccp registers. these generic names are shown in table 14-1 . table 14-1: speci? to generic ccp nomenclature table 14-2 shows the resources of the ccp modules, in each of its modes. while table 14-3 shows the interactions between the ccp modules, where ccpx is one ccp module and ccpy is another ccp module. table 14-2: ccp mode - timer resource table 14-3: interaction of two ccp modules generic name ccp1 ccp2 comment ccpxcon ccp1con ccp2con ccp control register ccprxh ccpr1h ccpr2h ccp high byte ccprxl ccpr1l ccpr2l ccp low byte ccpx ccp1 ccp2 ccp pin ccp mode timer resource capture compare pwm timer1 timer1 timer2 ccpx mode ccpy mode interaction capture capture same tmr1 time-base. capture compare the compare should be con?ured for the special event trigger, which clears tmr1. compare compare the compare(s) should be con?ured for the special event trigger, which clears tmr1. pwm pwm the pwms will have the same frequency, and update rate (tmr2 interrupt). pwm capture none pwm compare none
1997 microchip technology inc. ds31014a-page 14-3 section 14. ccp ccp 14 14.2 control register register 14-1: ccpxcon register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 bit 7:6 unimplemented: read as '0' bit 5:4 dcxb1:dcxb0 : pwm duty cycle bit1 and bit0 capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs (bit1 and bit0) of the 10-bit pwm duty cycle. the upper eight bits (dcx9:dcx2) of the duty cycle are found in ccprxl. bit 3:0 ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm off (resets ccpx module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, initialize ccp pin low, on compare match force ccp pin high (ccpif bit is set) 1001 = compare mode, initialize ccp pin high, on compare match force ccp pin low (ccpif bit is set) 1010 = compare mode, generate software interrupt on compare match (ccpif bit is set, ccp pin is unaffected) 1011 = compare mode, trigger special event (ccpif bit is set) 11xx = pwm mode legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31014a-page 14-4 1997 microchip technology inc. 14.3 capture mode in capture mode, ccprxh:ccprxl captures the 16-bit value of the tmr1 register when an event occurs on pin ccpx. an event is de?ed as: every falling edge every rising edge every 4th rising edge every 16th rising edge an event is selected by control bits ccpxm3:ccpxm0 (ccpxcon<3:0>). when a capture is made, the interrupt request ?g bit, ccpxif, is set. the ccpxif bit must be cleared in software. if another capture occurs before the value in register ccprx is read, the previous captured value will be lost. as can be seen in figure 14-1 , a capture does not reset the 16-bit tmr1 register. this is so timer1 can also be used as the timebase for other operations. the time between two captures can easily be computed as the difference between the value of the second capture that of the ?st capture. when timer1 over?ws, the tmr1if bit will be set and if enabled an interrupt will occur, allowing the time base to be extended to greater than 16-bits. 14.3.1 ccp pin con?uration in capture mode, the ccpx pin should be con?ured as an input by setting its corresponding tris bit. figure 14-1: capture mode operation block diagram the prescaler can be used to get a very ?e average resolution on a constant input frequency. for example, if we have a stable input frequency and we set the prescaler to 1:16, then the total error for those 16 periods is 1 t cy . this gives an effective resolution of t cy /16, which at 20 mhz is 12.5 ns. this technique is only valid where the input frequency is ?table over the 16 samples. without using the prescaler (1:1), each sample would have a resolution of t cy . note: timer1 must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. note: if the ccpx pin is con?ured as an output, a write to the port can cause a capture condition. ccprxh ccprxl tmr1h tmr1l set ?g bit ccpxif capture enable qs ccpxcon<3:0> ccpx pin prescaler ? 1, 4, 16 and edge detect
1997 microchip technology inc. ds31014a-page 14-5 section 14. ccp ccp 14 14.3.2 changing between capture modes when the capture mode is changed, a capture interrupt may be generated. the user should keep the ccpxie bit clear to disable these interrupts and should clear the ccpxif ?g bit following any such change in operating mode. 14.3.2.1 ccp prescaler there are four prescaler settings, speci?d by bits ccpxm3:ccpxm0. whenever the ccp mod- ule is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescale setting to another may generate an interrupt. also, the pres- caler counter will not be cleared, therefore the ?st capture may be from a nonzero prescaler. example 14-1 shows the recommended method for switching between capture prescale settings. this example also clears the prescaler counter and will not generate the interrupt. example 14-1: changing between capture prescalers to clear the capture prescaler count, the ccp module must be con?ured into any non-capture ccp mode (compare, pwm, or ccp off modes). 14.3.3 sleep operation when the device is placed in sleep, timer1 will not increment (since it is in synchronous mode), but the prescaler will continue to count events (not synchronized). when a speci?d capture event occurs, the ccpxif bit will be set, but the capture register will not be updated. if the ccp interrupt is enabled, the device will wake-up from sleep. the value in the 16-bit tmr1 register is not transferred to the 16-bit capture register, but since the timer was not incrementing, this value should not have any meaning. effectively, this allows the ccp pin to be used as another external interrupt. 14.3.4 effects of a reset the ccp module is off, and the value in the capture prescaler is forced to 0. clrf ccp1con ; turn ccp module off movlw new_capt_ps ; load the w reg with the new prescaler ; mode value and ccp on movwf ccp1con ; load ccp1con with this value
picmicro mid-range mcu family ds31014a-page 14-6 1997 microchip technology inc. 14.4 compare mode in compare mode, the 16-bit ccprx register value is constantly compared against the tmr1 register pair value. when a match occurs, the ccpx pin is: driven high driven low remains unchanged the action on the pin is based on the value of control bits ccpxm3:ccpxm0 (ccpxcon<3:0>). at the same time, a compare interrupt is also generated. figure 14-2: compare mode operation block diagram note: timer1 must be running in timer mode or synchronized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. ccprxh ccprxl tmr1h tmr1l comparator qs r output logic special event trigger set ?g bit ccpxif match ccpx pin tris ccpxcon<3:0> mode select output enable
1997 microchip technology inc. ds31014a-page 14-7 section 14. ccp ccp 14 14.4.1 ccp pin operation in compare mode the user must con?ure the ccpx pin as an output by clearing the appropriate tris bit. selecting the compare output mode, forces the state of the ccp pin to the state that is opposite of the match state. so if the compare mode is selected to force the output pin low on match, then the output will be forced high until the match occurs (or the mode is changed). 14.4.2 software interrupt mode when generate software interrupt mode is chosen, the ccpx pin is not affected. only a ccp interrupt is generated (if enabled). 14.4.3 special event trigger in this mode, an internal hardware trigger is generated which may be used to initiate an action. the special event trigger output of ccpx resets the tmr1 register pair. this allows the ccprx register to effectively be a 16-bit programmable period register for timer1. for some devices, the special trigger output of the ccp module resets the tmr1 register pair, and starts an a/d conversion (if the a/d module is enabled). 14.4.4 sleep operation when the device is placed in sleep, timer1 will not increment (since in synchronous mode), and the state of the module will not change. if the ccp pin is driving a value, it will continue to drive that value. when the device wakes-up, it will continue form this state. 14.4.5 effects of a reset the ccp module is off. note: clearing the ccpxcon register will force the ccpx compare output latch to the default low level. this is not the port i/o data latch. note: the special event trigger will not set the timer1 interrupt ?g bit, tmr1if.
picmicro mid-range mcu family ds31014a-page 14-8 1997 microchip technology inc. 14.5 pwm mode in pulse width modulation (pwm) mode, the ccpx pin produces up to a 10-bit resolution pwm output. since the ccpx pin is multiplexed with the port data latch, the corresponding tris bit must be cleared to make the ccpx pin an output. figure 14-3 shows a simpli?d block diagram of the ccp module in pwm mode. for a step by step procedure on how to set up the ccp module for pwm operation, see subsec- tion 14.5.3 ?et-up for pwm operation. figure 14-3: simpli?d pwm block diagram a pwm output ( figure 14-4 ) has a time-base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 14-4: pwm output note: clearing the ccpxcon register will force the ccpx pwm output latch to the default low level. this is not the port i/o data latch. ccprxl ccprxh (slave) comparator tmr2 comparator pr2 r q s duty cycle registers ccpxcon<5:4> clear timer, ccpx pin and latch the duty cycle tris ccpx timer2 module (note 1) 8 8 10 10 10 ccp module note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time-base. (dcxb9:dcxb2) (dcxb1:dcxb0) period = pr2 + 1 tmr2 = pr2 + 1, tmr2 forced to 0h tmr2 = duty cycle tmr2 = pr2 + 1, tmr2 forced to 0h duty cycle = dcxb9:dcxb0
1997 microchip technology inc. ds31014a-page 14-9 section 14. ccp ccp 14 14.5.1 pwm period the pwm period is speci?d by writing to the pr2 register. the pwm period can be calculated using the following formula: pwm period = [(pr2) + 1] ?4 ?t osc ?(tmr2 prescale value), speci?d in units of time pwm frequency (f pwm ) is de?ed as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the ccpx pin is set (exception: if pwm duty cycle = 0%, the ccpx pin will not be set) the pwm duty cycle is latched from ccprxl into ccprxh 14.5.2 pwm duty cycle the pwm duty cycle is speci?d by writing to the ccprxl register and to the dcxb1:dcxb0 (ccpxcon<5:4>) bits. up to 10-bit resolution is available: the ccprxl contains the eight msbs and ccpxcon<5:4> contains the two lsbs. this 10-bit value is represented by dcxb9:dcxb0. the following equation is used to calculate the pwm duty cycle: pwm duty cycle = (dcxb9:dcxb0 bits value) ?tosc ?(tmr2 prescale value), in units of time the dcxb9:dcxb0 bits can be written to at any time, but the duty cycle value is not latched into ccprxh until after a match between pr2 and tmr2 occurs (which is the end of the current period). in pwm mode, ccprxh is a read-only register. the ccprxh register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when ccprxh and 2-bit latch match the value of tmr2 concatenated with the internal 2-bit q clock (or two bits of the tmr2 prescaler), the ccpx pin is cleared. this is the end of the duty cycle. maximum pwm resolution (bits) for a given pwm frequency: note: the timer2 postscaler is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. note: if the pwm duty cycle value is longer than the pwm period, the ccpx pin will not be cleared. this allows a duty cycle of 100%. log ( f pwm log(2) f osc ) bits =
picmicro mid-range mcu family ds31014a-page 14-10 1997 microchip technology inc. 14.5.2.2 minimum resolution the minimum resolution (in time) of each bit of the pwm duty cycle depends on the prescaler of timer2. table 14-4: minimum duty cycle bit time example 14-2: pwm period and duty cycle calculation at most, an 8-bit resolution duty cycle can be obtained from a 78.125 khz frequency and a 20 mhz oscillator, i.e., 0 dcxb9:dcxb0 255. any value greater than 255 will result in a 100% duty cycle. in order to achieve higher resolution, the pwm frequency must be decreased. in order to achieve higher pwm frequency, the resolution must be decreased. table 14-5 lists example pwm frequencies and resolutions for fosc = 20 mhz. the tmr2 pres- caler and pr2 values are also shown. table 14-5: example pwm frequencies and bit resolutions at 20 mhz prescaler value t2ckps1:t2ckps0 minimum resolution (time) 10 0 t osc 40 1 t cy 16 1 x 4 t cy desired pwm frequency is 78.125 khz, fosc = 20 mhz tmr2 prescale = 1 1/78.125 khz= [(pr2) + 1] ?4 ?1/20 mhz ?1 12.8 m s = [(pr2) + 1] ?4 ?50 ns ?1 pr2 = 63 find the maximum resolution of the duty cycle that can be used with a 78.125 khz frequency and 20 mhz oscillator: 1/78.125 khz= 2 pwm resolution ?1/20 mhz ?1 12.8 m s= 2 pwm resolution ?50 ns ?1 256 = 2 pwm resolution log(256) = (pwm resolution) ?log(2) 8.0 = pwm resolution pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescaler (1, 4, 16) 1641111 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 5.5
1997 microchip technology inc. ds31014a-page 14-11 section 14. ccp ccp 14 14.5.3 set-up for pwm operation the following steps con?ure the ccp module for pwm operation: 1. establish the pwm period by writing to the pr2 register. 2. establish the pwm duty cycle by writing to the dcxb9:dcxb0 bits. 3. make the ccpx pin an output by clearing the appropriate tris bit. 4. establish the tmr2 prescale value and enable timer2 by writing to t2con. 5. con?ure the ccp module for pwm operation. 14.5.4 sleep operation when the device is placed in sleep, timer2 will not increment, and the state of the module will not change. if the ccp pin is driving a value, it will continue to drive that value. when the device wakes-up, it will continue from this state. 14.5.5 effects of a reset the ccp module is off.
picmicro mid-range mcu family ds31014a-page 14-12 1997 microchip technology inc. 14.6 initialization the ccp module has three modes of operation. example 14-3 shows the initialization of capture mode, example 14-4 shows the initialization of compare mode, and example 14-5 shows the ini- tialization of pwm mode. example 14-3: capture initialization clrf ccp1con ; ccp module is off clrf tmr1h ; clear timer1 high byte clrf tmr1l ; clear timer1 low byte clrf intcon ; disable interrupts and clear t0if bsf status, rp0 ; bank1 bsf trisc, ccp1 ; make ccp pin input clrf pie1 ; disable peripheral interrupts bcf status, rp0 ; bank0 clrf pir1 ; clear peripheral interrupts flags movlw 0x06 ; capture mode, every 4th rising edge movwf ccp1con ; bsf t1con, tmr1on ; timer1 starts to increment ; ; the ccp1 interrupt is disabled, ; do polling on the ccp interrupt flag bit ; capture_event btfss pir1, ccp1if goto capture_event ; ; capture has occurred ; bcf pir1, ccp1if ; this needs to be done before next compare
1997 microchip technology inc. ds31014a-page 14-13 section 14. ccp ccp 14 example 14-4: compare initialization clrf ccp1con ; ccp module is off clrf tmr1h ; clear timer1 high byte clrf tmr1l ; clear timer1 low byte clrf intcon ; disable interrupts and clear t0if bsf status, rp0 ; bank1 bcf trisc, ccp1 ; make ccp pin output if controlling state of pin clrf pie1 ; disable peripheral interrupts bcf status, rp0 ; bank0 clrf pir1 ; clear peripheral interrupts flags movlw 0x08 ; compare mode, set ccp1 pin on match movwf ccp1con ; bsf t1con, tmr1on ; timer1 starts to increment ; ; the ccp1 interrupt is disabled, ; do polling on the ccp interrupt flag bit ; compare_event btfss pir1, ccp1if goto compare_event ; ; compare has occurred ; bcf pir1, ccp1if ; this needs to be done before next compare
picmicro mid-range mcu family ds31014a-page 14-14 1997 microchip technology inc. example 14-5: pwm initialization clrf ccp1con ; ccp module is off clrf tmr2 ; clear timer2 movlw 0x7f ; movwf pr2 ; movlw 0x1f ; movwf ccpr1l ; duty cycle is 25% of pwm period clrf intcon ; disable interrupts and clear t0if bsf status, rp0 ; bank1 bcf trisc, pwm1 ; make pin output clrf pie1 ; disable peripheral interrupts bcf status, rp0 ; bank0 clrf pir1 ; clear peripheral interrupts flags movlw 0x2c ; pwm mode, 2 lsbs of duty cycle = 10 movwf ccp1con ; bsf t2con, tmr2on ; timer2 starts to increment ; ; the ccp1 interrupt is disabled, ; do polling on the tmr2 interrupt flag bit ; pwm_period_match btfss pir1, tmr2if goto pwm_period_match ; ; update this pwm period and the following pwm duty cycle ; bcf pir1, tmr2if
1997 microchip technology inc. ds31014a-page 14-15 section 14. ccp ccp 14 14.7 design tips question 1: what timers can i use for the capture and compare modes? answer 1: the capture and compare modes are designed around timer1, so no other timer can be used for these functions. this also means that if multiple ccp modules (in parts with more than one) are being used for a capture or compare function, they will share the same timer. question 2: what timers can i use with the pwm mode? answer 2: the pwm mode is designed around timer2, so no other timer can be used for this function. (it is the only timer with a period register associated with it.) if multiple ccp modules (in parts with more than one) are doing pwm they will share the same timer, meaning they will have the same pwm period and frequency. question 3: can i use one ccp module to do capture (or compare) and pwm at the same time, since they use different timers as their reference? answer 3: the timers may be different, but other logic functions are shared. however you can switch from one mode to the other. for a device with two ccp modules, you can also have ccp1 set up for pwm and ccp2 set up for capture or compare (or vice versa) since they are two independent modules. question 4: how does a reset affect the ccp module? answer 4: any reset will turn the ccp module off. see the section on resets to see reset values. question 5: i am setting up the ccp1con module for ?ompare mode, trigger special event ( 1011 ) which resets tmr1. when a compare match occurs, will i have both the tmr1 and the ccp1 interrupts pending (tmr1if is set, ccp1if is set)? answer 5: the ccp1if ?g will be set on the match condition. tmr1if is set when timer1 over?ws, and the special trigger reset of timer1 is not considered an over?w. however, if both the ccpr1l and ccpr1h registers are set at ffh, then an over?w occurs at the same time as the match, which will then set both ccp1if and tmr1if. question 6: how do i use timer2 as a general purpose timer, with an interrupt ?g on rollover? answer 6: timer2 always resets to zero when it equals pr2 and ?g bit tmr2if always gets set at this time. by putting ffh into pr2, you will get an interrupt on over?w at ffh, as you would with timer0, for instance. quite often it is desirable to have an event occur at a periodic rate, perhaps an inter- rupt driven event. normally an initial value would be placed into the timer so that the over?w will occur at the desired time. this value would have to be placed back into the timer every time it over?wed to make the interrupts occur at the same desired rate. the bene? of timer2 is that a value can be written to pr2 that will cause it to reset at your desired time interval. this means you do not have the housekeeping chore of reloading the timer every time it over?ws, since pr2 maintains its value.
picmicro mid-range mcu family ds31014a-page 14-16 1997 microchip technology inc. question 7: i am using a ccp module in pwm mode. the duty cycle being output is almost always 100%, even when my program writes a value like 7fh to the duty cycle register, which should be 50%. what am i doing wrong? answer 7: 1. the value in ccprxl is higher than pr2. this happens quite often when a user desires a fast pwm output frequency and will write a small value in the pr2. in this case, if a value of 7eh were written to pr2, then a value 7fh in ccprxl will result in 100% duty cycle. 2. if the tris bit corresponding to the ccp output pin you are using is con?ured as an input, the pwm output cannot drive the pin. in this case the pin would ?at and duty cycle may appear to be 0%, 100% or some other ?ating value. question 8: i want to determine a signal frequency using the ccp module in capture mode to ?d the period. i am currently resetting timer1 on the ?st edge, then using the value in the capture register on the second edge as the time period. the problem is that my code to clear the timer does not occur until almost twelve instructions after the ?st capture edge (interrupt latency plus saving of registers in interrupt) so i cannot measure very fast frequen- cies. is there a better way to do this? answer 8: you do not need to zero the counter to ?d the difference between two pulse edges. just take the ?st captured value and put it into another set of registers. then when the second capture event occurs, just subtract the ?st event from the second. assuming that your pulse edges are not so far apart that the counter can wrap around past the last capture value, the answer will always be correct. this is illustrated by the following example: 1. first captured value is fffeh. store this value in two registers. 2. the second capture value is 0001h (the counter has incremented three times). 3. 0001h - fffeh = 0003, which is the same as if you had cleared timer1 to zero and let it count to 3. (theoretically, except that there was a delay getting to the code that clears timer1, so actual values would differ). the interrupt overhead is now less important because the values are captured automatically. for even faster inputs do not enable interrupts and just test the ?g bit in a loop. if you must also capture very long time periods, such that the timer can wrap around past the previous capture value, then consider using an auto-scaling technique that starts with a large prescale and shorten the prescale as you converge on the exact frequency.
1997 microchip technology inc. ds31014a-page 14-17 section 14. ccp ccp 14 14.8 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the ccp modules are: title application note # using the ccp modules an594 implementing ultrasonic ranging an597 air flow control using fuzzy logic an600 adaptive differential pulse code modulation an643
picmicro mid-range mcu family ds31014a-page 14-18 1997 microchip technology inc. 14.9 revision history revision a this is the initial released revision of the ccp module description.
1997 microchip technology inc. ds31015a page 15-1 m ssp 15 section 15. synchronous serial port (ssp) highlights this section of the manual contains the following major topics: 15.1 introduction ............................................................................................................... ...15-2 15.2 control registers .........................................................................................................1 5-3 15.3 spi mode ................................................................................................................... ..15-6 15.4 ssp i 2 c operation .....................................................................................................15-16 15.5 initialization ............................................................................................................. ...15-26 15.6 design tips ................................................................................................................ 15-28 15.7 related application notes..........................................................................................15-29 15.8 revision history .........................................................................................................15 -30 note: please refer to appendix c.2 or the device data sheet to determine which devices use this module. i 2 c is a trademark of philips corporation.
picmicro mid-range mcu family ds31015a-page 15-2 1997 microchip technology inc. 15.1 introduction the synchronous serial port (ssp) module is a serial interface useful for communicating with other peripherals or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the ssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) - slave mode - i/o slope control, and start and stop bit detection to ease software implementation of master and multi-master modes spi is a registered trademark of motorola corporation. i 2 c is a trademark of philips corporation.
1997 microchip technology inc. ds31015a-page 15-3 section 15. ssp ssp 15 15.2 control registers register 15-1: sspstat: synchronous serial port status register r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a p s r/w ua bf bit 7 bit 0 bit 7 smp: spi data input sample phase spi master mode 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi sla v e mode smp must be cleared when spi is used in slave mode bit 6 cke : spi clock edge select ( figure 15-3 , figure 15-4 , and figure 15-5 ) ckp = 0 (sspcon<4>) 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck ckp = 1 (sspcon<4>) 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p : stop bit (i 2 c mode only. this bit is cleared when the ssp module is disabled) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3 s : start bit (i 2 c mode only. this bit is cleared when the ssp module is disabled) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2 r/w : read/wr ite bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not a ck bit. 1 = read 0 = write bit 1 ua : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf : buffer full status bit receiv e (spi and i 2 c modes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty t r ansmit (i 2 c mode only) 1 = transmit in progress, sspbuf is full 0 = transmit complete, sspbuf is empty legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31015a-page 15-4 1997 microchip technology inc. register 15-2: sspcon: synchronous serial port control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol : write collision detect bit 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov : receive over?w indicator bit in spi mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of over?w, the data in sspsr is lost and the sspbuf is no longer updated. over?w can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting over?w. in master mode the over?w bit is not set since each new recep- tion (and transmission) is initiated by writing to the sspbuf register. 0 = no over?w in i 2 c mode: 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a ?on? care in transmit mode. sspov must be cleared in software in either mode. 0 = no over?w bit 5 sspen : synchronous serial port enable bit in both modes, when enabled, these pins must be properly con?ured as input or output. in spi mode: 1 = enables serial port and con?ures sck, sdo, sdi, and ss as the source of the serial port pins 0 = disables serial port and con?ures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and con?ures the sda and scl pins as the source of the serial port pins 0 = disables serial port and con?ures these pins as i/o port pins bit 4 ckp : clock polarity select bit in spi mode: 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c mode: sck release control 1 = enable clock 0 = holds clock low (clock stretch) (used to ensure data setup time)
1997 microchip technology inc. ds31015a-page 15-5 section 15. ssp ssp 15 bit 3:0 sspm3:sspm0 : synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = reserved 1001 = reserved 1010 = reserved 1011 = i 2 c firmware controlled master mode (slave idle) 1100 = reserved 1101 = reserved 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset register 15-2: sspcon: synchronous serial port control register (contd)
picmicro mid-range mcu family ds31015a-page 15-6 1997 microchip technology inc. 15.3 spi mode the spi mode allows 8-bits of data to be synchronously transmitted and received simulta- neously. all four modes of spi are supported, as well as microwire (sample edge) when the spi is in the master mode. to accomplish communication, typically three pins are used: serial data out (sdo) serial data in (sdi) serial clock (sck) additionally a fourth pin may be used when in a slave mode of operation: slave select (ss ) 15.3.1 operation when initializing the spi, several options need to be speci?d. this is done by programming the appropriate control bits in the sspcon register (sspcon<5:0>) and sspstat<7:6>. these control bits allow the following to be speci?d: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) clock edge (output data on rising/falling edge of sck) data input sample phase clock rate (master mode only) slave select mode (slave mode only) figure 15-1 shows the block diagram of the ssp module, when in spi mode. figure 15-1: ssp block diagram (spi mode) read write internal data bus sdi sdo ss sck sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t cy prescaler 4, 16, 64 tris bit of sck pin 2 edge select 2 4
1997 microchip technology inc. ds31015a-page 15-7 section 15. ssp ssp 15 the ssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb ?st. the sspbuf holds the data that was written to the sspsr, until the received data is ready. once the 8-bits of data have been received, that byte is moved to the sspbuf register. then the buffer full detect bit, bf (sspstat<0>), and interrupt ?g bit, sspif, are set. this double buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored, and the write collision detect bit, wcol (sspcon<7>), will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the sspbuf register completed suc- cessfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit, bf (sspstat<0>), indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally the ssp interrupt is used to determine when the transmis- sion/reception has completed. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 15-1 shows the loading of the sspbuf (sspsr) for data transmission. the shaded instruction is only required if the received data is meaningful (some spi applications are transmit only). example 15-1: loading the sspbuf (sspsr) register the sspsr is not directly readable or writable, and can only be accessed from addressing the sspbuf register. additionally, the ssp status register (sspstat) indicates the various status conditions. bcf status, rp1 ;specify bank1 bsf status, rp0 ; loop btfss sspstat, bf ;has data been received (transmit complete)? goto loop ;no bcf status, rp0 ;specify bank0 movf sspbuf, w ;w reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit microwire is a trademark of national semiconductor.
picmicro mid-range mcu family ds31015a-page 15-8 1997 microchip technology inc. 15.3.2 enabling spi i/o to enable the serial port the ssp enable bit, sspen (sspcon<5>), must be set. to reset or recon?ure spi mode, clear the sspen bit which re-initializes the sspcon register, and then set the sspen bit. this con?ures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port function, they must have their data direction bits (in the tris register) appropriately programmed. that is: sdi must have the tris bit set sdo must have the tris bit cleared sck (master mode) must have the tris bit cleared sck (slave mode) must have the tris bit set ?s must have the tris bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. an example would be in master mode where you are only sending data (to a display driver), then both sdi and ss could be used as general purpose outputs by clearing their corresponding tris register bits.
1997 microchip technology inc. ds31015a-page 15-9 section 15. ssp ssp 15 15.3.3 typical connection figure 15-2 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their programmed clock edge, and latched on the edge of the clock speci?d by the smp bit. both processors should be programmed to same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data trans- mission: master sends data slave sends dummy data master sends data slave sends data master sends dummy data slave sends data figure 15-2: spi master/slave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm3:sspm0 = 00xx b serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm3:sspm0 = 010x b serial clock
picmicro mid-range mcu family ds31015a-page 15-10 1997 microchip technology inc. 15.3.4 master operation the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2) is to broadcast data by the software protocol. in master mode the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be disabled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver appli- cations as a ?ine activity monitor mode. the clock polarity is selected by appropriately programming bit ckp (sspcon<4>). this then would give waveforms for spi communication as shown in figure 15-3 , figure 15-4 , and figure 15-5 where the msb is transmitted ?st. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: ? osc /4 (or t cy ) ? osc /16 (or 4 ?t cy ) ? osc /64 (or 16 ?t cy ) timer2 output/2 this allows a maximum data rate of 5 mbps (at 20 mhz). figure 15-3: spi mode waveform, master mode 4 clock modes input sample (smp = 0) input sample (smp = 1) sdi (smp = 0) bit7 bit0 sdo (cke = 0) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit0 sdi (smp = 1) sspif write to sspbuf sspsr to sspbuf sdo (cke = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck (ckp = 0, cke = 0) sck (ckp = 0, cke = 1) sck (ckp = 1, cke = 0) sck (ckp = 1, cke = 1) next q4 cycle after q2
1997 microchip technology inc. ds31015a-page 15-11 section 15. ssp ssp 15 15.3.5 slave operation in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the interrupt ?g bit sspif is set. the clock polarity is selected by appropriately programming bit ckp (sspcon<4>). this then would give waveforms for spi communication as shown in figure 15-3 , figure 15-4 , and figure 15-5 where the msb is transmitted ?st. when in slave mode the external clock must meet the minimum high and low times. in sleep mode, the slave can transmit and receive data. when a byte is received, the device will wake-up from sleep, if the interrupt is enabled. figure 15-4: spi mode waveform (slave mode with cke = 0) sck (ckp = 1, sck (ckp = 0, input sample (smp = 0) sdi bit7 bit0 sdo bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss optional next q4 cycle after q2 bit7
picmicro mid-range mcu family ds31015a-page 15-12 1997 microchip technology inc. 15.3.6 slave select mode when in slave select mode, the ss pin allows multi-drop for multiple slaves with a single master. the spi must be in slave mode (sspcon<3:0> = 04h) and the tris bit, for the ss pin, must be set for the slave select mode to be enabled. when the ss pin is low, trans- mission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte, and becomes a ?ating output. external pull-up/ pull-down resistors may be desirable, depending on the application. when the spi is in slave mode with ss pin control enabled, (sspcon<3:0> = 0100 ) the spi module will reset if the ss pin is set to v dd . if the spi is used in slave mode with the cke bit is set, then the ss pin control must be enabled. when the spi module resets, the bit counter is forced to 0. this can be done by either by forcing the ss pin to a high level or clearing the sspen bit ( figure 15-6 ). to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver the sdo pin can be con?ured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus con?ct. figure 15-5: spi mode waveform (slave select mode with cke = 1) sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif interrupt (smp = 0) cke = 1) cke = 1) (smp = 0) write to sspbuf sspsr to sspbuf ss flag not optional next q4 cycle after q2
1997 microchip technology inc. ds31015a-page 15-13 section 15. ssp ssp 15 figure 15-6: slave synchronization waveform sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 sdo bit7 bit6 bit7 sspif interrupt (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss flag bit0 bit7 bit0
picmicro mid-range mcu family ds31015a-page 15-14 1997 microchip technology inc. 15.3.7 sleep operation in master mode all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from sleep. after the device returns to normal mode, the module will continue to transmit/receive data. in slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode, and data to be shifted into the spi transmit/receive shift register. when all 8-bits have been received, the ssp interrupt ?g bit will be set and if enabled will wake the device from sleep.
1997 microchip technology inc. ds31015a-page 15-15 section 15. ssp ssp 15 15.3.8 effects of a reset a reset disables the ssp module and terminates the current transfer. table 15-1: registers associated with spi operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie t0ie inte rbie (2) t0if intf rbif (2) 0000 000x 0000 000u pir sspif (1) 00 pie sspie (1) 00 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 trisa porta data direction register --11 1111 --11 1111 trisc portc data direction control register 1111 1111 1111 1111 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the ssp in spi mode. note 1: the position of this bit is device dependent. 2: these bits may also be named gpie and gpif.
picmicro mid-range mcu family ds31015a-page 15-16 1997 microchip technology inc. 15.4 ssp i 2 c operation the ssp module in i 2 c mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate software implementations of the master functions. the ssp module implements the standard mode speci?ations as well as 7-bit and 10-bit addressing. appendix a gives an overview of the i 2 c bus speci?ation. two pins are used for data transfer. these are the scl pin, which is the clock, and the sda pin, which is the data. the user must con?ure these pins as inputs through the tris bits. the ssp module functions are enabled by setting ssp enable bit, sspen (sspcon<5>). a ?litch filter is on the scl and sda pins when the pin is an input. this ?ter operates in both the 100 khz and 400 khz modes. in the 100 khz mode, when these pins are an output, there is a slew rate control of the pin that is independent of device frequency. figure 15-7: ssp block diagram (i 2 c mode) read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus address match set, reset s, p bits (sspstat reg) scl shift clock msb lsb sda
1997 microchip technology inc. ds31015a-page 15-17 section 15. ssp ssp 15 the ssp module has ?e registers for i 2 c operation. they are: ssp control register (sspcon) ssp status register (sspstat) serial receive/transmit buffer (sspbuf) ssp shift register (sspsr) - not directly accessible ssp address register (sspadd) the sspcon register allows control of the i 2 c operation. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: ? 2 c slave mode (7-bit address) ? 2 c slave mode (10-bit address) ? 2 c firmware controlled multi-master mode (start and stop bit interrupts enabled) ? 2 c firmware controlled multi-master mode (start and stop bit interrupts enabled) ? 2 c firmware controlled master mode, slave is idle before selecting any i 2 c mode, the scl and sda pins must be programmed to inputs by setting the appropriate tris bits. selecting an i 2 c mode, by setting the sspen bit, enables the scl and sda pins to be used as the clock and data lines in i 2 c mode. the sspstat register gives the status of the data transfer. this information includes detection of a start or stop bit, speci?s if the received byte was data or address, if the next byte is the completion of 10-bit address, and if this will be a read or write data transfer. the sspbuf is the register to which transfer data is written to or read from. the sspsr register shifts the data in or out of the device. in receive operations, the sspbuf and sspsr create a doubled buffered receiver. this allows reception of the next byte to begin before reading the last byte of received data. when the complete byte is received, it is transferred to the sspbuf reg- ister and ?g bit sspif is set. if another complete byte is received before the sspbuf register is read, a receiver over?w has occurred and the sspov bit (sspcon<6>) is set and the byte in the sspsr is lost. the sspadd register holds the slave address. in 10-bit mode, the user needs to write the high byte of the address ( 1111 0 a9 a8 0 ). following the high byte address match, the low byte of the address needs to be loaded (a7:a0).
picmicro mid-range mcu family ds31015a-page 15-18 1997 microchip technology inc. 15.4.1 slave mode in slave mode, the scl and sda pins must be con?ured as inputs (tris set). the ssp module will override the input state with the output data when required (slave-transmitter). when an address is matched or the data transfer after an address match is received, the hard- ware automatically will generate the acknowledge (a ck ) pulse, and then load the sspbuf reg- ister with the received value currently in the sspsr register. there are certain conditions that will cause the ssp module not to give this a ck pulse. these are if either (or both): a) the buffer full bit, bf (sspstat<0>), was set before the message completed. b) the over?w bit, sspov (sspcon<6>), was set before the message completed. in this case, the sspsr register value is not loaded into the sspbuf, but the sspif and sspov bits are set. table 15-2 shows what happens when a data transfer byte is received, given the sta- tus of bits bf and sspov. the shaded cells show the condition where user software did not prop- erly clear the over?w condition. flag bit bf is cleared by reading the sspbuf register while bit sspov is cleared through software. the scl clock input must have a minimum high and low time for proper operation. the high and low times of the i 2 c speci?ation as well as the requirement of the ssp module is shown in device data sheet electrical speci?ations parameters 100 and 101 .
1997 microchip technology inc. ds31015a-page 15-19 section 15. ssp ssp 15 15.4.1.1 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register on the falling edge of the eight scl pulse. b) the buffer full bit, bf, is set on the falling edge of the eigth scl pulse. c) an a ck pulse is generated. d) ssp interrupt ?g bit, sspif, is set (interrupt is generated if enabled) - on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the ?e most signi?ant bits (msbs) of the ?st address byte specify if this is a 10-bit address. the r/w bit (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address the ?st byte would equal 1111 0 a9 a8 0 ? where a9 and a8 are the two msbs of the address. the sequence of events for a 10-bit address is as follows, with steps 7- 9 for slave-transmitter: 1. receive ?st (high) byte of address (the sspif, bf, and ua (sspstat<1>) bits are set). 2. update the sspadd register with second (low) byte of address (clears the ua bit and releases the scl line). 3. read the sspbuf register (clears the bf bit) and clear the sspif ?g bit. 4. receive second (low) byte of address (the sspif, bf, and ua bits are set). 5. update the sspadd register with the high byte of address. this will clear the ua bit and releases scl line. 6. read the sspbuf register (clears the bf bit) and clear the sspif ?g bit. 7. receive repeated start condition. 8. receive ?st (high) byte of address (the sspif and bf bits are set). 9. read the sspbuf register (clears the bf bit) and clear the sspif ?g bit. table 15-2: data transfer received byte actions note: following the restart condition (step 7) in 10-bit mode, the user only needs to match the ?st 7-bit address. the user does not update the sspadd for the second half of the address. status bits as data transfer is received sspsr ? sspbuf generate a ck pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 ye s ye s ye s 10 no no yes 11 no no yes 0 1 ye s no ye s note:shaded cells show the conditions where the user software did not properly clear the over?w condition.
picmicro mid-range mcu family ds31015a-page 15-20 1997 microchip technology inc. 15.4.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte over?w condition exists, then no acknowledge (a ck ) pulse is given. an over?w condition is de?ed as either the bf bit (sspstat<0>) is set or the sspov bit (sspcon<6>) is set. so when a byte is received, with these conditions, and attempts to move from the sspsr register to the sspbuf register, no acknowledge pulse is given. an ssp interrupt is generated for each data transfer byte. the sspif ?g bit must be cleared in software. the sspstat register is used to determine the status of the receive byte. figure 15-8: i 2 c waveforms for reception (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read a ck receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 a ck r/w =0 receiving address sspif bf (sspstat<0>) sspov (sspcon<6>) a ck a ck is not sent.
1997 microchip technology inc. ds31015a-page 15-21 section 15. ssp ssp 15 figure 15-9: i 2 c waveforms for reception (10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 d7d6d5d4d3 d1d0 receive data byte a ck r/w = 0 a ck receive first byte of address cleared in software bus master terminates transfer d2 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated. ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf ?g a ck r/w = 1 cleared in software dummy read of sspbuf to clear bf ?g read of sspbuf clears bf ?g cleared by hardware when sspadd is updated.
picmicro mid-range mcu family ds31015a-page 15-22 1997 microchip technology inc. 15.4.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the a ck pulse will be sent on the ninth bit, and the scl pin is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then the scl pin should be enabled by setting the ckp bit (sspcon<4>). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretching the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time ( figure 15-10 ). an ssp interrupt is generated for each data transfer byte. the sspif ?g bit must be cleared in software, and the sspstat register is used to determine the status of the byte transfer. the sspif ?g bit is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the a ck pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not a ck ), then the data transfer is complete. when the not a ck is latched by the slave, the slave logic is reset and the slave then monitors for another occurrence of the start bit. if the sda line was low (a ck ), the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then the scl pin should be enabled by setting the ckp bit. figure 15-10: i 2 c waveforms for transmission (7-bit address) sda scl sspif bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 a ck d7 d6 d5 d4 d3 d2 d1 d0 a ck transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written-to before the ckp bit can be set) r/w = 0
1997 microchip technology inc. ds31015a-page 15-23 section 15. ssp ssp 15 figure 15-11: i 2 c waveforms for transmission (10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 1 1 1 1 0 a8 r/w =1 a ck a ck r/w = 0 a ck receive first byte of address cleared in software master sends nack a9 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated. ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated. sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf ?g receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 a ck d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf ?g sr cleared in software write of sspbuf initiates transmit cleared in software transmit is complete ckp has to be set for clock to be released bus master terminates transfer
picmicro mid-range mcu family ds31015a-page 15-24 1997 microchip technology inc. 15.4.1.4 clock arbitration clock arbitration has the scl pin to inhibit the master device from sending the next clock pulse. the ssp module in i 2 c slave mode will hold the scl pin low when the cpu needs to respond to the ssp interrupt (sspif bit is set and the ckp bit is cleared). the data that needs to be trans- mitted will need to be written to the sspbuf register, and then the ckp bit will need to be set to allow the master to generate the required clocks. 15.4.2 master mode (firmware) master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle with both the s and p bits clear. in master mode the scl and sda lines are manipulated by clearing the corresponding tris bit(s). the output level is always low, irrespective of the value(s) in the port register. so when transmitting data, a '1' data bit must have its tris bit set (input) and a '0' data bit must have its tris bit cleared (output). the same scenario is true for the scl line with the tris bit. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): start condition stop condition data transfer byte transmitted/received master mode of operation can be done with either the slave mode idle (sspm3:sspm0 = 1011 ) or with the slave active (sspm3:ssp0 = 1110 or 1111). when the slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. 15.4.3 multi-master mode (firmware) in multi-master mode, the interrupt generation on the detection of the start and stop condi- tions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat<4>) is set, or the bus is idle with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored to see if the signal level is the expected output level. this check only needs to be done when a high level is output. if a high level is expected and a low level is present, the device needs to release the sda and scl lines (set the tris bits). there are two stages where this arbitration can be lost, they are: address transfer data transfer when the slave logic is enabled, the slave continues to receive. if arbitration was lost during the address transfer stage, communication to the device may be in progress. if addressed an a ck pulse will be generated. if arbitration was lost during the data transfer stage, the device will need to retransfer the data at a later time.
1997 microchip technology inc. ds31015a-page 15-25 section 15. ssp ssp 15 15.4.4 sleep operation while in sleep mode, the i 2 c module can receive addresses or data, and when an address match or complete byte transfer occurs wake the processor from sleep (if the ssp interrupt is enabled). 15.4.5 effect of a reset a reset disables the ssp module and terminates the current transfer. table 15-3: registers associated with i 2 c operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie t0ie inte rbie (2) t0if intf rbif (2) 0000 000x 0000 000u pir sspif (1) 00 pie sspie (1) 00 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by ssp in i 2 c mode. note 1: the positions of these bits are device dependent. 2: these bits may also be named gpie and gpif.
picmicro mid-range mcu family ds31015a-page 15-26 1997 microchip technology inc. 15.5 initialization example 15-2: spi master mode initialization clrf status ; bank 0 clrf sspstat ; smp = 0, cke = 0, and clear status bits bsf sspstat, cke ; cke = 1 movlw 0x31 ; set up spi port, master mode, clk/16, movwf sspcon ; data xmit on falling edge (cke=1 & ckp=1) ; data sampled in middle (smp=0 & master mode) bsf status, rp0 ; bank 1 bsf pie, sspie ; enable ssp interrupt bcf status, rp0 ; bank 0 bsf intcon, gie ; enable, enabled interrupts movlw databyte ; data to be transmitted ; could move data from ram location movwf sspbuf ; start transmission
1997 microchip technology inc. ds31015a-page 15-27 section 15. ssp ssp 15 15.5.1 ssp module / basic ssp module compatibility when upgrading from the basic ssp module, the sspstat register contains two additional control bits. these bits are only used in spi mode and are: smp, spi data input sample phase cke, spi clock edge select to be compatible with the spi of the basic ssp module, these bits must be appropriately con?- ured. if these bits are not at the states shown in table 15-4 , improper spi communication may occur. table 15-4: new bit states for compatibility basic ssp module ssp module ckp ckp cke smp 1 100 0 000
picmicro mid-range mcu family ds31015a-page 15-28 1997 microchip technology inc. 15.6 design tips question 1: using spi mode, i do not seem able to talk to an spi device. answer 1: ensure that you are using the correct spi mode for that device. this spi supports all four spi modes so you should be able to get it to function. check the clock polarity and the clock phase. question 2: using i 2 c mode, i do not seem able to make the master mode work. answer 2: this ssp module does not have master mode fully automated in hardware, see application note an578 for software which uses the ssp module to implement master mode. if you require a fully automated hardware implementation of i 2 c master mode, please refer to the microchip line card for devices that have the master ssp module. question 3: using i 2 c mode, i write data to the sspbuf register, but the data did not transmit. answer 3: ensure that you set the ckp bit to release the i 2 c clock. note: at the time of printing only the high-end family of devices (pic17cxxx) have devices with the master ssp module implemented.
1997 microchip technology inc. ds31015a-page 15-29 section 15. ssp ssp 15 15.7 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the ssp module are: title application note # use of the ssp module in the i 2 c multi-master environment. an578 using microchip 93 series serial eeproms with microcontroller spi ports an613 software implementation of i 2 c bus master an554 use of the ssp module in the multi-master environment an578 interfacing pic16c64/74 to microchip spi serial eeprom an647 interfacing a microchip pic16c92x to microchip spi serial eeprom an668
picmicro mid-range mcu family ds31015a-page 15-30 1997 microchip technology inc. 15.8 revision history revision a this is the initial released revision of the ssp module description.
1997 microchip technology inc. ds31016a page 16-1 bssp 16 m section 16. basic sychronous serial port (bssp) highlights this section of the manual contains the following major topics: 16.1 introduction ............................................................................................................... ...16-2 16.2 control registers .........................................................................................................1 6-3 16.3 spi mode.................................................................................................................. 16-6 16.4 ssp i 2 c operation .....................................................................................................16-15 16.5 initialization ............................................................................................................. ...16-23 16.6 design tips ................................................................................................................ 16-24 16.7 related application notes..........................................................................................16-25 16.8 revision history .........................................................................................................16 -26 note: please refer to appendix c.2 or the device data sheet to determine which devices use this module. spi is a trademark of motorola corporation. i 2 c is a trademark of philips corporation.
picmicro mid-range mcu family ds31016a-page 16-2 1997 microchip technology inc. 16.1 introduction the basic synchronous serial port (bssp) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the bssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) - slave mode - i/o slope control, start and stop bits to ease software implementation of master and multi-master modes i 2 c is a trademark of philips corporation.
1997 microchip technology inc. ds31016a-page 16-3 section 16. bssp bssp 16 16.2 control registers register 16-1: sspstat: synchronous serial port status register u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 d/a p s r/w ua bf bit 7 bit 0 bit 7:6 unimplemented: read as '0' bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p : stop bit (i 2 c mode only. this bit is cleared when the ssp module is disabled) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3 s : start bit (i 2 c mode only. this bit is cleared when the ssp module is disabled) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not a ck bit. 1 = read 0 = write bit 1 ua : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf : buffer full status bit receiv e (spi and i 2 c modes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty t r ansmit (i 2 c mode only) 1 = transmit in progress, sspbuf is full 0 = transmit complete, sspbuf is empty legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31016a-page 16-4 1997 microchip technology inc. register 16-2: sspcon: synchronous serial port control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol : write collision detect bit 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov : receive over?w indicator bit in spi mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of over?w, the data in sspsr is lost. over?w can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting over?w. in master mode the over?w bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 0 = no over?w in i 2 c mode: 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a ?on? care in transmit mode. sspov must be cleared in software in either mode. 0 = no over?w bit 5 sspen : synchronous serial port enable bit in both modes, when enabled, these pins must be properly con?ured as input or output. in spi mode: 1 = enables serial port and con?ures sck, sdo, sdi, and ss as the source of the serial port pins 0 = disables serial port and con?ures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and con?ures the sda and scl pins as the source of the serial port pins 0 = disables serial port and con?ures these pins as i/o port pins bit 4 ckp : clock polarity select bit in spi mode: 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c mode: sck release control 1 = enable clock 0 = holds clock low (clock stretch) (used to ensure data setup time)
1997 microchip technology inc. ds31016a-page 16-5 section 16. bssp bssp 16 bit 3:0 sspm3:sspm0 : synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = reserved 1001 = reserved 1010 = reserved 1011 = i 2 c firmware controlled master mode (slave idle) 1100 = reserved 1101 = reserved 1110 = i 2 c firmware controlled multi-master mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c firmware controlled master mode, 10-bit address with start and stop bit interrupts enabled legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset register 16-2: sspcon: synchronous serial port control register (contd)
picmicro mid-range mcu family ds31016a-page 16-6 1997 microchip technology inc. 16.3 spi mode the spi mode allows 8-bits of data to be synchronously transmitted and received simulta- neously. to accomplish communication, typically three pins are used: serial data out (sdo) serial data in (sdi) serial clock (sck) additionally a fourth pin may be used when in a slave mode of operation: slave select (ss ) 16.3.1 operation when initializing the spi, several options need to be speci?d. this is done by programming the appropriate control bits in the sspcon register (sspcon<5:0>). these control bits allow the following to be speci?d: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (output/input data on the rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) figure 16-1 shows the block diagram of the ssp module, when in spi mode. figure 16-1: ssp block diagram (spi mode) read write internal data bus sdi sdo ss sck sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t cy prescaler 4, 16, 64 tris bit of sck pin 2 edge select 2 4 spi is a trademark of motorola corporations.
1997 microchip technology inc. ds31016a-page 16-7 section 16. bssp bssp 16 the ssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb ?st. the sspbuf holds the data that was previously written to the sspsr, until the received data is ready. once the 8-bits of data have been received, that information is moved to the sspbuf register. then the buffer full detect bit, bf (sspstat <0>), and interrupt ?g bit, sspif, are set. this double buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was received. any write to the sspbuf register during transmission/reception of data will be ignored, and the write collision detect bit, wcol (sspcon<7>), will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the sspbuf register completed suc- cessfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit, bf (ssp- stat<0>), indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally the ssp interrupt is used to determine when the transmis- sion/reception has completed. the sspbuf can then be read (if data is meaningful) and/or the sspbuf (sspsr) can be written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 16-1 shows the load- ing of the sspbuf (sspsr) for data transmission. the shaded instruction is only required if the received data is meaningful (some spi applications are transmit only). example 16-1: loading the sspbuf (sspsr) register the sspsr is not directly readable or writable, and can only be accessed from addressing the sspbuf register. additionally, the ssp status register (sspstat) indicates the various status conditions. bcf status, rp1 ;specify bank1 bsf status, rp0 ; loop btfss sspstat, bf ;has data been received (transmit complete)? goto loop ;no bcf status, rp0 ;specify bank0 movf sspbuf, w ;w reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit
picmicro mid-range mcu family ds31016a-page 16-8 1997 microchip technology inc. 16.3.2 enabling spi i/o to enable the serial port, ssp enable bit, sspen (sspcon<5>), must be set. to reset or recon- ?ure spi mode, clear the sspen bit which re-initializes the sspcon register, and then set the sspen bit. this con?ures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port function, they must have their data direction bits (in the tris register) appropriately programmed. that is: sdi must have the tris bit set sdo must have the tris bit cleared sck (master mode) must have the tris bit cleared sck (slave mode) must have the tris bit set ?s must have the tris bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. an example would be in master mode where you are only sending data (to a display driver), then both sdi and ss could be used as general purpose outputs by clearing their corresponding tris register bits.
1997 microchip technology inc. ds31016a-page 16-9 section 16. bssp bssp 16 16.3.3 typical connection figure 16-2 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge of the clock. both processors should be programmed to same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: master sends data slave sends dummy data master sends data slave sends data master sends dummy data slave sends data figure 16-2: spi master/slave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master (sspm3:sspm0 = 00xxb) serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave (sspm3:sspm0 = 010xb ) serial clock
picmicro mid-range mcu family ds31016a-page 16-10 1997 microchip technology inc. 16.3.4 master operation the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2) wishes to broadcast data by the software protocol. in master mode the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be disabled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver appli- cations as a ?ine activity monitor mode. the clock polarity is selected by appropriately programming the ckp bit (sspcon<4>). this then would give waveforms for spi communication as shown in figure 16-5 and figure 16-5 where the msb is transmitted ?st. in master mode, the spi clock rate (bit rate) is user program- mable to be one of the following: ? osc /4 (or t cy ) ? osc /16 (or 4 ?t cy ) ? osc /64 (or 16 ?t cy ) timer2 output/2 this allows a maximum data rate of 5 mbps (at 20 mhz). figure 16-3: spi mode waveform (master mode) sck (ckp = 0) sck (ckp = 1) sdo sdi sspif interrupt ?g bit7 bit7 bit0 bit6 bit5 bit4 bit3 bit2 bit1 bit0
1997 microchip technology inc. ds31016a-page 16-11 section 16. bssp bssp 16 16.3.5 slave operation in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched the sspif interrupt ?g bit is set. the clock polarity is selected by appropriately programming the ckp bit (sspcon<4>). this then would give waveforms for spi communication as shown in figure 16-5 and figure 16-5 where the msb is transmitted ?st. when in slave mode the external clock must meet the mini- mum high and low times. in sleep mode, the slave can transmit and receive data and wake the device from sleep if the interrupt is enabled. figure 16-4: spi mode waveform (slave mode w/o ss control) sck (ckp = 0) sck (ckp = 1) sdo sdi sspif interrupt ?g bit7 bit7 bit0 bit6 bit5 bit4 bit3 bit2 bit1 bit0 next q4 cycle after q2
picmicro mid-range mcu family ds31016a-page 16-12 1997 microchip technology inc. 16.3.6 slave select mode the ss pin allows a synchronous slave mode. the spi must be in slave mode (sspcon<3:0> = 04h) and the tris bit must be set the for the synchronous slave mode to be enabled. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte, and becomes a ?ating output. if the ss pin is taken low without resetting spi mode, the transmission will continue from the point at which it was taken high. to clear the bit counter the basic ssp module must be disabled and then re-enabled. external pull-up/pull-down resistors may be desirable, depending on the application. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver the sdo pin can be con?ured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus con?ct. figure 16-5: spi mode waveform (slave mode with ss control) sck (ckp = 0) sck (ckp = 1) sdo sdi sspif bit7 bit7 bit0 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ss next q4 cycle after q2
1997 microchip technology inc. ds31016a-page 16-13 section 16. bssp bssp 16 figure 16-6: slave synchronization waveform sck (ckp = 1) sck (ckp = 0) input sample sdi sdo bit7 bit6 bit5 sspif interrupt write to sspbuf sspsr to sspbuf ss flag bit0 bit5 bit0 bit7
picmicro mid-range mcu family ds31016a-page 16-14 1997 microchip technology inc. 16.3.7 sleep operation in master mode all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from sleep. after the device returns to normal mode, the module will continue to transmit/receive data. in slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode, and data to be shifted into the spi transmit/receive shift register. when all 8-bits have been received, the ssp interrupt ?g bit will be set and if enabled will wake the device from sleep. 16.3.8 effects of a reset a reset disables the ssp module and terminates the current transfer. table 16-1: registers associated with spi operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets intcon gie peie t0ie inte rbie (2) t0if intf rbif (2) 0000 000x 0000 000u pir sspif (1) 00 pie sspie (1) 00 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 sspstat d/a p s r/w ua bf --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the ssp in spi mode. note 1: the position of this bit is device dependent. 2: these bits can also be named gpie and gpif.
1997 microchip technology inc. ds31016a-page 16-15 section 16. bssp bssp 16 16.4 ssp i 2 c operation the ssp module in i 2 c mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate software implementations of the master functions. the ssp module implements the standard and fast mode speci?ations as well as 7-bit and 10-bit addressing. appendix a gives an overview of the i 2 c bus speci?ation. two pins are used for data transfer. these are the scl pin, which is the clock, and the sda pin, which is the data. the user must con?ure these pins as inputs through the tris bits. the ssp module functions are enabled by setting ssp enable bit, sspen (sspcon<5>). a ?litch ?ter is on the scl and sda pins when the pin is an input. this ?ter operates in both the 100 khz and 400 khz modes. in the 100 khz mode, when these pins are an output, there is a slew rate control of the pin that is independent of device frequency. figure 16-7: ssp block diagram (i 2 c mode) read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) scl shift clock msb lsb sda
picmicro mid-range mcu family ds31016a-page 16-16 1997 microchip technology inc. the ssp module has ?e registers for i 2 c operation. they are: ssp control register (sspcon) ssp status register (sspstat) serial receive/transmit buffer (sspbuf) ssp shift register (sspsr) - not directly accessible ssp address register (sspadd) the sspcon register allows control of the i 2 c operation. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: ? 2 c slave mode (7-bit address) ? 2 c slave mode (10-bit address) ? 2 c firmware controlled multi-master mode, 7-bit address (start and stop bit interrupts enabled) ? 2 c firmware controlled multi-master mode, 10-bit address (start and stop bit interrupts enabled) ? 2 c firmware controlled master mode, slave is idle before selecting any i 2 c mode, the scl and sda pins must be programmed to inputs by setting the appropriate tris bits. selecting an i 2 c mode, by setting the sspen bit, enables the scl and sda pins to be used as the clock and data lines in i 2 c mode. the sspstat register gives the status of the data transfer. this information includes detection of a start or stop bit, speci?s if the received byte was data or address, if the next byte is the completion of 10-bit address, and if this will be a read or write data transfer. the sspstat reg- ister is read only. the sspbuf is the register to which transfer data is written to or read from. the sspsr register shifts the data in or out of the device. in receive operations, the sspbuf and sspsr create a doubled buffered receiver. this allows reception of the next byte to begin before reading the last byte of received data. when the complete byte is received, it is transferred to the sspbuf reg- ister and the sspif ?g bit is set. if another complete byte is received before the sspbuf reg- ister is read, a receiver over?w has occurred and bit sspov (sspcon<6>) is set. the sspadd register holds the slave address. in 10-bit mode, the user needs to write the high byte of the address ( 1111 0 a9 a8 0 ). following the high byte address match, the low byte of the address needs to be loaded (a7:a0).
1997 microchip technology inc. ds31016a-page 16-17 section 16. bssp bssp 16 16.4.1 slave mode in slave mode, the scl and sda pins must be con?ured as inputs (tris bits set). the ssp module will override the input state with the output data when required (slave-transmitter). when an address is matched or the data transfer after an address match is received, the hard- ware automatically will generate the acknowledge (a ck ) pulse, and then load the sspbuf reg- ister with the received value currently in the sspsr register. there are certain conditions that will cause the ssp module not to give this a ck pulse. these are if either (or both): a) the buffer full bit, bf (sspstat<0>), was set before the transfer was received. b) the over?w bit, sspov (sspcon<6>), was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif and sspov bits are set. table 16-2 shows what happens when a data transfer byte is received, given the sta- tus of the bf and sspov bits. the shaded cells show the condition where user software did not properly clear the over?w condition. the bf ?g bit is cleared by reading the sspbuf register while the sspov bit is cleared through software. the scl clock input must have a minimum high and low time for proper operation. the high and low times of the i 2 c speci?ation as well as the requirement of the ssp module are given in parameter 100 and parameter 101 of the ?lectrical speci?ations section.
picmicro mid-range mcu family ds31016a-page 16-18 1997 microchip technology inc. 16.4.1.1 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register on the falling edge of the eight scl pulse. b) the buffer full bit, bf, is set on the falling edge of the eight scl pulse. c) an a ck pulse is generated. d) ssp interrupt ?g bit, sspif, is set (interrupt is generated if enabled) - on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the ?e most signi?ant bits (msbs) of the ?st address byte specify if this is a 10-bit address. the r/w bit (sspstat<2>) must specify a write, so the slave device will receive the second address byte. for a 10-bit address the ?st byte would equal 1111 0 a9 a8 0 ? where a9 and a8 are the two msbs of the address. the sequence of events for a 10-bit address is as follows, with steps 7- 9 for slave-transmitter: 1. receive ?st (high) byte of address (the sspif, bf, and ua (sspstat<1>) bits are set). 2. update the sspadd register with second (low) byte of address (clears the ua bit and releases the scl line). 3. read the sspbuf register (clears the bf bit) and clear the sspif ?g bit. 4. receive second (low) byte of address (the sspif, bf, and ua bits are set). 5. update the sspadd register with the ?st (high) byte of address. this will clear the ua bit and release the scl line. 6. read the sspbuf register (clears the bf bit) and clear the sspif ?g bit. 7. receive repeated start condition. 8. receive ?st (high) byte of address (the sspif and bf bits are set). 9. read the sspbuf register (clears the bf bit) and clear the sspif ?g bit. table 16-2: data transfer received byte actions note: following the restart condition (step 7) in 10-bit mode, the user only needs to match the ?st 7-bit address. the user does not update the sspadd for the second half of the address. status bits as data transfer is received sspsr ? sspbuf generate a ck pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 ye s ye s ye s 10 no no yes 11 no no yes 0 1 ye s no ye s note:shaded cells show the conditions where the user software did not properly clear the over?w con- dition
1997 microchip technology inc. ds31016a-page 16-19 section 16. bssp bssp 16 16.4.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte over?w condition exists, then no acknowledge (a ck ) pulse is given. an over?w condition is de?ed as either the bf bit (sspstat<0>) is set or the sspov bit (sspcon<6>) is set. an ssp interrupt is generated for each data transfer byte. the sspif ?g bit must be cleared in software, and the sspstat register is used to determine the status of the byte. figure 16-8: i 2 c waveforms for reception (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read a ck receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 a ck r/w =0 receiving address sspif bf (sspstat<0>) sspov (sspcon<6>) a ck a ck is not sent.
picmicro mid-range mcu family ds31016a-page 16-20 1997 microchip technology inc. 16.4.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the a ck pulse will be sent on the ninth bit, and the scl pin is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then the scl pin should be enabled by setting the ckp bit (sspcon<4>). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretching the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time ( figure 16-9 ). an ssp interrupt is generated for each data transfer byte. the sspif ?g bit must be cleared in software, and the sspstat register is used to determine the status of the byte transfer. the sspif ?g bit is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the a ck pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not a ck ), then the data transfer is complete. when the not a ck is latched by the slave, the slave logic is reset and the slave then monitors for another occurrence of the start bit. if the sda line was low (a ck ), the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then the scl pin should be enabled by setting the ckp bit. figure 16-9: i 2 c waveforms for transmission (7-bit address) 16.4.1.4 clock arbitration clock arbitration has the scl pin to inhibit the master device from sending the next clock pulse. the ssp module in i 2 c slave mode will hold the scl pin low when the cpu needs to respond to the ssp interrupt (sspif bit is set and the ckp bit is cleared). the data that needs to be trans- mitted will need to be written to the sspbuf register, and then the ckp bit will need to be set to allow the master to generate the required clocks. sda scl sspif bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 a ck d7 d6 d5 d4 d3 d2 d1 d0 a ck transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif
1997 microchip technology inc. ds31016a-page 16-21 section 16. bssp bssp 16 16.4.2 master mode (firmware) master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle with both the s and p bits clear. in master mode the scl and sda lines are manipulated by clearing the corresponding tris bit(s). the output level is always low, irrespective of the value(s) in port. so when transmitting data, a '1' data bit must have the tris bit set (input) and a '0' data bit must have the tris bit cleared (output). the same scenario is true for the scl line with the tris bit. the following events will cause the sspif interrupt flag bit to be set (ssp interrupt if enabled): start condition stop condition data transfer byte transmitted/received master mode of operation can be done with either the slave mode idle (sspm3:sspm0 = 1011 ) or with the slave active (sspm3:ssp0 = 1110 or 1111 ). when the slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. 16.4.3 multi-master mode (firmware) in multi-master mode, the interrupt generation on the detection of the start and stop condi- tions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat<4>) is set, or the bus is idle with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored to see if the signal level is the expected output level. this check only needs to be done when a high level is output. if a high level is expected and a low level is present, the device needs to release the sda and scl lines (set the tris bits). there are two stages where this arbitration can be lost, they are: address transfer data transfer when the slave logic is enabled, the slave continues to receive. if arbitration was lost during the address transfer stage, communication to the device may be in progress. if addressed an a ck pulse will be generated. if arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time.
picmicro mid-range mcu family ds31016a-page 16-22 1997 microchip technology inc. 16.4.4 sleep operation while in sleep mode, the i 2 c module can receive addresses or data, and when an address match or complete byte transfer occurs wake the processor from sleep (if the ssp interrupt is enabled). 16.4.5 effect of a reset a reset disables the ssp module and terminates the current transfer. table 16-3: registers associated with i 2 c operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets intcon gie peie t0ie inte rbie (2) t0if intf rbif (2) 0000 000x 0000 000u pir sspif (1) 00 pie sspie (1) 00 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 sspstat d/a p s r/w ua bf --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by ssp in i 2 c mode. note 1: the position of these bits is device dependent. 2: these bits can also be named gpie and gpif.
1997 microchip technology inc. ds31016a-page 16-23 section 16. bssp bssp 16 16.5 initialization example 16-2: spi master mode initialization 16.5.1 ssp module / basic ssp module compatibility when changing from the ssp module to the basic ssp module, the sspstat register contains two additional control bits. these bits are: smp, spi data input sample phase cke, spi clock edge select to be compatible with the spi of the basic ssp module, these bits must be appropriately con?- ured. if these bits are not at the states shown in table 16-4 , improper spi communication should be expected. if the ssp module uses a different con?uration then shown in table 16-4 , the basic ssp module can not be used to implement that mode. that mode may be implemented in software. table 16-4: new bit states for compatibility clrf status ; bank 0 clrf sspstat ; clear status bits movlw 0x31 ; set up spi port, master mode, clk/16, movwf sspcon ; data xmit on rising edge ; data sampled in middle bsf status, rp0 ; bank 1 bsf pie1, sspie ; enable ssp interrupt bcf status, rp0 ; bank 0 bsf intcon, gie ; enable, enabled interrupts movlw databyte ; data to be transmitted ; could move data from ram location movwf sspbuf ; start transmission basic ssp module ssp module ckp ckp cke smp 1 100 0 000
picmicro mid-range mcu family ds31016a-page 16-24 1997 microchip technology inc. 16.6 design tips question 1: using spi mode, i do not seem able to talk to an spi device. answer 1: ensure that you are using the correct spi mode for that device. this spi supports two of the four spi modes so ensure that the spi device that you are trying to interface to is compatible with one of these two modes. check the clock polarity and the clock phase. if the device is not compatible, switch to one of the microchip devices that has the ssp module, and that should solve this. question 2: using i 2 c mode, i do not seem able to make the master mode work. answer 2: this ssp module does not have master mode fully automated in hardware, see application note an578 for software which uses the ssp module to implement master mode. if you require a fully automated hardware implementation of i 2 c master mode, please refer to the microchip line card for devices that have the master ssp module. question 3: using i 2 c mode, i write data to the sspbuf register, but the data did not transmit. answer 3: ensure that you set the ckp bit to release the i 2 c clock. note: at the time of printing only the high-end family of devices (pic17cxxx) have devices with the master ssp module implemented.
1997 microchip technology inc. ds31016a-page 16-25 section 16. bssp bssp 16 16.7 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to this section are: title application note # use of the ssp module in the i 2 c multi-master environment. an578 using microchip 93 series serial eeproms with microcontroller spi ports an613 software implementation of i 2 c bus master an554 use of the ssp module in the multi-master environment an578 interfacing pic16c64/74 to microchip spi serial eeprom an647 interfacing a microchip pic16c92x to microchip spi serial eeprom an668
picmicro mid-range mcu family ds31016a-page 16-26 1997 microchip technology inc. 16.8 revision history revision a this is the initial revision of the basic ssp module description.
1997 microchip technology inc. preliminary ds31017a page 17-1 m mssp 17 section 17. master synchronous serial port (mssp) highlights this section of the manual contains the following major topics: 17.1 introduction ............................................................................................................... ...17-2 17.2 control register ........................................................................................................... 17-4 17.3 spi mode ................................................................................................................... ..17-9 17.4 ssp i 2 c operation .................................................................................................17-18 17.5 connection considerations for i 2 c bus .....................................................................17-56 17.6 initialization ............................................................................................................. ...17-57 17.7 design tips ................................................................................................................ 17-58 17.8 related application notes..........................................................................................17-59 17.9 revision history .........................................................................................................17 -60 note: at present no mid-range mcu devices are available with this module. devices are planned, but there is no schedule for availability. please refer to microchips web site or bbs for release of product briefs. you will be able to ?d out the details and the features for new devices. this module is available on microchips high end family (pic17cxxx). please refer to microchips web site, bbs, regional sales of?e, or factory repre- sentatives. i 2 c is a trademark of philips corporation.
picmicro mid-range mcu family ds31017a-page 17-2 preliminary 1997 microchip technology inc. 17.1 introduction the master synchronous serial port (mssp) module is a serial interface useful for communicat- ing with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the mssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) - full master mode - slave mode (with general address call) figure 17-1 shows a block diagram for the spi mode, while figure 17-2 , and figure 17-3 show the block diagrams for the two different i 2 c modes of operation. figure 17-1: spi mode block diagram read write internal data bus sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr tris bit 2 smp:cke sdi sdo ss sck spi is a trademark of motorola corporation. i 2 c is a trademark of philips corporation.
1997 microchip technology inc. preliminary ds31017a-page 17-3 section 17. mssp mssp 17 figure 17-2: i 2 c slave mode block diagram figure 17-3: i 2 c master mode block diagram read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus address match or set, reset s, p bits (sspstat reg) scl shift clock msb lsb sda general call detected read write sspsr reg match detect sspadd reg start and stop bit detect / generate sspbuf reg internal data bus address match or set/clear s bit clear/set p bit (sspstat reg) scl shift clock msb lsb sda baud rate generator 7 sspadd<6:0> and and set sspif general call detected
picmicro mid-range mcu family ds31017a-page 17-4 preliminary 1997 microchip technology inc. 17.2 control register register 17-1: sspstat: ssp status register r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a p s r/w ua bf bit 7 bit 0 bit 7 smp: sample bit spi master mode 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi sla v e mode smp must be cleared when spi is used in slave mode in i 2 c master or sla v e mode: 1= slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0= slew rate control enabled for high speed mode (400 khz) bit 6 cke : spi clock edge select ckp = 0 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck ckp = 1 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p : stop bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, sspen is cleared) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3 s : start bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, sspen is cleared) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not a ck bit. in i 2 c sla v e mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress. or?ng this bit with sen, rsen, pen, rcen, or acken will indicate if the ssp is in idle mode. bit 1 ua : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated
1997 microchip technology inc. preliminary ds31017a-page 17-5 section 17. mssp mssp 17 bit 0 bf : buffer full status bit receiv e (spi and i 2 c modes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty t r ansmit (i 2 c mode only) 1 = data transmit in progress (does not include the a ck and stop bits), sspbuf is full 0 = data transmit complete (does not include the a ck and stop bits), sspbuf is empty legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset register 17-1: sspstat: ssp status register (contd)
picmicro mid-range mcu family ds31017a-page 17-6 preliminary 1997 microchip technology inc. register 17-2: sspcon1: ssp control register1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol : write collision detect bit master mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision sla v e mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov : receive over?w indicator bit in spi mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of over?w, the data in sspsr is lost. over?w can only occur in slave mode. in slave mode, the user must read the sspbuf, even if only transmitting data, to avoid setting over- ?w. in master mode the over?w bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 0 = no over?w in i 2 c mode: 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a ?on? care in transmit mode. sspov must be cleared in software in either mode. (must be cleared in software) 0 = no over?w bit 5 sspen : synchronous serial port enable bit in both modes, when enabled, these pins must be properly con?ured as input or output. in spi mode: 1 = enables serial port and con?ures sck, sdo, sdi, and ss as the source of the serial port pins 0 = disables serial port and con?ures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and con?ures the sda and scl pins as the source of the serial port pins 0 = disables serial port and con?ures these pins as i/o port pins bit 4 ckp : clock polarity select bit in spi mode: 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c sla v e mode: sck release control 1 = enable clock 0 = holds clock low (clock stretch) (used to ensure data setup time) in i 2 c master mode unused in this mode
1997 microchip technology inc. preliminary ds31017a-page 17-7 section 17. mssp mssp 17 bit 3 - 0 sspm3:sspm0 : synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc / (4 * (sspadd+1) ) 1xx1 = reserved 1x1x = reserved legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset register 17-2: sspcon1: ssp control register1 (contd)
picmicro mid-range mcu family ds31017a-page 17-8 preliminary 1997 microchip technology inc. register 17-3: sspcon2: ssp control register2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 bit 7 gcen : general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspsr 0 = general call address disabled bit 6 ackstat : acknowledge status bit (in i 2 c master mode only) in master tr ansmit mode: 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt : acknowledge data bit (in i 2 c master mode only) in master receiv e mode: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. 1 = not acknowledge 0 = acknowledge bit 4 acken : acknowledge sequence enable bit (in i 2 c master mode only) in master receiv e mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit akdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled). bit 3 rcen : receive enable bit (in i 2 c master mode only) 1 = enables receive mode for i 2 c 0 = receive idle note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled). bit 2 pen : stop condition enable bit (in i 2 c master mode only) sck release control 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled). bit 1 rsen : repeated start condition enabled bit (in i 2 c master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle. note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled). bit 0 sen : start condition enabled bit (in i 2 c master mode only) 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled). legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
1997 microchip technology inc. preliminary ds31017a-page 17-9 section 17. mssp mssp 17 17.3 spi mode the spi mode allows 8-bits of data to be synchronously transmitted and received simulta- neously. all four modes of spi are supported. to accomplish communication, typically three pins are used: serial data out (sdo) serial data in (sdi) serial clock (sck) additionally a fourth pin may be used when in a slave mode of operation: slave select (ss ) 17.3.1 operation when initializing the spi, several options need to be speci?d. this is done by programming the appropriate control bits in the sspcon1 register (sspcon1<5:0>) and sspstat<7:6>. these control bits allow the following to be speci?d: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) data input sample phase (middle or end of data output time) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) figure 17-4 shows the block diagram of the ssp module, when in spi mode. figure 17-4: ssp block diagram (spi mode) read write internal data bus sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr tris bit 2 smp:cke sdi sdo ss sck
picmicro mid-range mcu family ds31017a-page 17-10 preliminary 1997 microchip technology inc. the ssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb ?st. the sspbuf holds the data that was written to the sspsr, until the received data is ready. once the 8-bits of data have been received, that byte is moved to the sspbuf register. then the buffer full detect bit, bf (sspstat<0>), and the interrupt ?g bit, sspif, are set. this double buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored, and the write collision detect bit, wcol (sspcon1<7>), will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the sspbuf register com- pleted successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit, bf (sspstat<0>), indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally the ssp interrupt is used to determine when the transmission/reception has completed. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 17-1 shows the loading of the sspbuf (sspsr) for data transmission. example 17-1: loading the sspbuf (sspsr) register the sspsr is not directly readable or writable, and can only be accessed by addressing the sspbuf register. additionally, the ssp status register (sspstat) indicates the various status conditions. 17.3.2 enabling spi i/o to enable the serial port, ssp enable bit, sspen (sspcon1<5>), must be set. to reset or recon?ure spi mode, clear the sspen bit, re-initialize the sspcon registers, and then set the sspen bit. this con?ures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed. that is: sdi is automatically controlled by the spi module sdo must have tris bit cleared sck (master mode) must have tris bit cleared sck (slave mode) must have tris bit set ?s must have tris bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. bcf status, rp1 ;specify bank1 bsf status, rp0 ; loop btfss sspstat, bf ;has data been received (transmit complete)? goto loop ;no bcf status, rp0 ;specify bank0 movf sspbuf, w ;w reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit
1997 microchip technology inc. preliminary ds31017a-page 17-11 section 17. mssp mssp 17 17.3.3 typical connection figure 17-5 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge of the clock. both processors should be programmed to same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: master sends data slave sends dummy data master sends data slave sends data master sends dummy data slave sends data figure 17-5: spi master/slave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm3:sspm0 = 00xx b serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm3:sspm0 = 010x b serial clock
picmicro mid-range mcu family ds31017a-page 17-12 preliminary 1997 microchip technology inc. 17.3.4 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 17-5 ) is to broadcast data by the software pro- tocol. in master mode the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be disabled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver appli- cations as a ?ine activity monitor mode. the clock polarity is selected by appropriately programming the ckp bit (sspcon1<4>). this then would give waveforms for spi communication as shown in figure 17-6 , figure 17-8 , and figure 17-9 where the msb is transmitted ?st. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: ? osc /4 (or t cy ) ? osc /16 (or 4 ?t cy ) ? osc /64 (or 16 ?t cy ) timer2 output/2 this allows a maximum data rate (at 20 mhz) of 8.25 mbps. figure 17-6 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown.
1997 microchip technology inc. preliminary ds31017a-page 17-13 section 17. mssp mssp 17 figure 17-6: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit0 sdi sspif (smp = 1) (smp = 0) (smp = 1) cke = 1) cke = 0) cke = 1) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (cke = 0) (cke = 1) next q4 cycle after q2
picmicro mid-range mcu family ds31017a-page 17-14 preliminary 1997 microchip technology inc. 17.3.5 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the sspif interrupt ?g bit is set. while in slave mode the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as speci?d in the electrical spec- i?ations. while in sleep mode, the slave can transmit/receive data. when a byte is receive the device will wake-up from sleep. 17.3.6 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon1<3:0> = 04h). the pin must not be driven low for the ss pin to function as an input. the data latch must be high. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte, and becomes a ?ating output. external pull-up/ pull-down resistors may be desirable, depending on the application. when the spi module resets, the bit counter is forced to 0. this can be done by either by forcing the ss pin to a high level or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver the sdo pin can be con?ured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus con?ct. note 1: when the spi is in slave mode with ss pin control enabled, (sspcon<3:0> = 0100 ) the spi module will reset if the ss pin is set to v dd . note 2: if the spi is used in slave mode with cke is set, then the ss pin control must be enabled.
1997 microchip technology inc. preliminary ds31017a-page 17-15 section 17. mssp mssp 17 figure 17-7: slave synchronization waveform figure 17-8: spi mode waveform (slave mode with cke = 0) sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 sdo bit7 bit6 bit7 sspif interrupt (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss flag bit0 bit7 bit0 next q4 cycle after q2 sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif interrupt (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss flag optional next q4 cycle after q2
picmicro mid-range mcu family ds31017a-page 17-16 preliminary 1997 microchip technology inc. figure 17-9: spi mode waveform (slave mode with cke = 1) sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif interrupt (smp = 0) cke = 1) cke = 1) (smp = 0) write to sspbuf sspsr to sspbuf ss flag not optional next q4 cycle after q2
1997 microchip technology inc. preliminary ds31017a-page 17-17 section 17. mssp mssp 17 17.3.7 sleep operation in master mode all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from sleep. after the device returns to normal mode, the module will continue to transmit/receive data. in slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode, and data to be shifted into the spi transmit/receive shift register. when all 8-bits have been received, the mssp interrupt ?g bit will be set and if enabled will wake the device from sleep. 17.3.8 effects of a reset a reset disables the mssp module and terminates the current transfer. table 17-1: registers associated with spi operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie t0ie inte rbie (2) t0if intf rbif (2) 0000 0000 0000 0000 pir sspif (1) 00 pie sspie (1) 00 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the ssp in spi mode. note 1: the position of this bit is device dependent. 2: these bits may also be named gpie and gpif.
picmicro mid-range mcu family ds31017a-page 17-18 preliminary 1997 microchip technology inc. 17.4 ssp i 2 c operation the mssp module in i 2 c mode fully implements all master and slave functions (including gen- eral call support) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master function). the ssp module implements the standard mode speci?ations as well as 7-bit and 10-bit addressing. appendix a gives an overview of the i 2 c bus speci?ation. a ?litch filter is on the scl and sda pins when the pin is an input. this ?ter operates in both the 100 khz and 400 khz modes. in the 100 khz mode, when these pins are an output, there is a slew rate control of the pin that is independent of device frequency. figure 17-10: i 2 c slave mode block diagram figure 17-11: i 2 c master mode block diagram read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus address match set, reset s, p bits (sspstat reg) scl shift clock msb lsb sda read write sspsr reg match detect sspadd reg start and stop bit detect / generate sspbuf reg internal data bus address match set/clear s bit clear/set p bit (sspstat reg) scl shift clock msb lsb sda baud rate generator 7 sspadd<6:0> and and set sspif
1997 microchip technology inc. preliminary ds31017a-page 17-19 section 17. mssp mssp 17 two pins are used for data transfer. these are the scl pin, which is the clock, and the sda pin, which is the data. pins that are on the port are automatically con?ured when the i 2 c mode is enabled. the ssp module functions are enabled by setting ssp enable bit, sspen (sspcon1<5>). the ssp module has six registers for i 2 c operation. they are the: ssp control register1 (sspcon1) ssp control register2 (sspcon2) ssp status register (sspstat) serial receive/transmit buffer (sspbuf) ssp shift register (sspsr) - not directly accessible ssp address register (sspadd) the sspcon1 register allows control of the i 2 c operation. four mode selection bits (sspcon1<3:0>) allow one of the following i 2 c modes to be selected: ? 2 c slave mode (7-bit address) ? 2 c slave mode (10-bit address) ? 2 c master mode, clock = osc/4 (sspadd +1) before selecting any i 2 c mode, the scl and sda pins must be programmed to inputs by setting the appropriate tris bits. selecting an i 2 c mode, by setting the sspen bit, enables the scl and sda pins to be used as the clock and data lines in i 2 c mode. the sspstat register gives the status of the data transfer. this information includes detection of a start or stop bit, speci?s if the received byte was data or address, if the next byte is the completion of 10-bit address, and if this will be a read or write data transfer. the sspbuf is the register to which transfer data is written to or read from. the sspsr register shifts the data in or out of the device. in receive operations, the sspbuf and sspsr create a double buffered receiver. this allows reception of the next byte to begin before reading the last byte of received data. when the complete byte is received, it is transferred to the sspbuf reg- ister and ?g bit sspif is set. if another complete byte is received before the sspbuf register is read, a receiver over?w has occurred and the sspov bit (sspcon1<6>) is set and the byte in the sspsr is lost. the sspadd register holds the slave address. in 10-bit mode, the user needs to write the high byte of the address ( 1111 0 a9 a8 0 ). following the high byte address match, the low byte of the address needs to be loaded (a7:a0).
picmicro mid-range mcu family ds31017a-page 17-20 preliminary 1997 microchip technology inc. 17.4.1 slave mode in slave mode, the scl and sda pins must be con?ured as inputs. the ssp module will over- ride the input state with the output data when required (slave-transmitter). when an address is matched or the data transfer after an address match is received, the hard- ware automatically will generate the acknowledge (a ck ) pulse, and then load the sspbuf reg- ister with the received value currently in the sspsr register. there are certain conditions that will cause the ssp module not to give this a ck pulse. these are if either (or both): a) the buffer full bit, bf (sspstat<0>), was set before the transfer was received. b) the over?w bit, sspov (sspcon1<6>), was set before the transfer was received. if the bf bit is set, the sspsr register value is not loaded into the sspbuf, but the sspif and sspov bits are set. table 17-2 shows what happens when a data transfer byte is received, given the status of the bf and sspov bits. the shaded cells show the condition where user software did not properly clear the over?w condition. the bf ?g bit is cleared by reading the sspbuf register while bit sspov is cleared through software. the scl clock input must have a minimum high and low time for proper operation. the high and low times of the i 2 c speci?ation as well as the requirement of the ssp module is shown in timing parameters 100 and 101 of the ?lectrical speci?ations section.
1997 microchip technology inc. preliminary ds31017a-page 17-21 section 17. mssp mssp 17 17.4.1.1 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register on the falling edge of the eighth scl pulse. b) the buffer full bit, bf, is set on the falling edge of the eighth scl pulse. c) an a ck pulse is generated. d) ssp interrupt ?g bit, sspif, is set (interrupt is generated if enabled) - on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the ?e most sig- ni?ant bits (msbs) of the ?st address byte specify if this is a 10-bit address. the r/w bit (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address the ?st byte would equal 1111 0 a9 a8 0 ? where a9 and a8 are the two msbs of the address. the sequence of events for a 10-bit address is as follows, with steps 7- 9 for slave-transmitter: 1. receive ?st (high) byte of address (the sspif, bf, and ua (sspstat<1>) bits are set). 2. update the sspadd register with second (low) byte of address (clears the ua bit and releases the scl line). 3. read the sspbuf register (clears the bf bit) and clear ?g bit sspif. 4. receive second (low) byte of address (the sspif, bf, and ua bits are set). 5. update the sspadd register with the ?st (high) byte of address. this will clear the ua bit and release the scl line. 6. read the sspbuf register (clears the bf bit) and clear the sspif ?g bit. 7. receive repeated start condition. 8. receive ?st (high) byte of address (the sspif and bf bits are set). 9. read the sspbuf register (clears the bf bit) and clear the sspif ?g bit. table 17-2: data transfer received byte actions note: following the repeated start condition (step 7) in 10-bit mode, the user only needs to match the ?st 7-bit address. the user does not update the sspadd for the sec- ond half of the address. status bits as data transfer is received sspsr ? sspbuf generate a ck pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 ye s ye s ye s 10 no no yes 11 no no yes 0 1 ye s no ye s note: shaded cells show the conditions where the user software did not properly clear the over?w condition
picmicro mid-range mcu family ds31017a-page 17-22 preliminary 1997 microchip technology inc. 17.4.1.2 slave reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte over?w condition exists, then no acknowledge (a ck ) pulse is given. an over?w condition is de?ed as either the bf bit (sspstat<0>) is set or the sspov bit (sspcon1<6>) is set. an ssp interrupt is generated for each data transfer byte. the sspif ?g bit must be cleared in software. the sspstat register is used to determine the status of the received byte. note: the sspbuf will be loaded if the sspov bit is set and the bf ?g bit is cleared. if a read of the sspbuf was performed, but the user did not clear the state of the sspov bit before the next receive occurred. the a ck is not sent and the sspbuf is updated.
1997 microchip technology inc. preliminary ds31017a-page 17-23 section 17. mssp mssp 17 17.4.1.3 slave transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the a ck pulse will be sent on the ninth bit, and the scl pin is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then the scl pin should be enabled by setting the ckp bit (sspcon1<4>). the master should monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretching the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time ( figure 17-13 ). an ssp interrupt is generated for each data transfer byte. the sspif ?g bit must be cleared in software, and the sspstat register is used to determine the status of the byte transfer. the sspif ?g bit is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the a ck pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not a ck ), then the data transfer is complete. when the not a ck is latched by the slave, the slave logic is reset and the slave then monitors for another occurrence of the start bit. if the sda line was low (a ck ), the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then the scl pin should be enabled by setting the ckp bit. figure 17-12: i 2 c slave mode waveforms for reception (7-bit address) figure 17-13: i 2 c slave mode waveforms for transmission (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read a ck receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 a ck r/w =0 receiving address sspif bf (sspstat<0>) sspov (sspcon1<6>) a ck a ck is not sent. sda scl sspif bf (sspstat<0>) ckp (sspcon1<4>) a7 a6 a5 a4 a3 a2 a1 a ck d7 d6 d5 d4 d3 d2 d1 d0 a ck transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written-to before the ckp bit can be set) r/w = 0
picmicro mid-range mcu family ds31017a-page 17-24 preliminary 1997 microchip technology inc. figure 17-14: i 2 c slave mode waveform (transmission 10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 1 1 1 1 0 a8 r/w =1 a ck a ck r/w = 0 a ck receive first byte of address cleared in software master sends nack a9 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated. ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated. sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf ?g receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 a ck d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf ?g sr cleared in software write of sspbuf initiates transmit cleared in software transmit is complete ckp has to be set for clock to be released bus master terminates transfer
1997 microchip technology inc. preliminary ds31017a-page 17-25 section 17. mssp mssp 17 figure 17-15: i 2 c slave mode waveform (reception 10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 d7d6d5d4d3 d1d0 receive data byte a ck r/w = 0 a ck receive first byte of address cleared in software bus master terminates transfer d2 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated. ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf ?g a ck r/w = 1 cleared in software dummy read of sspbuf to clear bf ?g read of sspbuf clears bf ?g cleared by hardware when sspadd is updated.
picmicro mid-range mcu family ds31017a-page 17-26 preliminary 1997 microchip technology inc. 17.4.2 general call address support the addressing procedure for the i 2 c bus is such that the ?st byte after the start condition usually determines which device will be the slave addressed by the master. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for speci? purposes by the i 2 c pro- tocol. it consists of all 0s with r/w = 0. the general call address is recognized when the general call enable bit (gcen) is enabled (sspcon2<7> set). following a start-bit detect, 8-bits are shifted into sspsr and the address is compared against sspadd, and is also compared to the general call address, ?ed in hard- ware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf ?g bit is set (eight bit), and on the falling edge of the ninth bit (a ck bit) the sspif interrupt ?g bit is set. when the interrupt is serviced. the source for the interrupt can be checked by reading the con- tents of the sspbuf to determine if the address was device speci? or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match, and the ua bit is set (sspstat<1>). if the general call address is sampled when the gcen bit is set while the slave is con?ured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set, and the slave will begin receiving data after the acknowledge ( figure 17-16 ). figure 17-16: slave mode general call address sequence (7 or 10-bit address mode) sda scl s sspif bf (sspstat<0>) sspov (sspcon1<6>) cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address gcen (sspcon2<7>) receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack, set interrupt '0' '1'
1997 microchip technology inc. preliminary ds31017a-page 17-27 section 17. mssp mssp 17 17.4.3 sleep operation while in sleep mode, the i 2 c module can receive addresses or data, and when an address match or complete byte transfer occurs wake the processor from sleep (if the mssp interrupt is enabled). 17.4.4 effect of a reset a reset disables the mssp module and terminates the current transfer. table 17-3: registers associated with i 2 c operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie t0ie inte rbie (2) t0if intf rbif (2) 0000 0000 0000 0000 pir sspif, bclif (1) 0, 0 0, 0 pie sspie, bclif (1) 0, 0 0, 0 sspadd synchronous serial port (i 2 c mode) address register (slave mode)/baud rate generator (master mode) 0000 0000 0000 0000 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the ssp in i 2 c mode. note 1: the position of these bits is device dependent. 2: these bits may also be named gpie and gpif.
picmicro mid-range mcu family ds31017a-page 17-28 preliminary 1997 microchip technology inc. 17.4.5 master mode master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle with both the s and p bits clear. in master mode the scl and sda lines are manipulated by the ssp hardware. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): start condition stop condition data transfer byte transmitted/received acknowledge transmit repeated start figure 17-17: ssp block diagram (i 2 c master mode) read write sspsr start bit, stop bit, start bit detect sspbuf internal data bus set/reset, s, p, wcol (sspstat) shift clock msb lsb sda acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif reset acks tat, pen (sspcon2) rate generator sspm3:sspm0
1997 microchip technology inc. preliminary ds31017a-page 17-29 section 17. mssp mssp 17 17.4.6 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop condi- tions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat<4>) is set, or the bus is idle with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored, for arbitration, to see if the signal level is the expected output level. this check is performed in hardware, with the result placed in the bclif bit. the states where arbitration can be lost are: address transfer data transfer a start condition a repeated start condition an acknowledge condition 17.4.7 i 2 c master mode support master mode is enabled by setting and clearing the appropriate sspm bits in sspcon1 and by setting the sspen bit. once master mode is enabled, the user has six options. 1. assert a start condition on sda and scl. 2. assert a repeated start condition on sda and scl. 3. write to the sspbuf register initiating transmission of data/address. 4. generate a stop condition on sda and scl. 5. con?ure the i 2 c port to receive data. 6. generate an acknowledge condition at the end of a received byte of data. note: the ssp module when con?ured in i 2 c master mode does not allow queueing of events. for instance: the user is not allowed to initiate a start condition, and imme- diately write the sspbuf register to imitate transmission before the start condi- tion is complete. in this case the sspbuf will not be written to, and the wcol bit will be set, indicating that a write to the sspbuf did not occur.
picmicro mid-range mcu family ds31017a-page 17-30 preliminary 1997 microchip technology inc. 17.4.7.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode serial data is output through sda, while scl outputs the serial clock. the ?st byte transmitted contains the slave address of the receiving device, (7 bits) and the read/write (r/w ) bit. in this case the r/w bit will be logic '0'. serial data is transmitted 8 bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop condi- tions are output to indicate the beginning and the end of a serial transfer. in master receive mode the ?st byte transmitted contains the slave address of the transmitting device (7 bits) and the r/w bit. in this case the r/w bit will be logic ?? thus the ?st byte trans- mitted is a 7-bit slave address followed by a '1' to indicate receive bit. serial data is received via sda while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the begin- ning and end of transmission. the baud rate generator used for spi mode operation is used to set the scl clock frequency for either 100 khz, 400 khz, or 1 mhz i 2 c operation. the baud rate generator reload value is con- tained in the lower 7 bits of the sspadd register. the baud rate generator will automatically begin counting on a write to the sspbuf. once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ack) the internal clock will automatically stop counting and the scl pin will remain in its last state. a typical transmit sequence would go as follows: a) the user generates a start condition by setting the start enable bit, sen (sspcon2<0>). b) sspif is set. the ssp module will wait the required start time before any other operation takes place. c) the user loads the sspbuf with the address to transmit. d) address is shifted out the sda pin until all 8 bits are transmitted. e) the ssp module shifts in the ack bit from the slave device, and writes its value into the sspcon2 register (sspcon2<6>). f) the ssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. g) the user loads the sspbuf with eight bits of data. h) data is shifted out the sda pin until all 8 bits are transmitted. i) the ssp module shifts in the ack bit from the slave device, and writes its value into the sspcon2 register (sspcon2<6>). j) the ssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. k) the user generates a stop condition by setting the stop enable bit, pen (sspcon2<2>). l) interrupt is generated once the stop condition is complete.
1997 microchip technology inc. preliminary ds31017a-page 17-31 section 17. mssp mssp 17 17.4.8 baud rate generator in i 2 c master mode, the reload value for the brg is located in the lower 7 bits of the sspadd register ( figure 17-18 ). when the brg is loaded with this value, the brg counts down to 0 and stops until another reload has taken place. in i 2 c master mode, the brg is reloaded automati- cally. if clock arbitration is taking place for instance, the brg will be reloaded when the scl pin is sampled high ( figure 17-19 ). figure 17-18: baud rate generator block diagram figure 17-19: baud rate generator timing with clock arbitration sspm3:sspm0 brg down counter clkout fosc/4 sspadd<6:0> sspm3:sspm0 scl reload control reload sda scl scl de-asserted but slave holds dx-1 dx brg scl is sampled high, reload takes place, and brg starts its count. 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg counts down brg counts down brg counts down
picmicro mid-range mcu family ds31017a-page 17-32 preliminary 1997 microchip technology inc. 17.4.9 i 2 c master mode start condition timing to initiate a start condition the user sets the start condition enable bit, sen (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate generator is re-loaded with the contents of sspadd<6:0>, and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition, and causes the s bit (sspstat<3>) to be set. fol- lowing this, the baud rate generator is reloaded with the contents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ) the sen bit (sspcon2<0>) will be automatically cleared by hardware, the baud rate generator is suspended leaving the sda line held low, and the start condition is complete. 17.4.9.1 wcol status flag if the user writes the sspbuf when an start sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn? occur). figure 17-20: first start bit timing note: if at the beginning of start condition the sda and scl pins are already sampled low, or if during the start condition the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag,bclif, is set, the start condition is aborted, and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1, at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here. set s bit (sspstat<3>) and sets sspif bit
1997 microchip technology inc. preliminary ds31017a-page 17-33 section 17. mssp mssp 17 figure 17-21: start condition flowchart idle mode sen (sspcon2<0> = 1) bus collision detected, set bclif, sda = 1? load brg with ye s brg rollover? force sda = 0, load brg with sspadd<6:0>, no ye s force scl = 0, clear sen. set s bit sspadd<6:0> scl = 1? sda = 0? no ye s brg rollover? no clear sen start condition done, no ye s reset brg scl= 0? no ye s scl = 0? no ye s reset brg release scl, sspen = 1, sspcon1<3:0> = 1000 set sspif
picmicro mid-range mcu family ds31017a-page 17-34 preliminary 1997 microchip technology inc. 17.4.10 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2<1>) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded with the contents of sspadd<5:0>, and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be de-asserted (brought high). when scl is sampled high the baud rate generator is re-loaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0) for one t brg while scl is high. following this, the rsen bit (sspcon2<1>) will be automati- cally cleared, and the baud rate generator is not reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed-out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode, or the default ?st address in 10-bit mode. after the ?st eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). note 1: if rsen is programmed while any other event is in progress, it will not take effect. note 2: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low to high. ? scl goes low before sda is asserted low. this may indicates that another master is attempting to transmit a data ??
1997 microchip technology inc. preliminary ds31017a-page 17-35 section 17. mssp mssp 17 17.4.10.1 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn? occur). figure 17-22: repeat start condition waveform note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here. falling edge of ninth clock end of xmit at completion of start bit, hardware clear rsen bit 1st bit set s (sspstat<3>) t brg t brg sda = 1, sda = 1, scl(no change) scl = 1 occurs here. t brg t brg t brg and set sspif
picmicro mid-range mcu family ds31017a-page 17-36 preliminary 1997 microchip technology inc. figure 17-23: repeated start condition flowchart (part 1 of 2) idle mode, sspen = 1, force scl = 0 scl = 0? release sda, load brg with scl = 1? no ye s no ye s brg no ye s release scl sspcon1<3:0> = 1000 rollover? sspadd<6:0> load brg with sspadd<6:0> (clock arbitration) a b c sda = 1? no ye s start rsen = 1 bus collision, set bclif, release sda, clear rsen
1997 microchip technology inc. preliminary ds31017a-page 17-37 section 17. mssp mssp 17 figure 17-24: repeated start condition flowchart (part 2 of 2) force sda = 0, load brg with sspadd<6:0> ye s repeated start clear rsen, ye s brg rollover? brg rollover? ye s sda = 0? no scl = 1? no b set s c a no no ye s force scl = 0, reset brg set sspif. scl = '0'? reset brg no ye s condition done,
picmicro mid-range mcu family ds31017a-page 17-38 preliminary 1997 microchip technology inc. 17.4.11 i 2 c master mode transmission transmission of a data byte, a 7-bit address, or the either half of a 10-bit address is accomplished by simply writing a value to sspbuf register. this action will set the buffer full ?g bit, bf, and allow the baud rate generator to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time speci?ation parameters 106 ). scl is held low for one baud rate generator roll over count (t brg ). data should be valid before scl is released high (see data setup time spec- i?ation parameters 107 ). when the scl pin is released high, it is held that way for t brg , the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf ?g is cleared and the master releases sda allowing the slave device being addressed to respond with an a ck bit during the ninth bit time, if an address match occurs or if data was received prop- erly. the status of a ck is written into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, acks tat, i s cleared. if not, the bit is set. after the ninth clock the sspif bit is set, and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf leaving scl low and sda unchanged ( figure 17-26 ). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock the master will de-assert the sda pin allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock the master will sample the sda pin to see if the address was rec- ognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspcon2<6>). following the falling edge of the ninth clock transmission of the address, the sspif is set, the bf ?g is cleared, and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to ?at. 17.4.11.1 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 17.4.11.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e. sspsr is still shifting out a data byte), then wcol is set and the contents of the buffer are unchanged (the write doesn? occur). wcol must be cleared in software. 17.4.11.3 ackstat status flag in transmit mode, the ackstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (a ck = 0), and is set when the slave does not acknowledge (a ck = 1). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data.
1997 microchip technology inc. preliminary ds31017a-page 17-39 section 17. mssp mssp 17 figure 17-25: master transmit flowchart idle mode num_clocks = 0, release sda so slave can drive ack, num_clocks load brg with sda = current data bit ye s brg rollover? no brg no ye s force scl = 0 = 8? ye s no ye s brg rollover? no force scl = 1, stop brg scl = 1? load brg with count high time rollover? no read sda and place into ackstat bit (sspcon2<6>) force scl = 0, scl = 1? sda = data bit? no ye s ye s rollover? no ye s stop brg, force scl = 1 (clock arbitration) (clock arbitration) num_clocks = num_clocks + 1 bus collision detected set bclif, hold prescale off, ye s no bf = 1 force bf = 0 sspadd<6:0>, start brg count, load brg with sspadd<6:0>, start brg count sspadd<6:0>, load brg with count scl high time sspadd<6:0>, sda = data bit? ye s no clear xmit enable scl = 0? no ye s reset brg write sspbuf set sspif
picmicro mid-range mcu family ds31017a-page 17-40 preliminary 1997 microchip technology inc. figure 17-26: i 2 c master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 a ck = 0 d7d6d5d4d3d2d1d0 a ck transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from ssp interrupt after start condition sen cleared by hardware. s sspbuf written with 7 bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared in software sspbuf written pen cleared in software r/w
1997 microchip technology inc. preliminary ds31017a-page 17-41 section 17. mssp mssp 17 17.4.12 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting, and on each rollover, the state of the scl pin changes (high to low/low to high), and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable ?g is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf ?g bit is set, the sspif ?g bit is set, and the baud rate generator is sus- pended from counting, holding scl low. the ssp is now in idle state, awaiting the next com- mand. when the buffer is read by the cpu, the bf ?g bit is automatically cleared. the user can then send an acknowledge bit at the end of reception, by setting the acknowledge sequence enable bit, acken (sspcon2<4>). 17.4.12.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 17.4.12.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspsr, and the bf ?g bit is already set from a previous reception. 17.4.12.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e. sspsr is still shifting in a data byte), then the wcol bit is set and the contents of the buffer are unchanged (the write doesn? occur). note: the ssp module must be in an idle state before the rcen bit is set, or the rcen bit will be disregarded.
picmicro mid-range mcu family ds31017a-page 17-42 preliminary 1997 microchip technology inc. figure 17-27: master receiver flowchart idle mode num_clocks = 0, release sda force scl=0, ye s no brg rollover? release scl ye s no scl = 1? load brg with ye s no brg rollover? (clock arbitration) load brg w/ start count sspadd<6:0>, start count. sample sda, shift data into sspsr num_clocks = num_clocks + 1 ye s num_clocks = 8? no force scl = 0, set sspif, set bf. move contents of sspsr into sspbuf, clear rcen. rcen = 1 sspadd<6:0>, scl = 0? ye s no
1997 microchip technology inc. preliminary ds31017a-page 17-43 section 17. mssp mssp 17 figure 17-28: i 2 c master mode waveform (reception 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer a ck receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 a ck r/w = 1 transmit address to slave sspif bf a ck is not sent write to sspcon2<0> (sen = 1) write to sspbuf occurs here ack from slave master con?ured as a receiver by programming sspcon2<3>, (rcen = 1) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0, scl = 1 while cpu (sspstat<0>) a ck last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken start acknowledge sequence sspov is set because sspbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 start next receive write to sspcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared in software sda = ackdt = 0
picmicro mid-range mcu family ds31017a-page 17-44 preliminary 1997 microchip technology inc. 17.4.13 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowl- edge data bit is presented on the sda pin. if the user wishes to generate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ), and the scl pin is de-asserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off, and the ssp module then goes into idle mode ( figure 17-29 ). 17.4.13.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn? occur). figure 17-29: acknowledge sequence waveform note: t brg = one baud rate generator period. sda scl set sspif at the end acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg of receive a ck 8 acken = 1, ackdt = 0 d0 9 sspif software set sspif at the end of acknowledge sequence cleared in software
1997 microchip technology inc. preliminary ds31017a-page 17-45 section 17. mssp mssp 17 figure 17-30: acknowledge flowchart idle mode force scl = 0 ye s no scl = 0? drive ackdt bit ye s no brg rollover? (sspcon2<5>) onto sda pin, load brg with sspadd<6:0>, start count. force scl = 1 ye s no scl = 1? no ackdt = 1? load brg with no brg rollover? sspadd <6:0>, start count. no sda = 1? bus collision detected, set bclif, ye s force scl = 0, (clock arbitration) clear acken no scl = 0? reset brg clear acken set acken release scl, ye s ye s ye s set sspif
picmicro mid-range mcu family ds31017a-page 17-46 preliminary 1997 microchip technology inc. 17.4.14 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspcon2<2>). at the end of a receive/transmit the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sampled low, the baud rate generator is reloaded and counts down to 0. when the baud rate generator times out, the scl pin will be brought high, and one t brg (baud rate generator rollover count) later, the sda pin will be de-asserted. when the sda pin is sampled high while scl is high the p bit (sspstat<4>) is set. a t brg later, the pen bit is cleared and the sspif bit is set ( figure 17-31 ). whenever the ?mware decides to take control of the bus, it will ?st determine if the bus is busy by checking the s and p bits in the sspstat register. if the bus is busy, then the cpu can be interrupted (noti?d) when a stop bit is detected (i.e. bus is free). 17.4.14.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write doesn? occur). figure 17-31: stop condition receive or transmit mode scl sda sda asserted low before rising edge of clock write to sspcon2 set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set t brg to setup stop condition. a ck p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set
1997 microchip technology inc. preliminary ds31017a-page 17-47 section 17. mssp mssp 17 figure 17-32: stop condition flowchart idle mode, sspen = 1, force sda = 0 scl doesn? change sda = 0? de-assert scl, scl = 1 scl = 1? no ye s start brg no ye s brg sda going from 0 to 1 while scl = 1, no ye s set sspif, release sda, start brg stop condition done sspcon1<3:0> = 1000 rollover? no brg rollover? ye s p bit set? no ye s bus collision detected, set bclif, clear pen start brg no ye s brg rollover? (clock arbitration) pen = 1 pen cleared
picmicro mid-range mcu family ds31017a-page 17-48 preliminary 1997 microchip technology inc. 17.4.15 clock arbitration clock arbitration occurs when the master, during any receive, transmit, or repeated start/stop condition de-asserts the scl pin (scl allowed to ?at high). when the scl pin is allowed to ?at high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device ( figure 17-33 ). figure 17-33: clock arbitration timing in master transmit mode 17.4.16 sleep operation while in sleep mode, the i 2 c module can receive addresses or data, and when an address match or complete byte transfer occurs wake the processor from sleep (if the mssp interrupt is enabled). 17.4.17 effect of a reset a reset disables the mssp module and terminates the current transfer. scl sda brg over?w, release scl, if scl = 1 load brg with sspadd<6:0>, and start count brg over?w occurs, release scl, slave device holds scl low. scl = 1 brg starts counting clock high interval. scl line sampled once every machine cycle (t osc 4). hold off brg until scl is sampled high. t brg t brg t brg to measure high time interval
1997 microchip technology inc. preliminary ds31017a-page 17-49 section 17. mssp mssp 17 17.4.18 multi -master communication, bus collision, and bus arbitration multi-master mode support is achieved by bus arbitration. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a '1' on sda by letting sda ?at high and another master asserts a '0'. when the scl pin ?ats high, data should be stable. if the expected data on sda is a '1' and the data sampled on the sda pin = '0', then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif and reset the i 2 c port to its idle state. ( figure 17-34 ). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf ?g is cleared, the sda and scl lines are de-asserted, and the sspbuf can be written to. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop, or acknowledge condition was in progress when the bus col- lision occurred, the condition is aborted, the sda and scl lines are de-asserted, and the respec- tive control bits in the sspcon2 register are cleared. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by assert- ing a start condition. the master will continue to monitor the sda and scl pins, and if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the ?st data bit, regardless of where the transmitter left off when bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the determination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register, or the bus is idle and the s and p bits are cleared. figure 17-34: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high data doesn? match what is driven bus collision has occurred. set bus collision interrupt (bclif). by the master. by master data changes while scl = 0
picmicro mid-range mcu family ds31017a-page 17-50 preliminary 1997 microchip technology inc. 17.4.18.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition ( figure 17-35 ). b) scl is sampled low before sda is asserted low ( figure 17-36 ). during a start condition both the sda and the scl pins are monitored. if: the sda pin is already low or the scl pin is already low, then: the start condition is aborted, and the bclif ?g is set, and the ssp module is reset to its idle state ( figure 17-35 ). the start condition begins with the sda and scl pins de-asserted. when the sda pin is sam- pled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early ( figure 17-37 ). if however a '1' is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0, and during this time, if the scl pins is sampled as '0', a bus collision does not occur. at the end of the brg count the scl pin is asserted low. note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision because the two masters must be allowed to arbitrate the ?st address fol- lowing the start condition, and if the address is the same, arbitration must be allowed to continue into the data portion, repeated start, or stop conditions.
1997 microchip technology inc. preliminary ds31017a-page 17-51 section 17. mssp mssp 17 figure 17-35: bus collision during start condition (sda only) figure 17-36: bus collision during start condition (scl = 0) sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1, scl=1 sda = 0, scl = 1 bclif s sspif sda = 0, scl = 1 sspif and bclif are cleared in software. sspif and bclif are cleared in software. . set bclif, set bclif. start condition. sda scl sen bus collision occurs, set bclif. scl = 0 before sda = 0, set sen, enable start sequence if sda = 1, scl = 1 t brg t brg sda = 0, scl = 1 bclif s sspif interrupts cleared in software. bus collision occurs, set bclif. scl = 0 before brg time out, '0' '0' '0' '0'
picmicro mid-range mcu family ds31017a-page 17-52 preliminary 1997 microchip technology inc. figure 17-37: brg reset due to sda arbitration during start condition sda scl sen set s set sen, enable start sequence if sda = 1, scl = 1 less than t brg t brg sda = 0, scl = 1 bclif s sspif s interrupts cleared in software. set sspif sda = 0, scl = 1 sda pulled low by other master. reset brg and assert sda scl pulled low after brg timeout set sspif
1997 microchip technology inc. preliminary ds31017a-page 17-53 section 17. mssp mssp 17 17.4.18.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data ?? when the user de-asserts sda and the pin is allowed to ?at high, the brg is loaded with sspadd<6:0>, and counts down to zero. the scl pin is then de-asserted, and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e. another master, figure 17-38 , is attempting to transmit a data ??. if, however, sda is sampled high then the brg is reloaded and begins counting. if sda goes from high to low before the brg times out, no bus collision occurs, because no two masters can assert sda at exactly the same time. if, however, scl goes from high to low before the brg times out and sda has not already been asserted, then a bus collision occurs. in this case, another master is attempting to transmit a data ? during the repeated start condition, figure 17-39 . if at the end of the brg time out both scl and sda are still high, the sda pin is driven low, the brg is reloaded, and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 17-38: bus collision during a repeated start condition (case 1) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0, set bclif and release sda and scl cleared in software '0' '0'
picmicro mid-range mcu family ds31017a-page 17-54 preliminary 1997 microchip technology inc. figure 17-39: bus collision during repeated start condition (case 2) sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl t brg t brg '0' '0'
1997 microchip technology inc. preliminary ds31017a-page 17-55 section 17. mssp mssp 17 17.4.18.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been de-asserted and allowed to ?at high, sda is sampled low after the brg has timed out. b) after the scl pin is de-asserted, scl is sampled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allow to ?at. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to 0. after the brg times out sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data '0' ( figure 17-40 ). if the scl pin is sampled low before sda is allowed to ?at high, a bus collision occurs. this is another case of another master attempting to drive a data '0' ( figure 17-41 ). figure 17-40: bus collision during a stop condition (case 1) figure 17-41: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif '0' '0' sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high set bclif '0' '0'
picmicro mid-range mcu family ds31017a-page 17-56 preliminary 1997 microchip technology inc. 17.5 connection considerations for i 2 c bus for standard-mode i 2 c bus devices, the values of resistors r p and r s in figure 17-42 depends on the following parameters: supply voltage bus capacitance number of connected devices (input current + leakage current) the supply voltage limits the minimum value of resistor r p due to the speci?d minimum sink current of 3 ma at v olmax = 0.4v for the speci?d output stages. for example, with a supply volt- age of v dd = 5v+ 10% and v olmax = 0.4v at 3 ma, r pmin = (5.5-0.4)/0.003 = 1.7 k w. v dd as a function of r p is shown in figure 17-42. the desired noise margin of 0.1v dd for the low level, limits the maximum value of r s . series resistors are optional, and used to improve esd suscep- tibility. the bus capacitance is the total capacitance of wire, connections, and pins. this capacitance lim- its the maximum value of r p due to the speci?d rise time ( figure 17-42 ). the smp bit is the slew rate control enabled bit. this bit is in the sspstat register, and controls the slew rate of the i/o pins when in i 2 c mode (master or slave). figure 17-42: sample device con?uration for i 2 c bus r p r p v dd + 10% sda scl note : i 2 c devices with input levels related to v dd must have one common supply line to which the pull up resistor is also connected. device c b = 10 - 400 pf r s r s
1997 microchip technology inc. preliminary ds31017a-page 17-57 section 17. mssp mssp 17 17.6 initialization example 17-2: spi master mode initialization 17.6.1 master ssp module / basic ssp module compatibility when changing from the spi in the basic ssp module, the sspstat register contains two addi- tional control bits. these bits are: smp, spi data input sample phase cke, spi clock edge select to be compatible with the spi of the master ssp module, these bits must be appropriately con- ?ured. if these bits are not at the states shown in table 17-4 , improper spi communication may occur. table 17-4: new bit states for compatibility clrf status ; bank 0 clrf sspstat ; smp = 0, cke = 0, and clear status bits bsf sspstat, cke ; cke = 1 movlw 0x31 ; set up spi port, master mode, clk/16, movwf sspcon ; data xmit on falling edge (cke=1 & ckp=1) ; data sampled in middle (smp=0 & master mode) bsf status, rp0 ; bank 1 bsf pie, sspie ; enable ssp interrupt bcf status, rp0 ; bank 0 bsf intcon, gie ; enable, enabled interrupts movlw databyte ; data to be transmitted ; could move data from ram location movwf sspbuf ; start transmission basic ssp module master ssp module ckp ckp cke smp 1 100 0 000
picmicro mid-range mcu family ds31017a-page 17-58 preliminary 1997 microchip technology inc. 17.7 design tips question 1: using spi mode, i do not seem able to talk to an spi device. answer 1: ensure that you are using the correct spi mode for that device. this spi supports all 4 spi modes so you should be able to get it to function. check the clock polarity and the clock phase. question 2: using i 2 c mode, i write data to the sspbuf register, but the data did not transmit. answer 2: ensure that you set the ckp bit to release the i 2 c clock.
1997 microchip technology inc. preliminary ds31017a-page 17-59 section 17. mssp mssp 17 17.8 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the master ssp module are: title application note # use of the ssp module in the i 2 c multi-master environment. an578 using microchip 93 series serial eeproms with microcontroller spi ports an613 interfacing pic16c64/74 to microchip spi serial eeprom an647 interfacing a microchip pic16c92x to microchip spi serial eeprom an668
picmicro mid-range mcu family ds31017a-page 17-60 1997 microchip technology inc. 17.9 revision history revision a this is the initial released revision of the master ssp module description.
1997 microchip technology inc. ds31018a page 18-1 m usart 18 section 18. usart highlights this section of the manual contains the following major topics: 18.1 introduction ............................................................................................................... ...18-2 18.2 control registers .........................................................................................................1 8-3 18.3 usart baud rate generator (brg)...........................................................................18-5 18.4 usart asynchronous mode .......................................................................................18-8 18.5 usart synchronous master mode ...........................................................................18-15 18.6 usart synchronous slave mode .............................................................................18-19 18.7 initialization ............................................................................................................. ...18-21 18.8 design tips ................................................................................................................ 18-22 18.9 related application notes..........................................................................................18-23 18.10 revision history .........................................................................................................1 8-24
picmicro mid-range mcu family ds31018a-page 18-2 1997 microchip technology inc. 18.1 introduction the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules (other is the ssp module). the usart is also known as a serial com- munications interface or sci. the usart can be con?ured as a full duplex asynchronous sys- tem that can communicate with peripheral devices such as crt terminals and personal computers, or it can be con?ured as a half duplex synchronous system that can communicate with peripheral devices such as a/d or d/a integrated circuits, serial eeproms etc. the usart can be con?ured in the following modes: asynchronous (full duplex) synchronous - master (half duplex) synchronous - slave (half duplex) the spen bit (rcsta<7>), and the tris bits, have to be set in order to con?ure the tx/ck and rx/dt pins for the usart.
1997 microchip technology inc. ds31018a-page 18-3 section 18. usart usart 18 18.2 control registers register 18-1: txsta: transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync brgh trmt tx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode don? care synchronous mode 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4 sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as '0' bit 2 brgh : high baud rate select bit asynchronous mode 1 = high speed 0 = low speed synchronous mode unused in this mode bit 1 trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data. can be parity bit. legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31018a-page 18-4 1997 microchip technology inc. register 18-2: rcsta: receive status and control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r-0 r-0 r-0 spen rx9 sren cren ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (con?ures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled bit 6 rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren : single receive enable bit asynchronous mode don? care synchronous mode - master 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode - sla v e unused in this mode bit 4 cren : continuous receive enable bit asynchronous mode 1 = enables continuous receive 0 = disables continuous receive synchronous mode 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 unimplemented: read as '0' bit 2 ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data, can be parity bit. legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
1997 microchip technology inc. ds31018a-page 18-5 section 18. usart usart 18 18.3 usart baud rate generator (brg) the brg supports both the asynchronous and synchronous modes of the usart. it is a dedi- cated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. in asynchronous mode bit brgh (txsta<2>) also controls the baud rate. in synchronous mode bit brgh is ignored. table 18-1 shows the formula for computation of the baud rate for different usart modes which only apply in master mode (internal clock). given the desired baud rate and fosc, the nearest integer value for the spbrg register can be calculated using the formula in table 18-1 , where x equals the value in the spbrg register (0 to 255). from this, the error in baud rate can be determined. table 18-1: baud rate formula example 18-1 shows the calculation of the baud rate error for the following conditions: f osc = 16 mhz desired baud rate = 9600 brgh = 0 sync = 0 example 18-1: calculating baud rate error it may be advantageous to use the high baud rate (brgh = 1) even for slower baud clocks. this is because the f osc / (16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer over?w before outputting the new baud rate. table 18-2: registers associated with baud rate generator sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64(x+1)) (synchronous) baud rate = f osc /(4(x+1)) baud rate= f osc /(16(x+1)) na x = value in spbrg (0 to 255) desired baud rate = fosc / (64 (x + 1)) 9600 = 16000000 / (64 (x + 1)) x= ? 25.042 ? = 25 calculated baud rate = 16000000 / (64 (25 + 1)) = 9615 error = (calculated baud rate - desired baud rate) desired baud rate = (9615 - 9600) / 9600 = 0.16% name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used by the brg.
picmicro mid-range mcu family ds31018a-page 18-6 1997 microchip technology inc. table 18-3: baud rates for synchronous mode baud rate (kbps) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - na - - na - - 1.2 na - - na - - na - - na - - 2.4 na - - na - - na - - na - - 9.6 na - - na - - 9.766 +1.73 255 9.622 +0.23 185 19.2 19.53 +1.73 255 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 76.8 76.92 +0.16 64 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 96 96.15 +0.16 51 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 300 294.1 -1.96 16 307.69 +2.56 12 312.5 +4.17 7 298.3 -0.57 5 500 500 0 9 500 0 7 500 0 4 na - - high 5000 - 0 4000 - 0 2500 - 0 1789.8 - 0 low 19.53 - 255 15.625 - 255 9.766 - 255 6.991 - 255 baud rate (kbps) f osc = 5.0688 mhz 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - na - - na - - 0.303 +1.14 26 1.2 na - - na - - na - - 1.202 +0.16 207 1.170 -2.48 6 2.4 na - - na - - na - - 2.404 +0.16 103 na - - 9.6 9.6 0 131 9.615 +0.16 103 9.622 +0.23 92 9.615 +0.16 25 na - - 19.2 19.2 0 65 19.231 +0.16 51 19.04 -0.83 46 19.24 +0.16 12 na - - 76.8 79.2 +3.13 15 76.923 +0.16 12 74.57 -2.90 11 83.34 +8.51 2 na - - 96 97.48 +1.54 12 1000 +4.17 9 99.43 +3.57 8 na - - na - - 300 316.8 +5.60 3 na - - 298.3 -0.57 2 na - - na - - 500 na - - na - - na - - na - - na - - high 1267 - 0 100 - 0 894.9 - 0 250 - 0 8.192 - 0 low 4.950 - 255 3.906 - 255 3.496 - 255 0.9766 - 255 0.032 - 255
1997 microchip technology inc. ds31018a-page 18-7 section 18. usart usart 18 table 18-4: baud rates for asynchronous mode (brgh = 0) table 18-5: baud rates for asynchronous mode (brgh = 1) baud rate (kbps) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - na - - na - - 1.2 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129 1.203 +0.23 92 2.4 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64 2.380 -0.83 46 9.6 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15 9.322 -2.90 11 19.2 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 76.8 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1 na - - 96 104.2 +8.51 2 na - - na - - na - - 300 312.5 +4.17 0 na - - na - - na - - 500 na - - na - - na - - na - - high 312.5 - 0 250 - 0 156.3 - 0 111.9 - 0 low 1.221 - 255 0.977 - 255 0.6104 - 255 0.437 - 255 baud rate (kbps) f osc = 5.0688 mhz 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 0.31 +3.13 255 0.3005 -0.17 207 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1 1.2 1.2 0 65 1.202 +1.67 51 1.190 -0.83 46 1.202 +0.16 12 na - - 2.4 2.4 0 32 2.404 +1.67 25 2.432 +1.32 22 2.232 -6.99 6 na - - 9.6 9.9 +3.13 7 na - - 9.322 -2.90 5 na - - na - - 19.2 19.8 +3.13 3 na - - 18.64 -2.90 2 na - - na - - 76.8 79.2 +3.13 0 na - - na - - na - - na - - 96 na - - na - - na - - na - - na - - 300 na - - na - - na - - na - - na - - 500 na - - na - - na - - na - - na - - high 79.2 - 0 62.500 - 0 55.93 - 0 15.63 - 0 0.512 - 0 low 0.3094 - 255 3.906 - 255 0.2185 - 255 0.0610 - 255 0.0020 - 255 baud rate (kbps) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 9.6 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64 9.520 -0.83 46 19.2 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32 19.454 +1.32 22 38.4 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15 37.286 -2.90 11 57.6 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10 55.930 -2.90 7 115.2 113.636 -1.36 10 111.111 -3.55 8 125 +8.51 4 111.860 -2.90 3 250 250 0 4 250 0 3 na - - na - - 625 625 0 1 na - - 625 0 0 na - - 1250 1250 0 0 na - - na - - na - - baud rate (kbps) f osc = 5.0688 mhz 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 9.6 9.6 0 32 na - - 9.727 +1.32 22 8.928 -6.99 6 na - - 19.2 18.645 -2.94 16 1.202 +0.17 207 18.643 -2.90 11 20.833 +8.51 2 na - - 38.4 39.6 +3.12 7 2.403 +0.13 103 37.286 -2.90 5 31.25 -18.61 1 na - - 57.6 52.8 -8.33 5 9.615 +0.16 25 55.930 -2.90 3 62.5 +8.51 0 na - - 115.2 105.6 -8.33 2 19.231 +0.16 12 111.860 -2.90 1 na - - na - - 250 na - - na - - 223.721 -10.51 0 na - - na - - 625 na - - na - - na - - na - - na - - 1250 na - - na - - na - - na - - na - -
picmicro mid-range mcu family ds31018a-page 18-8 1997 microchip technology inc. 18.4 usart asynchronous mode in this mode, the usart uses standard nonreturn-to-zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8-bits. an on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscilla- tor. the usart transmits and receives the lsb ?st. the usarts transmitter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock either x16 or x64 of the bit shift rate, depending on the brgh bit (txsta<2>). parity is not supported by the hardware, but can be implemented in software (stored as the ninth data bit). asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing the sync bit (txsta<4>). the usart asynchronous module consists of the following important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 18.4.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 18-1 . the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and the txif ?g bit is set. this interrupt can be enabled/disabled by setting/clearing the txie enable bit. the txif ?g bit will be set regardless of the state of the txie enable bit and cannot be cleared in software. it will reset only when new data is loaded into the txreg register. while the txif ?g bit indicated the status of the txreg register, the trmt bit (txsta<1>) shows the status of the tsr register. the trmt status bit is a read only bit which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. transmission is enabled by setting the txen enable bit (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data and the baud rate generator (brg) has produced a shift clock ( figure 18-1 ). the transmission can also be started by ?st loading the txreg register and then setting the txen enable bit. normally when transmission is ?st started, the tsr register is empty, so a transfer to the txreg register will result in an immediate transfer to tsr resulting in an empty txreg. a back-to-back transfer is thus possible ( figure 18-3 ). clearing the txen enable bit during a transmission will cause the transmission to be aborted and will reset the transmitter. as a result the tx/ck pin will revert to hi-impedance. in order to select 9-bit transmission, transmit bit, tx9 (txsta<6>), should be set and the ninth bit should be written to the tx9d bit (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg register. this is because a data write to the txreg register can result in an immediate transfer of the data to the tsr register (if the tsr is empty). in such a case, an incorrect ninth data bit maybe loaded in the tsr register. note 1: the tsr register is not mapped in data memory so it is not available to the user. note 2: when the txen bit is set, the txif ?g bit will also be set since the transmit buffer is not yet full (still can move transmit data to the txreg register).
1997 microchip technology inc. ds31018a-page 18-9 section 18. usart usart 18 figure 18-1: usart transmit block diagram steps to follow when setting up a asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set the brgh bit. (subsection 18.3 ?sart baud rate generator (brg) ) 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are desired, then set the txie, gie and peie bits. 4. if 9-bit transmission is desired, then set the tx9 bit. 5. enable the transmission by setting the txen bit, which will also set the txif bit. 6. if 9-bit transmission is selected, the ninth bit should be loaded in the tx9d bit. 7. load data to the txreg register (starts transmission). figure 18-2: asynchronous master transmission txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen tx/ck pin pin buffer and control 8 8 word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) tx/ck pin txif bit (transmit buffer reg. empty ?g) trmt bit (transmit shift reg. empty ?g)
picmicro mid-range mcu family ds31018a-page 18-10 1997 microchip technology inc. figure 18-3: asynchronous master transmission (back to back) table 18-6: registers associated with asynchronous transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets pir txif (1) 00 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x txreg tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 0000 0000 0000 0000 pie txie (1) 00 txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous transmission. note 1: the position of this bit is device dependent. transmit shift reg. write to txreg brg output (shift clock) tx/ck pin txif bit (interrupt reg. ?g) trmt bit (transmit shift reg. empty ?g) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions.
1997 microchip technology inc. ds31018a-page 18-11 section 18. usart usart 18 18.4.2 usart asynchronous receiver the receiver block diagram is shown in figure 18-4 . the data is received on the rx/dt pin and drives the data recovery block. the data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . once asynchronous mode is selected, reception is enabled by setting the cren bit (rcsta<4>). the heart of the receiver is the receive (serial) shift register (rsr). after sampling the rx/tx pin for the stop bit, the received data in the rsr is transferred to the rcreg register (if it is empty). if the transfer is complete, the rcif ?g bit is set. the actual interrupt can be enabled/disabled by setting/clearing the rcie enable bit. the rcif ?g bit is a read only bit which is cleared by the hardware. it is cleared when the rcreg register has been read and is empty. the rcreg is a double buffered register, i.e. it is a two deep fifo. it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte begin shifting to the rsr register. on the detection of the stop bit of the third byte, if the rcreg register is still full then overrun error bit, oerr (rcsta<1>), will be set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. the oerr bit has to be cleared in soft- ware. this is done by resetting the receive logic (the cren bit is cleared and then set). if the oerr bit is set, transfers from the rsr register to the rcreg register are inhibited, so it is essential to clear the oerr bit if it is set. framing error bit, ferr (rcsta<2>), is set if a stop bit is detected as a low level. the ferr bit and the 9th receive bit are buffered the same way as the receive data. reading the rcreg will load the rx9d and ferr bits with new values, there- fore it is essential for the user to read the rcsta register before reading the next rcreg reg- ister in order not to lose the old (previous) information in the ferr and rx9d bits. figure 18-4: usart receive block diagram x64 baud rate clk spbrg baud rate generator rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 stop start (8) 7 1 0 rx9
picmicro mid-range mcu family ds31018a-page 18-12 1997 microchip technology inc. steps to follow when setting up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh. (subsection 18.3 ?sart baud rate generator (brg) ). 2. enable the asynchronous serial port by clearing the sync bit, and setting the spen bit. 3. if interrupts are desired, then set the rcie, gie and peie bits. 4. if 9-bit reception is desired, then set the rx9 bit. 5. enable the reception by setting the cren bit. 6. the rcif ?g bit will be set when reception is complete and an interrupt will be generated if the rcie bit was set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing the cren bit. figure 18-5: asynchronous reception start bit bit7/8 bit1 bit0 bit7/8 bit0 stop bit start bit start bit bit7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt ?g) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third wor d, causing the oerr (overrun) bit to be set.
1997 microchip technology inc. ds31018a-page 18-13 section 18. usart usart 18 18.4.3 sampling the data on the rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. figure 18-6 shows the waveform for the sampling circuit. the sampling operates the same regardless of the state of the brgh bit, only the source of the x16 clock is different. figure 18-6: rx pin sampling scheme, brgh = 0 or brgh = 1 18.4.3.1 device exceptions all new devices will use the sampling scheme shown in figure 18-6 . devices that have an excep- tion to the above sampling scheme are: pic16c63 pic16c65 pic16c65a pic16c73 pic16c73a pic16c74 pic16c74a these devices have a sampling circuitry that works as follows. if the brgh bit (txsta<2>) is clear (i.e., at the low baud rates), the sampling is done on the seventh, eighth and ninth falling edges of a x16 clock ( figure 18-7 ). if bit brgh is set (i.e., at the high baud rates), the sampling is done on the 3 clock edges preceding the second rising edge after the ?st falling edge of a x4 clock ( figure 18-8 and figure 18-9 ). figure 18-7: rx pin sampling scheme (brgh = 0) rx baud clk x16 clk start bit bit0 samples 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 baud clk for all but start bit (rx/dt pin) rx baud clk x16 clk start bit bit0 samples 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 baud clk for all but start bit (rx/dt pin)
picmicro mid-range mcu family ds31018a-page 18-14 1997 microchip technology inc. figure 18-8: rx pin sampling scheme (brgh = 1) figure 18-9: rx pin sampling scheme (brgh = 1) table 18-7: registers associated with asynchronous reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets pir rcif (1) 00 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x rcreg rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 0000 0000 0000 0000 pie rcie (1) 00 txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous reception. note 1: the position of this bit is device dependent. rx pin baud clk x4 clk q2, q4 clk start bit bit0 bit1 first falling edge after rx pin goes low second rising edge samples samples samples 1234123412 rx pin baud clk x4 clk q2, q4 clk start bit bit0 first falling edge after rx pin goes low second rising edge samples 12 3 4 baud clk for all but start bit
1997 microchip technology inc. ds31018a-page 18-15 section 18. usart usart 18 18.5 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner, i.e. transmission and reception do not occur at the same time. when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting the sync bit (txsta<4>). in addition, the spen enable bit (rcsta<7>) is set in order to con?ure the tx/ck and rx/dt i/o pins to ck (clock) and dt (data) lines respectively. the master mode indicates that the processor trans- mits the master clock on the ck line. the master mode is entered by setting the csrc bit (txsta<7>). 18.5.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 18-1 . the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one tcycle), the txreg is empty and the txif interrupt ?g bit is set. the interrupt can be enabled/disabled by setting/clearing enable the txie bit. the txif ?g bit will be set regardless of the state of the txie enable bit and cannot be cleared in software. it will reset only when new data is loaded into the txreg register. while the txif ?g bit indicates the status of the txreg register, the trmt bit (txsta<1>) shows the status of the tsr register. the trmt bit is a read only bit which is set when the tsr is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. transmission is enabled by setting the txen bit (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data. the ?st data bit will be shifted out on the next available rising edge of the clock on the ck line. data out is stable at the falling edge of the synchronous clock ( figure 18-10 ). the transmission can also be started by ?st loading the txreg register and then setting the txen bit. this is advantageous when slow baud rates are selected, since the brg is kept in reset when the txen, cren, and sren bits are clear. setting the txen bit will start the brg, creating a shift clock immediately. normally when transmission is ?st started, the tsr register is empty, so a transfer to the txreg register will result in an immediate transfer to tsr resulting in an empty txreg. back-to-back transfers are possible. clearing the txen bit during a transmission will cause the transmission to be aborted and will reset the transmitter. the dt and ck pins will revert to hi-impedance. if either of the cren or sren bits are set during a transmission, the transmission is aborted and the dt pin reverts to a hi-impedance state (for a reception). the ck pin will remain an output if the csrc bit is set (inter- nal clock). the transmitter logic is not reset although it is disconnected from the pins. in order to reset the transmitter, the user has to clear the txen bit. if the sren bit is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, the sren bit will be cleared and the serial port will revert back to transmitting since the txen bit is still set. the dt line will immediately switch from hi-impedance receive mode to transmit and start driving. to avoid this the txen bit should be cleared. in order to select 9-bit transmission, the tx9 bit (txsta<6>) should be set and the ninth bit should be written to the tx9d bit (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg register. this is because a data write to the txreg can result in an immediate transfer of the data to the tsr register (if the tsr is empty). if the tsr was empty and the txreg was written before writing the ?ew value to the tx9d bit, the ?resent value of of the tx9d bit is loaded.
picmicro mid-range mcu family ds31018a-page 18-16 1997 microchip technology inc. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate (subsection 18.3 ?sart baud rate generator (brg) ). 2. enable the synchronous master serial port by setting the sync, spen, and csrc bits. 3. if interrupts are desired, then set the txie bit. 4. if 9-bit transmission is desired, then set the tx9 bit. 5. enable the transmission by setting the txen bit. 6. if 9-bit transmission is selected, the ninth bit should be loaded in the tx9d bit. 7. start transmission by loading data to the txreg register. table 18-8: registers associated with synchronous master transmission figure 18-10: synchronous transmission figure 18-11: synchronous transmission (through txen) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets pir txif (1) 00 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x txreg tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 0000 0000 0000 0000 pie txie (1) 00 txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous master transmission. note 1: the position of this bit is device dependent. bit 0 bit 1 bit 7 word 1 q1q2 q3q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2 q3q4 q3q4 q1q2 q3q4 q1q2 q3q4 q1q2 q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 bit 2 bit 0 bit 1 bit 7 rx/dt pin tx/ck pin write to txreg reg txif bit (interrupt flag) trmt txen bit '1' '1' note: sync master mode; spbrg = '0'. continuous transmission of two 8-bit words. word 2 trmt bit write word1 write word2 rx/dt pin tx/ck pin write to txreg reg txif bit trmt bit bit0 bit1 bit2 bit6 bit7
1997 microchip technology inc. ds31018a-page 18-17 section 18. usart usart 18 18.5.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either of the sren (rcsta<5>) or cren (rcsta<4>) bits. data is sampled on the rx/dt pin on the falling edge of the clock. if the sren bit is set, then only a single word is received. if the cren bit is set, the reception is continuous until the cren bit is cleared. if both bits are set then the cren bit takes precedence. after clocking the last serial data bit, the received data in the receive shift register (rsr) is transferred to the rcreg register (if it is empty). when the transfer is complete, the rcif interrupt ?g bit is set. the actual interrupt can be enabled/disabled by setting/clearing the rcie enable bit. the rcif ?g bit is a read only bit which is cleared by the hardware. in this case it is cleared when the rcreg register has been read and is empty. the rcreg is a double buff- ered register, i.e. it is a two deep fifo. it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting into the rsr register. on the clocking of the last bit of the third byte, if the rcreg register is still full then overrun error bit, oerr (rcsta<1>), is set and the word in the rsr is lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. the oerr bit has to be cleared in software (by clear- ing the cren bit). if the oerr bit is set, transfers from the rsr to the rcreg are inhibited, so it is essential to clear the oerr bit if it is set. the 9th receive bit is buffered the same way as the receive data. reading the rcreg register will load the rx9d bit with a new value, therefore it is essential for the user to read the rcsta register before reading rcreg in order not to lose the old (previous) information in the rx9d bit. steps to follow when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate. (subsection 18.3 ?sart baud rate generator (brg) ) 2. enable the synchronous master serial port by setting the sync, spen, and csrc bits. 3. ensure that the cren and sren bits are clear. 4. if interrupts are desired, then set the rcie bit. 5. if 9-bit reception is desired, then set the rx9 bit. 6. if a single reception is required, set the sren bit. for continuous reception set the cren bit. 7. the rcif bit will be set when reception is complete and an interrupt will be generated if the rcie bit was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing the cren bit. table 18-9: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets pir rcif (1) 00 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x rcreg rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 0000 0000 0000 0000 pie rcie (1) 00 txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous master reception. note 1: the position of this bit is device dependent.
picmicro mid-range mcu family ds31018a-page 18-18 1997 microchip technology inc. figure 18-12: synchronous reception (master mode, sren) cren bit dt pin ck pin write to sren bit sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with sren = '1' and brg = '0'. q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 '0' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 q1 q2 q3 q4
1997 microchip technology inc. ds31018a-page 18-19 section 18. usart usart 18 18.6 usart synchronous slave mode synchronous slave mode differs from the master mode in the fact that the shift clock is supplied externally at the tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing the csrc bit (txsta<7>). 18.6.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the ?st word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) the txif ?g bit will not be set. d) when the ?st word has been shifted out of tsr, the txreg register will transfer the sec- ond word to the tsr and the txif ?g bit will now be set. e) if the txie enable bit is set, the interrupt will wake the chip from sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). steps to follow when setting up a synchronous slave transmission: 1. enable the synchronous slave serial port by setting the sync and spen bits and clearing the csrc bit. 2. clear the cren and sren bits. 3. if interrupts are desired, then set the txie enable bit. 4. if 9-bit transmission is desired, then set the tx9 bit. 5. enable the transmission by setting the txen enable bit. 6. if 9-bit transmission is selected, the ninth bit should be loaded into the tx9d bit. 7. start transmission by loading data to the txreg register. table 18-10: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets pir txif (1) 00 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x txreg tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 0000 0000 0000 0000 pie txie (1) 00 txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous slave transmission. note 1: the position of this bit is device dependent.
picmicro mid-range mcu family ds31018a-page 18-20 1997 microchip technology inc. 18.6.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical except in the case of the sleep mode. also, bit sren is a don't care in slave mode. if receive is enabled, by setting the cren bit, prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr register will transfer the data to the rcreg register and if the rcie enable bit bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). steps to follow when setting up a synchronous slave reception: 1. enable the synchronous master serial port by setting the sync and spen bits and clear- ing the csrc bit. 2. if interrupts are desired, then set the rcie enable bit. 3. if 9-bit reception is desired, then set the rx9 bit. 4. to enable reception, set the cren enable bit. 5. the rcif bit will be set when reception is complete and an interrupt will be generated, if the rcie bit was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing the cren bit. table 18-11: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets pir rcif (1) 00 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x rcreg rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 0000 0000 0000 0000 pie rcie (1) 00 txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous slave reception. note 1: the position of this bit is device dependent.
1997 microchip technology inc. ds31018a-page 18-21 section 18. usart usart 18 18.7 initialization example 18-2 is an initialization routine for asynchronous transmitter/receiver mode. example 18-3 is for the synchronous mode. in both examples the data is 8-bits, and the value to load into the spbrg register is dependent on the desired baud rate and the device frequency. example 18-2: asynchronous transmitter/receiver example 18-3: synchronous transmitter/receiver bsf status,rp0 ; go to bank1 movlw ; set baud rate movwf spbrg movlw 0x40 ; 8-bit transmit, transmitter enabled, movwf txsta ; asynchronous mode, low speed mode bsf pie1,txie ; enable transmit interrupts bsf pie1,rcie ; enable receive interrupts bcf status,rp0 ; go to bank 0 movlw 0x90 ; 8-bit receive, receiver enabled, movwf rcsta ; serial port enabled bsf status,rp0 ; go to bank 1 movlw ; set baud rate movwf spbrg movlw 0xb0 ; synchronous master,8-bit transmit, movwf txsta ; transmitter enabled, low speed mode bsf pie1,txie ; enable transmit interrupts bsf pie1,rcie ; enable receive interrupts bcf status,rp0 ; go to bank 0 movlw 0x90 ; 8-bit receive, receiver enabled, movwf rcsta ; continuous receive, serial port enabled
picmicro mid-range mcu family ds31018a-page 18-22 1997 microchip technology inc. 18.8 design tips question 1: using the asynchronous mode i am getting a lot of transmission errors. answer 1: the most common reasons are 1. you are using the high speed mode (brgh is set) on one of the devices which has an errata for this mode (pic16c65/65a/73/73a/74/74a). 2. you have incorrectly calculated the value to load in to the spbrg register 3. the sum of the baud errors for the transmitter and receiver is too high.
1997 microchip technology inc. ds31018a-page 18-23 section 18. usart usart 18 18.9 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to this section are: title application note # serial port utilities an547 servo control of a dc brushless motor an543
picmicro mid-range mcu family ds31018a-page 18-24 1997 microchip technology inc. 18.10 revision history revision a this is the initial released revision of the usart module description.
1997 microchip technology inc. ds31019a page 19-1 m voltage reference 19 section 19. voltage reference highlights this section of the manual contains the following major topics: 19.1 introduction ............................................................................................................... ...19-2 19.2 control register ........................................................................................................... 19-3 19.3 con?uring the voltage reference ..............................................................................19-4 19.4 voltage reference accuracy/error ...............................................................................19-5 19.5 operation during sleep ...............................................................................................19-5 19.6 effects of a reset......................................................................................................... 19-5 19.7 connection considerations ..........................................................................................19-6 19.8 initialization ............................................................................................................. .....19-7 19.9 design tips ................................................................................................................ ..19-8 19.10 related application notes............................................................................................19-9 19.11 revision history .........................................................................................................1 9-10
picmicro mid-range mcu family ds31019a-page 19-2 1997 microchip technology inc. 19.1 introduction the voltage reference module is typically used in conjunction with the comparator module. the comparator modules inputs do not require very large drive, and therefore the drive capability of the voltage reference is limited. the voltage reference is a 16-tap resistor ladder network that provides a selectable voltage ref- erence. the resistor ladder is segmented to provide two ranges of v ref values and has a power-down function to conserve power when the reference is not being used. the vrcon reg- ister controls the operation of the reference as shown in figure 19-1 . the block diagram is given in figure 19-1 . within each range, the 16 steps are monotonic (i.e. each increasing code will result in an increasing output). figure 19-1: voltage reference block diagram table 19-1: typical voltage reference with v dd = 5.0v vr3:vr0 v ref vrr = 1 vrr = 0 0000 0.00 v 1.25 v 0001 0.21 v 1.41 v 0010 0.42 v 1.56 v 0011 0.63 v 1.72 v 0100 0.83 v 1.88 v 0101 1.04 v 2.03 v 0110 1.25 v 2.19 v 0111 1.46 v 2.34 v 1000 1.67 v 2.50 v 1001 1.88 v 2.66 v 1010 2.08 v 2.81 v 1011 2.29 v 2.97 v 1100 2.50 v 3.13 v 1101 2.71 v 3.28 v 1110 2.92 v 3.44 v 1111 3.13 v 3.59 v note 1: see parameter d312 in the electrical speci?ations section of the device data sheet. vrr 8r (1) vr3 vr0 (from vrcon<3:0>) 16-1 analog mux 8r (1) r (1) r (1) r (1) r (1) vren v ref 16 stages
1997 microchip technology inc. ds31019a-page 19-3 section 19. voltage reference voltage reference 19 19.2 control register register 19-1: vrcon register r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 vren vroe vrr vr3 vr2 vr1 vr0 bit 7 bit 0 bit 7 vren: v ref enable 1 = v ref circuit powered on 0 = v ref circuit powered down bit 6 vroe: v ref output enable 1 = v ref is internally connected to comparator modules v ref . this voltage level is also output on the v ref pin 0 = v ref is not connected to the comparator module. this voltage is disconnected from the v ref pin bit 5 vrr: v ref range selection 1 = 0v to 0.75 v dd , with v dd /24 step size 0 = 0.25 v dd to 0.75 v dd , with v dd /32 step size bit 4 unimplemented: read as '0' bit 3:0 vr3:vr0: v ref value selection 0 vr3:vr0 15 when vrr = 1: v ref = (vr<3:0>/ 24) v dd when vrr = 0: v ref = 1/4 * v dd + (vr3:vr0/ 32) v dd legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31019a-page 19-4 1997 microchip technology inc. 19.3 con?uring the voltage reference the voltage reference can output 16 distinct voltage levels for each range. the equations used to calculate the output of the voltage reference are as follows: if vrr = 1: v ref = (vr3:vr0/24) x v dd if vrr = 0: v ref = (v dd x 1/4) + (vr3:vr0/32) x v dd the settling time of the voltage reference must be considered when changing the v ref output. example 19-1 shows an example of how to con?ure the voltage reference for an output voltage of 1.25v with v dd = 5.0v. generally the v ref and v dd of the system will be known and you need to determine the value to load into vr3:vr0. equation 19-1 shows how to calculate the vr3:vr0 value. there will be some error since vr3:vr0 can only be an integer, and the v ref and v dd levels must be chosen so that the result is not greater then 15. equation 19-1: calculating vr3:vr0 v ref v dd x 24 vr3:vr0 = when vrr = 1 v ref - v dd /4 v dd x 32 vr3:vr0 = when vrr = 0
1997 microchip technology inc. ds31019a-page 19-5 section 19. voltage reference voltage reference 19 19.4 voltage reference accuracy/error the full range of v ss to v dd cannot be realized due to the construction of the module. the tran- sistors on the top and bottom of the resistor ladder network ( figure 19-1 ) keep v ref from approaching v ss or v dd . the voltage reference is v dd derived and therefore, the v ref output changes with ?ctuations in v dd . the absolute accuracy of the voltage reference can be found in the device data sheets electrical speci?ation parameter d311 . 19.5 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the vrcon register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 19.6 effects of a reset a device reset disables the voltage reference by clearing the vren bit (vrcon<7>). this reset also disconnects the reference from the v ref pin by clearing the vroe bit (vrcon<6>) and selects the high voltage range by clearing the vrr bit (vrcon<5>). the v ref value select bits, vrcon<3:0>, are also cleared.
picmicro mid-range mcu family ds31019a-page 19-6 1997 microchip technology inc. 19.7 connection considerations the voltage reference module operates independently of the comparator module. the output of the reference generator may be connected to the v ref pin if the corresponding tris bit is set and the vroe bit (vrcon<6>) is set. enabling the voltage reference output onto the v ref pin with an input signal present will increase current consumption. con?uring the v ref as a digital output with v ref enabled will also increase current consumption. the v ref pin can be used as a simple d/a output with limited drive capability. due to the limited drive capability, a buffer must be used in conjunction with the voltage reference output for exter- nal connections to v ref . figure 19-2 shows an example buffering technique. figure 19-2: voltage reference output buffer example v ref output + v ref module r (1) anx note 1: r is the voltage reference output impedance and is dependent upon the voltage reference con?uration vrcon<3:0> and vrcon<5>. pic16cxxx
1997 microchip technology inc. ds31019a-page 19-7 section 19. voltage reference voltage reference 19 19.8 initialization example 19-1 shows the steps to con?ure the voltage reference module. example 19-1: voltage reference con?uration movlw 0x02 ; 4 inputs muxed to 2 comparators movwf cmcon ; bsf status,rp0 ; go to bank1 movlw 0x07 ; ra3:ra0 are outputs movwf trisa ; outputs movlw 0xa6 ; enable vref movwf vrcon ; low range set vr3:vr0 = 6 bcf status,rp0 ; go to bank0 call delay10 ; 10 m s delay
picmicro mid-range mcu family ds31019a-page 19-8 1997 microchip technology inc. 19.9 design tips question 1: my v ref is not what i expect. answer 1: any variation of the device v dd will translate directly onto the v ref pin. also ensure that you have correctly calculated (speci?d) the v dd divider which generates the v ref . question 2: i am connecting v ref into a low impedance circuit, and the v ref is not at the expected level. answer 2: the voltage reference module is not intended to drive large loads. a buffer must be used between the picmicros v ref pin and the load.
1997 microchip technology inc. ds31019a-page 19-9 section 19. voltage reference voltage reference 19 19.10 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to voltage ref- erence are: title application note # resistance and capacitance meter using a pic16c622 an611
picmicro mid-range mcu family ds31019a-page 19-10 1997 microchip technology inc. 19.11 revision history revision a this is the initial released revision of the voltage reference description.
1997 microchip technology inc. ds31020a page 20-1 m comparator 20 section 20. comparator highlights this section of the manual contains the following major topics: 20.1 introduction ............................................................................................................... ...20-2 20.2 control register ........................................................................................................... 20-3 20.3 comparator con?uration............................................................................................20-4 20.4 comparator operation .................................................................................................20-6 20.5 comparator reference.................................................................................................20-6 20.6 comparator response time ........................................................................................20-8 20.7 comparator outputs ....................................................................................................20-8 20.8 comparator interrupts..................................................................................................20-9 20.9 comparator operation during sleep .........................................................................20-9 20.10 effects of a reset ......................................................................................................20 -9 20.11 analog input connection considerations...................................................................20-10 20.12 initialization ............................................................................................................ ....20-11 20.13 design tips ............................................................................................................... .20-12 20.14 related application notes..........................................................................................20-13 20.15 revision history .........................................................................................................2 0-14
picmicro mid-range mcu family ds31020a-page 20-2 1997 microchip technology inc. 20.1 introduction the comparator module contains two analog comparators. the inputs to the comparators are multiplexed with the i/o pins. the on-chip voltage reference (see the ?oltage reference sec- tion) can also be an input to the comparators. the cmcon register, shown in figure 20-1 , controls the comparator input and output multiplex- ers. a block diagram of the comparator is shown in figure 20-1 .
1997 microchip technology inc. ds31020a-page 20-3 section 20. comparator comparator 20 20.2 control register register 20-1: cmcon register r-0 r-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 c2out c1out cis cm2 cm1 cm0 bit 7 bit 0 bit 7 c2out : comparator2 output indicator bit 1 = c2 v in + > c2 v in ? 0 = c2 v in + < c2 v in bit 6 c1out : comparator1 output indicator bit 1 = c1 v in + > c1 v in ? 0 = c1 v in + < c1 v in bit 5:4 unimplemented: read as '0' bit 3 cis : comparator input switch bit when cm2:cm0: = 001: 1 = c1 v in ?connects to an3 0 = c1 v in ?connects to an0 when cm2:cm0 = 010: 1 = c1 v in ?connects to an3 c2 v in ?connects to an2 0 = c1 v in ?connects to an0 c2 v in ?connects to an1 bit 2:0 cm2:cm0 : comparator mode select bits see figure 20-1 . legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31020a-page 20-4 1997 microchip technology inc. 20.3 comparator con?uration there are eight modes of operation for the comparators. the cmcon register is used to select the mode. figure 20-1 shows the eight possible modes. the tris register controls the data direction of the comparator i/o pins for each mode. if the comparator mode is changed, the com- parator output level may not be valid for the new mode for the delay speci?d in the electrical speci?ations of the device. note: comparator interrupts should be disabled during a comparator mode change, oth- erwise a false interrupt may occur.
1997 microchip technology inc. ds31020a-page 20-5 section 20. comparator comparator 20 figure 20-1: comparator i/o operating modes c1 ra0/an0 v in - v in + ra3/an3 off (read as '0') comparators reset (por default value) a a cm2:cm0 = 000 c2 ra1/an1 v in - v in + ra2/an2 off (read as '0') a a c1 ra0/an0 v in - v in + ra3/an3 c1out two independent comparators a a cm2:cm0 = 100 c2 ra1/an1 v in - v in + ra2/an2 c2out a a c1 ra0/an0 v in - v in + ra3/an3 c1out two common reference comparators a d cm2:cm0 = 011 c2 ra1/an1 v in - v in + ra2/an2 c2out a a c1 ra0/an0 v in - v in + ra3/an3 off (read as '0') one independent comparator d d cm2:cm0 = 101 c2 ra1/an1 v in - v in + ra2/an2 c2out a a c1 ra0/an0 v in - v in + ra3/an3 off (read as '0') comparators off d d cm2:cm0 = 111 c2 ra1/an1 v in - v in + ra2/an2 off (read as '0') d d c1 ra0/an0 v in - v in + ra3/an3 c1out four inputs multiplexed to two comparators a a cm2:cm0 = 010 c2 ra1/an1 v in - v in + ra2/an2 c2out a a from v ref module cis = 0 cis = 1 cis = 0 cis = 1 c1 ra0/an0 v in - v in + ra3/an3 c1out two common reference comparators with outputs a d cm2:cm0 = 110 c2 ra1/an1 v in - v in + ra2/an2 c2out a a ra4 open drain c1 ra0/an0 v in - v in + ra3/an3 c1out three inputs multiplexed to two comparators a a cm2:cm0 = 001 c2 ra1/an1 v in - v in + ra2/an2 c2out a a cis = 0 cis = 1 a = analog input, port reads as zeros always. d = digital input. cis (cmcon<3>) is the comparator input switch.
picmicro mid-range mcu family ds31020a-page 20-6 1997 microchip technology inc. 20.4 comparator operation a single comparator is shown in figure 20-2 along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in ? the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in ? the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 20-2 represent the uncertainty due to input offsets and response time. 20.5 comparator reference an external or internal reference signal may be used depending on the comparator operating mode. the analog signal that is present at v in ?is compared to the signal at v in +, and the digital output of the comparator is adjusted accordingly ( figure 20-2 ). figure 20-2: single comparator + v in + v in output v in v in+ output
1997 microchip technology inc. ds31020a-page 20-7 section 20. comparator comparator 20 20.5.1 external reference signal when external voltage references are used, the comparator module can be con?ured to have the comparators operate from the same or different reference sources. the reference signal must be between v ss and v dd , and can be applied to either pin of the comparator(s). 20.5.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference for the comparators. the ?oltage reference section contains a detailed description of the voltage reference module that provides this signal. the internal reference signal is used when the com- parators are in mode cm2:cm0 = 010 ( figure 20-1 ). in this mode, the internal voltage reference is applied to the v in + input of both comparators. the internal voltage reference may be used in any comparator mode. when used in this fashion the i/o/v ref pin may be used for i/o. the voltage reference is connected to the v ref pin.
picmicro mid-range mcu family ds31020a-page 20-8 1997 microchip technology inc. 20.6 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is guaranteed to have a valid level. if the internal reference is changed, the maximum settling time of the internal voltage reference must be considered when using the comparator outputs. otherwise the maximum response time of the comparators should be used. 20.7 comparator outputs the comparator outputs are read through the cmcon register. these bits are read only. the comparator outputs may also be directly output to the i/o pins. when cm2:cm0 = 110 , multiplex- ors in the output path of the i/o pins will switch and the output of each pin will be the unsynchro- nized output of the comparator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the speci?ations. figure 20-3 shows the compar- ator output block diagram. the tris bits will still function as the output enable/disable for the i/o pins while in this mode. figure 20-3: comparator output block diagram note 1: when reading the port register, all pins con?ured as analog inputs will read as a ?? pins con?ured as digital inputs will convert an analog input according to the schmitt trigger input speci?ation. note 2: analog levels on any pin that is de?ed as a digital input may cause the input buffer to consume more current than is speci?d. d q en to i/o pin bus data rd cmcon set multiplex cmif bit - + d q en cl port pins rd cmcon reset from other comparator
1997 microchip technology inc. ds31020a-page 20-9 section 20. comparator comparator 20 20.8 comparator interrupts the comparator interrupt ?g is set whenever the comparators value changes relative to the last value loaded into cmxout bits. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that has occurred. the cmif bit, is the comparator interrupt ?g. the cmif bit must be cleared. since it is also pos- sible to set this bit, a simulated interrupt may be initiated. the cmie bit and the peie bit (intcon<6>) must be set to enable the interrupt. in addition, the gie bit must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of the cmcon register. this will load the cmcon register with the new value with the cmxout bits. b) clear the cmif ?g bit. an interrupt condition will continue to set the cmif ?g bit. reading cmcon will end the interrupt condition, and allow the cmif ?g bit to be cleared. 20.9 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional if enabled. this interrupt will wake up the device from sleep mode when enabled. while the comparator is powered-up, each comparator that is operational will consume additional current as shown in the comparator speci?ations. to minimize power consumption while in sleep mode, turn off the comparators, cm2:cm0 = 111 , before entering sleep. if the device wakes-up from sleep, the contents of the cmcon register are not affected. 20.10 effects of a reset a device reset forces the cmcon register to its reset state. this forces the comparator module to be in the comparator reset mode, cm2:cm0 = 000. this ensures that all potential inputs are analog inputs. device current is minimized when analog inputs are present at reset time. the comparators will be powered-down during the reset interval.
picmicro mid-range mcu family ds31020a-page 20-10 1997 microchip technology inc. 20.11 analog input connection considerations a simpli?d circuit for an analog input is shown in figure 20-4 . since the analog pins are con- nected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up may occur. a maximum source impedance of 10 k w is recommended for the analog sources. figure 20-4: analog input model table 20-1: registers associated with comparator module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets cmcon c2out c1out cis cm2 cm1 cm0 00-- 0000 00-- 0000 vrcon vren vroe vrr vr3 vr2 vr1 vr0 000- 0000 000- 0000 intcon gie peie t0ie inte rbie (2) t0if intf rbif (2) 0000 000x 0000 000x pir cmif (1) 00 pie cmie (1) 00 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for comparator module. note 1: the position of this bit is device dependent. 2: these bits can also be named gpie and gpif. v ain r s a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r c < 10k i leakage 500 na v ss legend c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance v a = analog voltage
1997 microchip technology inc. ds31020a-page 20-11 section 20. comparator comparator 20 20.12 initialization the code in example 20-1 depicts example steps required to con?ure the comparator module of the pic16c62x devices. ra3 and ra4 are con?ured as digital output. ra0 and ra1 are con- ?ured as the v- inputs and ra2 as the v+ input to both comparators. example 20-1: initializing comparator module (pic16c62x) flag_reg equ 0x20 ; clrf flag_reg ; init flag register clrf porta ; init porta andlw 0xc0 ; mask comparator bits iorwf flag_reg,f ; store bits in flag register movlw 0x03 ; init comparator mode movwf cmcon ; cm<2:0> = 011 bsf status,rp0 ; select bank1 movlw 0x07 ; initialize data direction movwf trisa ; set ra<2:0> as inputs, ra<4:3> as outputs, ; trisa<7:5> always read ?? bcf status,rp0 ; select bank0 call delay 10 ; 10 m s delay movf cmcon,f ; read cmcon to end change condition bcf pir1,cmif ; clear pending interrupts bsf status,rp0 ; select bank1 bsf pie1,cmie ; enable comparator interrupts bcf status,rp0 ; select bank0 bsf intcon,peie ; enable peripheral interrupts bsf intcon,gie ; global interrupt enable
picmicro mid-range mcu family ds31020a-page 20-12 1997 microchip technology inc. 20.13 design tips question 1: my program appears to lock up. answer 1: you may be getting stuck in an in?ite loop with the comparator interrupt service routine if you did not follow the proper sequence to clear the cmif ?g bit. first you must read the cmcon register, and then you can clear the cmif ?g bit.
1997 microchip technology inc. ds31020a-page 20-13 section 20. comparator comparator 20 20.14 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the compar- ator module are: title application note # resistance and capacitance meter using a pic16c622 an611
picmicro mid-range mcu family ds31020a-page 20-14 1997 microchip technology inc. 20.15 revision history revision a this is the initial released revision of the comparator module description.
1997 microchip technology inc. ds31021a page 21-1 8-bit a/d convertor 21 m section 21. 8-bit a/d converter highlights this section of the manual contains the following major topics: 21.1 introduction ............................................................................................................... ...21-2 21.2 control registers .........................................................................................................2 1-3 21.3 operation .................................................................................................................. ...21-5 21.4 a/d acquisition requirements .....................................................................................21-6 21.5 selecting the a/d conversion clock ............................................................................21-8 21.6 con?uring analog port pins.......................................................................................21-9 21.7 a/d conversions ........................................................................................................21-1 0 21.8 a/d operation during sleep ......................................................................................21-12 21.9 a/d accuracy/error ....................................................................................................21-13 21.10 effects of a reset ....................................................................................................21-1 3 21.11 use of the ccp trigger ..............................................................................................21-14 21.12 connection considerations ........................................................................................21-14 21.13 transfer function .......................................................................................................21 -14 21.14 initialization ............................................................................................................ ....21-15 21.15 design tips ............................................................................................................... .21-16 21.16 related application notes..........................................................................................21-17 21.17 revision history .........................................................................................................2 1-18 note: please refer to appendix c.3 or device data sheet to determine which devices use this module.
picmicro mid-range mcu family ds31021a-page 21-2 1997 microchip technology inc. 21.1 introduction the analog-to-digital (a/d) converter module has up to eight analog inputs. the a/d allows conversion of an analog input signal to a corresponding 8-bit digital number. the output of the sample and hold is the input into the converter, which generates the result via suc- cessive approximation. the analog reference voltage is software selectable to either the devices positive supply voltage (v dd ) or the voltage level on the v ref pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. the a/d module has three registers. these registers are: a/d result register (adres) a/d control register0 (adcon0) a/d control register1 (adcon1) the adcon0 register, shown in figure 21-1 , controls the operation of the a/d module. the adcon1 register, shown in figure 21-2 , con?ures the functions of the port pins. the i/o pins can be con?ured as analog inputs (one i/o can also be a voltage reference) or as digital i/o. the block diagram of the a/d module is shown in figure 21-1 . figure 21-1: 8-bit a/d block diagram (input voltage) v ain v ref (reference voltage) v dd (1) pcfg2:pcfg0 chs2:chs0 000 or 010 or 100 001 or 011 or 101 an7 an6 an5 an4 an3/v ref an2 an1 an0 111 110 101 100 011 010 001 000 8-bit a/d converter note: on some devices this is a separate pin called av dd . this allows the a/d v dd to be connected to a precise voltage source.
1997 microchip technology inc. ds31021a-page 21-3 section 21. 8-bit a/d converter 8-bit a/d converter 21 21.2 control registers register 21-1: adcon0 register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done resv adon bit 7 bit 0 bit 7:6 adcs1:adcs0 : a/d conversion clock select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from the internal a/d rc oscillator) bit 5:3 chs2:chs0 : analog channel select bits 000 = channel 0, (an0) 001 = channel 1, (an1) 010 = channel 2, (an2) 011 = channel 3, (an3) 100 = channel 4, (an4) 101 = channel 5, (an5) 110 = channel 6, (an6) 111 = channel 7, (an7) note: for devices that do not implement the full 8 a/d channels, the unimplemented selec- tions are reserved. do not select any unimplemented channels. bit 2 go/done : a/d conversion status bit when adon = 1 1 = a/d conversion in progress (setting this bit starts the a/d conversion. this bit is automatically cleared by hardware when the a/d conversion is complete) 0 = a/d conversion not in progress bit 1 reserved: always maintain this bit cleared. bit 0 adon : a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shutoff and consumes no operating current legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31021a-page 21-4 1997 microchip technology inc. register 21-2: adcon1 register u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7:3 unimplemented : read as '0' bit 2:0 pcfg2:pcfg0 : a/d port con?uration control bits legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset a = analog input d = digital i/o note: when an3 is selected as v ref , the a/d reference is the voltage on the an3 pin. when an3 is selected as an analog input (a), then the voltage reference for the a/d is the device v dd . pcfg2:pcfg0 an7 an6 an5 an4 an3 an2 an1 an0 000 aa a a a a aa 001 aa a a v ref aaa 010 dd d a a a aa 011 dd a a v ref aaa 100 dd d d a d aa 101 dd d d v ref daa 11x dd d d d d dd note 1: on any device reset, the port pins multiplexed with analog functions (anx) are forced to be an analog input.
1997 microchip technology inc. ds31021a-page 21-5 section 21. 8-bit a/d converter 8-bit a/d converter 21 21.3 operation when the a/d conversion is complete, the result is loaded into the adres register, the go/done bit (adcon0<2>) is cleared, and a/d interrupt ?g bit, adif, is set. after the a/d module has been con?ured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see subsection 21.4 ?/d acquisition requirements. after this acquisition time has elapsed the a/d conversion can be started. the following steps should be followed for doing an a/d conversion: 1. con?ure the a/d module: con?ure analog pins / voltage reference / and digital i/o (adcon1) select a/d input channel (adcon0) select a/d conversion clock (adcon0) turn on a/d module (adcon0) 2. con?ure a/d interrupt (if desired): clear the adif bit set the adie bit set the gie bit 3. wait the required acquisition time. 4. start conversion: set the go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result register (adres), clear the adif bit, if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is de?ed as t ad . a minimum wait of 2t ad is required before next acquisition starts. figure 21-2 shows the conversion sequence, and the terms that are used. acquisition time is the time that the a/d modules holding capacitor is connected to the external voltage level. then there is the conversion time of 10 t ad , which is started when the go bit is set. the sum of these two times is the sampling time. there is a minimum acquisition time to ensure that the holding capacitor is charged to a level that will give the desired accuracy for the a/d conversion. figure 21-2: a/d conversion sequence acquisition time conversion time a/d sample time when a/d holding capacitor start to charge. after a/d conversion, or new a/d channel is selected. when a/d conversion is started (setting the go bit). holding capacitor is disconnected from the analog input before the conversion is started. a/d conversion complete, result is loaded in adres register. holding capacitor begins acquiring voltage level on selected channel. adif bit is set.
picmicro mid-range mcu family ds31021a-page 21-6 1997 microchip technology inc. 21.4 a/d acquisition requirements for the a/d converter to meet its speci?d accuracy, the charge holding capacitor ( c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 21-3 . the source impedance ( r s ) and the internal sampling switch ( r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch ( r ss ) imped- ance varies over the device voltage (v dd ) ( figure 21-3 ). the maximum recommended imped- ance for analog sources is 10 k w . after the analog input channel is selected (changed) the acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 21-1 may be used. this equation assumes that 1/2 lsb error is used (512 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its speci?d resolution. equation 21-1: acquisition time equation 21-2: a/d minimum charging time example 21-1 shows the calculation of the minimum required acquisition time t acq . this calcu- lation is based on the following system assumptions. rs = 10 k w conversion error 1/2 lsb v dd = 5v ? rss = 7 k w (see graph in figure 21-3 ) temperature = 50 c (system max.) v hold = 0v @ time = 0 example 21-1: calculating the minimum required acquisition time t acq = ampli?r settling time + holding capacitor charging time + temperature coef?ient =t amp + t c + t coff v hold = (v ref - (v ref /512)) ?(1 - e (-tc/c hold (r ic + r ss + r s )) ) or tc = -(51.2 pf)(1 k w + r ss + r s ) ln(1/511) t acq =t amp + t c + t coff t acq =5 m s + tc + [(temp - 25 c)(0.05 m s/ c)] t c =-c hold (r ic + r ss + r s ) ln(1/512) -51.2 pf (1 k w + 7 k w + 10 k w ) ln(0.0020) -51.2 pf (18 k w ) ln(0.0020) -0.921 m s (-6.2146) 5.724 m s t acq =5 m s + 5.724 m s + [(50 c - 25 c)(0.05 m s/ c)] 10.724 m s + 1.25 m s 11.974 m s
1997 microchip technology inc. ds31021a-page 21-7 section 21. 8-bit a/d converter 8-bit a/d converter 21 figure 21-3: analog input model note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. note 2: the charge holding capacitor (c hold ) is not discharged after each conversion. note 3: the maximum recommended impedance for analog sources is 10 k w . this is required to meet the pin leakage speci?ation. note 4: after a conversion has completed, a 2.0 t ad delay must complete before acquisition can begin again. during this time the holding capacitor is not connected to the selected a/d input channel. c pin v ain rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 51.2 pf v ss 6v sampling switch 5v 4v 3v 2v 5 6 7 8 9 10 11 ( k w ) v dd 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions = analog input voltage v ain
picmicro mid-range mcu family ds31021a-page 21-8 1997 microchip technology inc. 21.5 selecting the a/d conversion clock the a/d conversion time per bit is de?ed as t ad . the a/d conversion requires 9.5 t ad per 8-bit conversion. the source of the a/d conversion clock is software selected. the four possible options for t ad are: ?t osc ?t osc 32t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a mini- mum t ad time of 1.6 m s for all devices, as shown in parameter 130 of the devices electrical spec- i?ations. table 21-1 and table 21-2 show the resultant t ad times derived from the device operating fre- quencies and the a/d clock source selected. table 21-1: t ad vs. device operating frequencies (for standard, c, devices) table 21-2: t ad vs. device operating frequencies (for extended, lc, devices) ad clock source (t ad ) device frequency operation adcs1:adcs0 20 mhz 5 mhz 1.25 mhz 333.33 khz 2t osc 00 100 ns (2) 400 ns (2) 1.6 m s6 m s 8t osc 01 400 ns (2) 1.6 m s 6.4 m s 24 m s (3) 32t osc 10 1.6 m s 6.4 m s 25.6 m s (3) 96 m s (3) rc 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1) legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 4 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion, or the a/d accuracy may be out of speci?ation. ad clock source (t ad ) device frequency operation adcs1:adcs0 4 mhz 2 mhz 1.25 mhz 333.33 khz 2t osc 00 500 ns (2) 1.0 m s (2) 1.6 m s (2) 6 m s 8t osc 01 2.0 m s (2) 4.0 m s 6.4 m s 24 m s (3) 32t osc 10 8.0 m s 16.0 m s 25.6 m s (3) 96 m s (3) rc 11 3 - 9 m s (1,4) 3 - 9 m s (1,4) 3 - 9 m s (1,4) 3 - 9 m s (1) legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 6 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion, or the a/d accuracy may be out of speci?ation.
1997 microchip technology inc. ds31021a-page 21-9 section 21. 8-bit a/d converter 8-bit a/d converter 21 21.6 con?uring analog port pins adcon1 and the corresponding tris registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. note 1: when reading the port register, all pins con?ured as analog input channels will read as cleared (a low level). pins con?ured as digital inputs, will convert an analog input. analog levels on a digitally con?ured input will not affect the conversion accuracy. note 2: analog levels on any pin that is de?ed as a digital input (including the an7:an0 pins), may cause the input buffer to consume current that is out of the devices spec- i?ation.
picmicro mid-range mcu family ds31021a-page 21-10 1997 microchip technology inc. 21.7 a/d conversions example 21-2 show how to perform an a/d conversion. the i/o pins are con?ured as analog inputs. the analog reference (v ref ) is the device v dd . the a/d interrupt is enabled, and the a/d conversion clock is f rc . the conversion is performed on the an0 channel. clearing the go/done bit during a conversion will abort the current conversion. the adres register will not be updated with the partially completed a/d conversion sample. that is, the adres register will continue to contain the value of the last completed conversion (or the last value written to the adres register). after the a/d conversion is aborted, a 2t ad wait is required before the next acquisition is started. after this 2t ad wait, an acquisition is automatically started on the selected channel. example 21-2: doing an a/d conversion figure 21-4: a/d conversion t ad cycles note: the go/done bit should not be set in the same instruction that turns on the a/d, due to the required acquition time requirement. bsf status, rp0 ; select bank1 clrf adcon1 ; configure a/d inputs bsf pie1, adie ; enable a/d interrupts bcf status, rp0 ; select bank0 movlw 0xc1 ; rc clock, a/d is on, channel 0 is selected movwf adcon0 ; bcf pir1, adif ; clear a/d interrupt flag bit bsf intcon, peie ; enable peripheral interrupts bsf intcon, gie ; enable all interrupts ; ; ensure that the required sampling time for the selected input ; channel has elapsed. then the conversion may be started. ; bsf adcon0, go ; start a/d conversion : ; the adif bit will be set and the go/done : ; bit is cleared upon completion of the : ; a/d conversion. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 9 t ad 10 set go bit holding capacitor is disconnected from analog input holding capacitor is connected to analog input go bit is cleared next q4: adres is loaded b7 b6 b5 b4 b3 b2 b1 b0 b0 t ad 11 adif bit is set
1997 microchip technology inc. ds31021a-page 21-11 section 21. 8-bit a/d converter 8-bit a/d converter 21 figure 21-5: flowchart of a/d operation acquire adon = 0 adon = 0? go = 0? a/d clock go = 0 adif = 0 abort conversion sleep power-down a/d wait 2t ad wake-up ye s no ye s no no ye s finish conversion go = 0 adif = 1 device in no ye s finish conversion go = 0 adif = 1 wait 2t ad stay in sleep selected channel = rc? sleep no ye s instruction? start of a/d conversion delayed 1 instruction cycle from sleep? power-down a/d ye s no wait 2t ad finish conversion go = 0 adif = 1 sleep?
picmicro mid-range mcu family ds31021a-page 21-12 1997 microchip technology inc. 21.7.1 faster conversion - lower resolution trade-off not all applications require a result with 8-bits of resolution, but may instead require a faster con- version time. the a/d module allows users to make the trade-off of conversion speed to resolu- tion. regardless of the resolution required, the acquisition time is the same. to speed up the conversion, the clock source of the a/d module may be switched so that the t ad time violates the minimum speci?d time (see the applicable electrical speci?ation). once the t ad time vio- lates the minimum speci?d time, all the following a/d result bits are not valid (see a/d conver- sion timing in the electrical speci?ations section). the clock sources may only be switched between the three oscillator versions (cannot be switched from/to rc). the equation to deter- mine the time before the oscillator can be switched is as follows: conversion time = t ad + n ?t ad + (10 - n)(2t osc ) where: n = number of bits of resolution required. since the t ad is based from the device oscillator, the user must use some method (a timer, soft- ware loop, etc.) to determine when the a/d oscillator may be changed. example 21-3 shows a comparison of time required for a conversion with 4-bits of resolution, versus the 8-bit resolution conversion. the example is for devices operating at 20 mhz (the a/d clock is programmed for 32t osc ), and assumes that immediately after 5t ad , the a/d clock is programmed for 2t osc . the 2t osc violates the minimum t ad time since the last 4-bits will not be converted to correct values. example 21-3: 4-bit vs. 8-bit conversion times 21.8 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs1:adcs0 = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all internal digital switching noise from the conversion. when the conversion is completed the go/done bit will be cleared, and the result loaded into the adres register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d module will then be turned off (to conserve power), although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conversion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. freq. (mhz) (1) resolution 4-bit 8-bit t ad 20 1.6 m s 1.6 m s t osc 20 50 ns 50 ns t ad + n ?t ad + (10 - n)(2t osc ) 20 8.6 m s 17.6 m s note 1: a minimum t ad time of 1.6 m s is required. 2: if the full 8-bit conversion is required, the a/d clock source should not be changed. note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs1:adcs0 = 11 ). to perform an a/d conversion in sleep, the go/done bit must be set, followed by the sleep instruction.
1997 microchip technology inc. ds31021a-page 21-13 section 21. 8-bit a/d converter 8-bit a/d converter 21 21.9 a/d accuracy/error in systems where the device frequency is low, use of the a/d rc clock is preferred. at moderate to high frequencies, t ad should be derived from the device oscillator. the absolute accuracy speci?d for the a/d converter includes the sum of all contributions for quantization error, integral error, differential error, full scale error, offset error, and monotonicity. it is de?ed as the maximum deviation from an actual transition versus an ideal transition for any code. the absolute error of the a/d converter is speci?d at < 1 lsb for v dd = v ref (over the devices speci?d operating range). however, the accuracy of the a/d converter will degrade as v dd diverges from v ref . for a given range of analog inputs, the output digital code will be the same. this is due to the quantization of the analog input to a digital code. quantization error is typically 1/2 lsb and is inherent in the analog to digital conversion process. the only way to reduce quantization error is to increase the resolution of the a/d converter. offset error measures the ?st actual transition of a code versus the ?st ideal transition of a code. offset error shifts the entire transfer function. offset error can be calibrated out of a system or introduced into a system through the interaction of the total leakage current and source imped- ance at the analog input. gain error measures the maximum deviation of the last actual transition and the last ideal tran- sition adjusted for offset error. this error appears as a change in slope of the transfer function. the difference in gain error to full scale error is that full scale does not take offset error into account. gain error can be calibrated out in software. linearity error refers to the uniformity of the code changes. linearity errors cannot be calibrated out of the system. integral non-linearity error measures the actual code transition versus the ideal code transition adjusted by the gain error for each code. differential non-linearity measures the maximum actual code width versus the ideal code width. this measure is unadjusted. the maximum pin leakage current is speci?d in the device data sheet electrical speci?ation parameter d060 . in systems where the device frequency is low, use of the a/d rc clock is preferred. at moderate to high frequencies, t ad should be derived from the device oscillator. t ad must not violate the minimum and should be minimized to reduce inaccuracies due to noise and sampling capacitor bleed off. in systems where the device will enter sleep mode after the start of the a/d conversion, the rc clock source selection is required. in this mode, the digital noise from the modules in sleep are stopped. this method gives high accuracy. 21.10 effects of a reset a device reset forces all registers to their reset state. this forces the a/d module to be turned off, and any conversion is aborted. the value that is in the adres register is not modi?d for a power-on reset. the adres register will contain unknown data after a power-on reset.
picmicro mid-range mcu family ds31021a-page 21-14 1997 microchip technology inc. 21.11 use of the ccp trigger an a/d conversion may be started by the ?pecial event trigger of a ccp module. this requires that the ccpxm3:ccpxm0 bits (ccpxcon<3:0>) be programmed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, start- ing the a/d conversion, and the timer1 counter will be reset to zero. timer1 is reset to automat- ically repeat the a/d acquisition period with minimal software overhead (moving the adres to the desired location). the appropriate analog input channel must be selected and the minimum acquisition done before the ?pecial event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the ?pecial event trigger will be ignored by the a/d module, but will still reset the timer1 counter. 21.12 connection considerations if the input voltage exceeds the rail values (v ss or v dd ) by greater than 0.3v, then the accuracy of the conversion is out of speci?ation. an external rc ?ter can sometimes be added for anti-aliasing of the input signal. the r compo- nent should be selected to ensure that the total source impedance is kept under the 10 k w rec- ommended speci?ation. any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. 21.13 transfer function the ideal transfer function of the a/d converter is as follows: the ?st transition occurs when the analog input voltage (v ain ) is 1 lsb (or analog v ref / 256) ( figure 21-6 ). figure 21-6: a/d transfer function digital code output ffh feh 04h 03h 02h 01h 00h 0.5 lsb 1 lsb 2 lsb 3 lsb 4 lsb 255 lsb 256 lsb (full scale) analog input voltage
1997 microchip technology inc. ds31021a-page 21-15 section 21. 8-bit a/d converter 8-bit a/d converter 21 21.14 initialization example 21-4 shows the initialization of the a/d module for the pic16c74a example 21-4: a/d initialization (for pic16c74a) bsf status, rp0 ; select bank1 clrf adcon1 ; configure a/d inputs bsf pie1, adie ; enable a/d interrupts bcf status, rp0 ; select bank0 movlw 0xc1 ; rc clock, a/d is on, channel 0 is selected movwf adcon0 ; bcf pir1, adif ; clear a/d interrupt flag bit bsf intcon, peie ; enable peripheral interrupts bsf intcon, gie ; enable all interrupts ; ; ensure that the required sampling time for the selected input ; channel has elapsed. then the conversion may be started. ; bsf adcon0, go ; start a/d conversion : ; the adif bit will be set and the go/done : ; bit is cleared upon completion of the : ; a/d conversion.
picmicro mid-range mcu family ds31021a-page 21-16 1997 microchip technology inc. 21.15 design tips question 1: i am using one of your pic16c7x devices, and i ?d that the analog to dig- ital converter result is not always accurate. what can i do to improve accu- racy? answer 1: 1. make sure you are meeting all of the timing speci?ations. if you are turning the a/d mod- ule off and on, there is a minimum delay you must wait before taking a sample, if you are changing input channels, there is a minimum delay you must wait for this as well, and ?ally there is tad, which is the time selected for each bit conversion. this is selected in adcon0 and should be between 2 and 6 m s. if t ad is too short, the result may not be fully converted before the conversion is terminated, and if t ad is made too long the voltage on the sampling capacitor can droop before the conversion is complete. these timing speci- ?ations are provided in the data book in a table or by way of a formula, and should be looked up for your speci? part and circumstances. 2. often the source impedance of the analog signal is high (greater than 1k ohms) so the current drawn from the source to charge the sample capacitor can affect accuracy. if the input signal does not change too quickly, try putting a 0.1 m f capacitor on the analog input. this capacitor will charge to the analog voltage being sampled, and supply the instanta- neous current needed to charge the 51.2 pf internal holding capacitor. 3. finally, straight from the data book: ?n systems where the device frequency is low, use of the a/d clock derived from the device oscillator is preferred...this reduces, to a large extent, the effects of digital switching noise. and ?n systems where the device will enter sleep mode after start of a/d conversion, the rc clock source selection is required. this method gives the highest accuracy. question 2: after starting an a/d conversion may i change the input channel (for my next conversion)? answer 2: after the holding capacitor is disconnected from the input channel, one t ad after the go bit is set, the input channel may be changed. question 3: do you know of a good reference on a/ds? answer 3: a very good reference for understanding a/d conversions is the ?nalog-digital conversion handbook third edition, published by prentice hall (isbn 0-13-03-2848-0).
1997 microchip technology inc. ds31021a-page 21-17 section 21. 8-bit a/d converter 8-bit a/d converter 21 21.16 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the 8-bit a/d are: title application note # using the analog to digital converter an546 four channel digital voltmeter with display and keyboard an557
picmicro mid-range mcu family ds31021a-page 21-18 1997 microchip technology inc. 21.17 revision history revision a this is the initial released revision of the 8-bit a/d module description.
1997 microchip technology inc. ds31022a page 22-1 m basic 8-bit a/d converter 22 section 22. basic 8-bit a/d converter highlights this section of the manual contains the following major topics: 22.1 introduction ............................................................................................................... ...22-2 22.2 control registers .........................................................................................................2 2-3 22.3 a/d acquisition requirements .....................................................................................22-6 22.4 selecting the a/d conversion clock ............................................................................22-8 22.5 con?uring analog port pins.....................................................................................22-10 22.6 a/d conversions ........................................................................................................22-1 1 22.7 a/d operation during sleep ......................................................................................22-14 22.8 a/d accuracy/error ....................................................................................................22-15 22.9 effects of a reset ....................................................................................................22-16 22.10 connection considerations ........................................................................................22-16 22.11 transfer function .......................................................................................................22 -16 22.12 initialization ............................................................................................................ ....22-17 22.13 design tips ............................................................................................................... .22-18 22.14 related application notes..........................................................................................22-19 22.15 revision history .........................................................................................................2 2-20 note: please refer to appendix c.2 or the device data sheet to determine which devices use this module.
picmicro mid-range mcu family ds31022a-page 22-2 1997 microchip technology inc. 22.1 introduction this analog-to-digital (a/d) converter module has four analog inputs. the a/d allows conversion of an analog input signal to a corresponding 8-bit digital number. the output of the sample and hold is the input into the converter, which generates the result via suc- cessive approximation. the analog reference voltage is software selectable to either the devices positive supply voltage (v dd ) or the voltage level on the an3/v ref pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. the a/d module has three registers. these registers are: a/d result register (adres) a/d control register0 (adcon0) a/d control register1 (adcon1) the adcon0 register, shown in figure 22-1 controls the operation of the a/d module. the adcon1 register, shown in figure 22-2 , con?ures the functions of the port pins. the port pins can be con?ured as analog inputs (or a voltage reference) or as digital i/o. figure 22-1: basic 8-bit a/d block diagram (input voltage) v ain v ref (reference voltage) v dd pcfg1:pcfg0 chs1:chs0 00 or 10 or 11 01 an3/v ref an0 an2 an1 11 10 01 00 basic 8-bit converter a/d
1997 microchip technology inc. ds31022a-page 22-3 section 22. basic 8-bit a/d converter basic 8-bit a/d converter 22 22.2 control registers register 22-1: adcon0 register r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs1 adcs0 (1) chs1 chs0 go/done adif / (2) adon bit 7 bit 0 bit 7:6 adcs1:adcs0: a/d conversion clock select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from the internal a/d rc oscillator) bit 5 unimplemented : read as '0'. bit 4:3 chs1:chs0 : analog channel select bits 00 = channel 0, (an0) 01 = channel 1, (an1) 10 = channel 2, (an2) 11 = channel 3, (an3) bit 2 go/done : a/d conversion status bit if adon = 1 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 = a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conversion is complete) bit 1 adif (2) : a/d conversion complete interrupt flag bit 1 = conversion is complete (must be cleared in software) 0 = conversion is not complete bit 0 adon: a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shutoff and consumes no operating current legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset note 1: for the pic16c71, bit5 of adcon0 is a general purpose r/w bit. for the pic16c710/711/715, this bit is unimplemented, read as '0'. note 2: for the pic12cxxx devices, this bit is reserved. the adif bit is implemented in the pir register. use of this bit a a general purpose r/w bit is not recommended. always maintain this bit cleared.
picmicro mid-range mcu family ds31022a-page 22-4 1997 microchip technology inc. register 22-2: adcon1 register u-0 u-0 u-0 u-0 u-0 u-0 / r/w-0 r/w-0 r/w-0 ?/ pcfg2 (1) pcfg1 pcfg0 bit 7 bit 0 bit 7:2 unimplemented: read as '0' note: some devices implement bit2 as the pcfg2 bit. bit 1:0 pcfg1:pcfg0 : a/d port con?uration control bits bit 2:0 pcfg2:pcfg0 : a/d port con?uration control bits (1) legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset note 1: some devices add an additional port con?uration bit (pcfg2). this allows the min- imum number of analog channels to be one. this is of most bene? to the 8-pin devices with the a/d converter, since in an 8-pin device i/o is a premium resource. in the other devices this bit is unimplemented, and read as ?? note 2: on any device reset, the port pins multiplexed with analog functions (anx) are forced to be an analog input. a = analog input d = digital i/o note: when an3 is selected as v ref +, the a/d reference is the voltage on the an3 pin. when an3 is selected as an analog input (a), then the voltage reference for the a/d is the device v dd . pcfg1:pcfg0 an3 an2 an1 an0 00 aaaa 01 v ref +a a a 10 ddaa 11 dddd a = analog input d = digital i/o note: when an1 is selected as v ref +, the a/d reference is the voltage on the an1 pin. when an1 is selected as an analog input (a), then the voltage reference for the a/d is the device v dd . pcfg2:pcfg0 an3 an2 an1 an0 000 aaaa 001 aav ref +a 010 daaa 011 dav ref +a 100 ddaa 101 ddv ref +a 110 ddda 111 dddd
1997 microchip technology inc. ds31022a-page 22-5 section 22. basic 8-bit a/d converter basic 8-bit a/d converter 22 the adres register contains the result of the a/d conversion. when the a/d conversion is com- plete, the result is loaded into the adres register, the go/done bit (adcon0<2>) is cleared, and a/d interrupt ?g bit adif is set. the block diagram of the a/d module is shown in figure 22-1 . after the a/d module has been con?ured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as an input. to determine sample time, see subsection 22.3 ?/d acquisition requirements after this acquisition time has elapsed the a/d conversion can be started. the following steps should be followed for doing an a/d conversion: 1. con?ure the a/d module: con?ure analog pins / voltage reference / and digital i/o (adcon1) select a/d input channel (adcon0) select a/d conversion clock (adcon0) turn on a/d module (adcon0) 2. con?ure a/d interrupt (if desired): clear the adif bit set the adie bit set the gie bit 3. wait the required acquisition time. 4. start conversion: set the go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result register (adres), clear the adif bit, if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is de?ed as t ad . a minimum wait of 2t ad is required before next acquisition starts. figure 22-2 shows the conversion sequence, and the terms that are used. acquisition time is the time that the a/d modules holding capacitor is connected to the external voltage level. then there is the conversion time of 10 t ad , which is started when the go bit is set. the sum of these two times is the sampling time. there is a minimum acquisition time to ensure that the holding capacitor is charged to a level that will give the desired accuracy for the a/d conversion. figure 22-2: a/d conversion sequence acquisition time a/d conversion time a/d sample time when a/d holding capacitor start to charge. after a/d conversion, or new a/d channel is selected when a/d conversion is started (setting the go bit) a/d conversion complete, result is loaded in adres register. holding capacitor begins acquiring voltage level on selected channel adif bit is set
picmicro mid-range mcu family ds31022a-page 22-6 1997 microchip technology inc. 22.3 a/d acquisition requirements for the a/d converter to meet its speci?d accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 22-3 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) imped- ance varies over the device voltage (v dd ), see figure 22-3 . the maximum recommended impedance for analog sources is 10 k w . after the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 22-1 may be used. this equation assumes that 1/2 lsb error is used (512 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its speci?d resolution. equation 22-1:acquisition time equation 22-2:a/d minimum charging time example 22-1 shows the calculation of the minimum required acquisition time t acq . this calcu- lation is based on the following system assumptions. rs = 10 k w conversion error 1/2 lsb v dd = 5v ? rss = 7 k w (see graph in figure 22-3 ) temperature = 50 c (system max.) v hold = 0v @ time = 0 example 22-1: calculating the minimum required acquisition time t acq = ampli?r settling time + holding capacitor charging time + temperature coef?ient =t amp + t c + t coff v hold = (v ref - (v ref /512)) ?(1 - e (-tc/c hold (r ic + r ss + r s )) ) or tc = -(51.2 pf)(1 k w + r ss + r s ) ln(1/511) t acq =t amp + t c + t coff t acq =5 m s + tc + [(temp - 25 c)(0.05 m s/ c)] t c =-c hold (r ic + r ss + r s ) ln(1/512) -51.2 pf (1 k w + 7 k w + 10 k w ) ln(0.0020) -51.2 pf (18 k w ) ln(0.0020) -0.921 m s (-6.2146) 5.724 m s t acq =5 m s + 5.724 m s + [(50 c - 25 c)(0.05 m s/ c)] 10.724 m s + 1.25 m s 11.974 m s
1997 microchip technology inc. ds31022a-page 22-7 section 22. basic 8-bit a/d converter basic 8-bit a/d converter 22 figure 22-3: analog input model note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. note 2: the charge holding capacitor (c hold ) is not discharged after each conversion. note 3: the maximum recommended impedance for analog sources is 10 k w . this is required to meet the pin leakage speci?ation. note 4: after a conversion has completed, a 2.0 t ad delay must complete before acquisition can begin again. during this time the holding capacitor is not connected to the selected a/d input channel. c pin va rs rax 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 51.2 pf v ss 6v sampling switch 5v 4v 3v 2v 5 6 7 8 9 10 11 ( k w ) v dd 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
picmicro mid-range mcu family ds31022a-page 22-8 1997 microchip technology inc. 22.4 selecting the a/d conversion clock the a/d conversion time per bit is de?ed as t ad . the a/d conversion requires 9.5 t ad per 8-bit conversion. the source of the a/d conversion clock is software selected. the four possible options for t ad are: ?t osc ?t osc 32t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a mini- mum t ad time of: 2.0 m s for the pic16c71, as shown in parameter 130 of devices electrical speci?ations. 1.6 m s for all other devices, as shown in parameter 130 of devices electrical speci?ations. table 22-1 through table 22-4 show the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 22-1: t ad vs. device operating frequencies, all devices (except pic16c71) (c devices) table 22-2: t ad vs. device operating frequencies, all devices (except pic16lc71) (lc devices) ad clock source (t ad ) device frequency operation adcs1:adcs0 20 mhz 5 mhz 1.25 mhz 333.33 khz 2t osc 00 100 ns (2) 400 ns (2) 1.6 m s6 m s 8t osc 01 400 ns (2) 1.6 m s 6.4 m s 24 m s (3) 32t osc 10 1.6 m s 6.4 m s 25.6 m s (3) 96 m s (3) rc (5) 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1) note 1: the rc source has a typical t ad time of 4 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion, or the a/d accuracy may be out of speci?ation. ad clock source (t ad ) device frequency operation adcs1:adcs0 4 mhz 2 mhz 1.25 mhz 333.33 khz 2t osc 00 500 ns (2) 1.0 m s (2) 1.6 m s (2) 6 m s 8t osc 01 2.0 m s (2) 4.0 m s 6.4 m s 24 m s (3) 32t osc 10 8.0 m s 16.0 m s 25.6 m s (3) 96 m s (3) rc (5) 11 3 - 9 m s (1,4) 3 - 9 m s (1,4) 3 - 9 m s (1,4) 3 - 9 m s (1) note 1: the rc source has a typical t ad time of 6 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion, or the a/d accuracy may be out of speci?ation.
1997 microchip technology inc. ds31022a-page 22-9 section 22. basic 8-bit a/d converter basic 8-bit a/d converter 22 table 22-3: t ad vs. device operating frequencies, pic16c71 ( c devices) table 22-4: t ad vs. device operating frequencies, pic16lc71 ( lc devices) ad clock source (t ad ) device frequency operation adcs1:adcs0 20 mhz 16 mhz 4 mhz 1 mhz 333.33 khz 2t osc 00 100 ns (2) 125 ns (2) 500 ns (2) 2.0 m s6 m s 8t osc 01 400 ns (2) 500 ns (2) 2.0 m s 8.0 m s 24 m s (3) 32t osc 10 1.6 m s (2) 2.0 m s 8.0 m s 32.0 m s (3) 96 m s (3) rc 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1) 2 - 6 m s (1) legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 4 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion, or the a/d accuracy may be out of speci?ation. ad clock source (t ad ) device frequency operation adcs1:adcs0 4 mhz 2 mhz 1.25 mhz 333.33 khz 2t osc 00 500 ns (2) 1.0 m s (2) 1.6 m s (2) 6 m s 8t osc 01 2.0 m s (2) 4.0 m s 6.4 m s 24 m s (3) 32t osc 10 8.0 m s 16.0 m s 25.6 m s (3) 96 m s (3) rc 11 3 - 9 m s (1,4) 3 - 9 m s (1,4) 3 - 9 m s (1,4) 3 - 9 m s (1) legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 6 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion, or the a/d accuracy may be out of speci?ation.
picmicro mid-range mcu family ds31022a-page 22-10 1997 microchip technology inc. 22.5 configuring analog port pins the adcon1 and trisa registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs1:chs0 bits and the tris bits. note 1: when reading the port register, all pins con?ured as analog input channel will read as cleared (a low level). pins con?ured as digital inputs, will convert an analog input. analog levels on a digitally con?ured input will not affect the conversion accuracy. note 2: analog levels on any pin that is de?ed as a digital input (including the an3:an0 pins), may cause the input buffer to consume current that is out of the devices spec- i?ation.
1997 microchip technology inc. ds31022a-page 22-11 section 22. basic 8-bit a/d converter basic 8-bit a/d converter 22 22.6 a/d conversions example 22-2 show how to perform an a/d conversion. the ra pins are con?ured as analog inputs. the analog reference (v ref ) is the device v dd . the a/d interrupt is enabled, and the a/d conversion clock is f rc . the conversion is performed on the ra0 channel. clearing the go/done bit during a conversion will abort the current conversion. the adres register will not be updated with the partially completed a/d conversion sample. that is, the adres register will continue to contain the value of the last completed conversion (or the last value written to the adres register). after the a/d conversion is aborted, a 2t ad wait is required before the next acquisition is started. after this 2t ad wait, an acquisition is automatically started on the selected channel. example 22-2: doing an a/d conversion figure 22-4: a/d conversion t ad cycles note: the go/done bit should not be set in the same instruction that turns on the a/d, due to the required acquisition time. bsf status, rp0 ; select bank1 clrf adcon1 ; configure a/d inputs bcf status, rp0 ; select bank0 movlw 0xc1 ; rc clock, a/d is on, channel 0 selected movwf adcon0 ; bsf intcon, adie ; enable a/d interrupt bsf intcon, gie ; enable all interrupts ; ; ensure that the required sampling time for the selected input ; channel has elapsed. then the conversion may be started. ; bsf adcon0, go ; start a/d conversion : ; the adif bit will be set and the go/done bit : ; is cleared upon completion of the ; a/d conversion. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 9 t ad 10 set go bit holding capacitor is disconnected from analog input holding capacitor is connected to analog input go bit is cleared next q4: adres is loaded b7 b6 b5 b4 b3 b2 b1 b0 b0 t ad 11 adif bit is set
picmicro mid-range mcu family ds31022a-page 22-12 1997 microchip technology inc. figure 22-5: flowchart of a/d operation acquire adon = 0 adon = 0? go = 0? a/d clock go = 0 adif = 0 abort conversion sleep power-down a/d wait 2t ad wake-up ye s no ye s no no ye s finish conversion go = 0 adif = 1 device in no ye s finish conversion go = 0 adif = 1 wait 2t ad stay in sleep selected channel = rc? sleep no ye s instruction? start of a/d conversion delayed 1 instruction cycle from sleep? power-down a/d ye s no wait 2t ad finish conversion go = 0 adif = 1 sleep?
1997 microchip technology inc. ds31022a-page 22-13 section 22. basic 8-bit a/d converter basic 8-bit a/d converter 22 22.6.1 faster conversion - lower resolution trade-off not all applications require a result with 8-bits of resolution, but may instead require a faster con- version time. the a/d module allows users to make the trade-off of conversion speed to resolu- tion. regardless of the resolution required, the acquisition time is the same. to speed up the conversion, the clock source of the a/d module may be switched so that the t ad time violates the minimum speci?d time (see the applicable electrical speci?ation). once the t ad time vio- lates the minimum speci?d time, all the following a/d result bits are not valid (see a/d conver- sion timing in the electrical speci?ations section.) the clock sources may only be switched between the three oscillator versions (cannot be switched from/to rc). the equation to deter- mine the time before the oscillator can be switched is as follows: conversion time = t ad + n ?t ad + (10 - n)(2t osc ) where: n = number of bits of resolution required. since the t ad is based from the device oscillator, the user must use some method (a timer, soft- ware loop, etc.) to determine when the a/d oscillator may be changed. example 22-3 shows a comparison of time required for a conversion with 4-bits of resolution, versus the 8-bit resolution conversion. the example is for devices operating at 20 mhz and 16 mhz (the a/d clock is pro- grammed for 32t osc ), and assumes that immediately after 5t ad , the a/d clock is programmed for 2t osc . the 2t osc violates the minimum t ad time since the last 4-bits will not be converted to correct values. example 22-3: 4-bit vs. 8-bit conversion times freq. (mhz) (1) resolution 4-bit 8-bit t ad 20 1.6 m s 1.6 m s 16 2.0 m s 2.0 m s t osc 20 50 ns 50 ns 16 62.5 ns 62.5 ns t ad + n ?t ad + (10 - n)(2t osc ) 20 8.6 m s 17.6 m s 16 10.75 m s 22 m s note 1: the pic16c71 has a minimum t ad time of 2.0 m s. all other devices have a minimum t ad time of 1.6 m s. 2: if the full 8-bit conversion is required, the a/d clock source should not be changed.
picmicro mid-range mcu family ds31022a-page 22-14 1997 microchip technology inc. 22.7 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs1:adcs0 = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all internal digital switching noise from the conversion. when the conversion is completed the go/done bit will be cleared, and the result loaded into the adres register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d module will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conversion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs1:adcs0 = 11 ). to perform an a/d conversion in sleep, the go/done bit must be set, followed by the sleep instruction.
1997 microchip technology inc. ds31022a-page 22-15 section 22. basic 8-bit a/d converter basic 8-bit a/d converter 22 22.8 a/d accuracy/error in systems where the device frequency is low, use of the a/d rc clock is preferred. at moderate to high frequencies, t ad should be derived from the device oscillator. the absolute accuracy speci?d for the a/d converter includes the sum of all contributions for quantization error, integral error, differential error, full scale error, offset error, and monotonicity. it is de?ed as the maximum deviation from an actual transition versus an ideal transition for any code. the absolute error of the a/d converter is speci?d at < 1 lsb for v dd = v ref (over the devices speci?d operating range). however, the accuracy of the a/d converter will degrade as v dd diverges from v ref . for a given range of analog inputs, the output digital code will be the same. this is due to the quantization of the analog input to a digital code. quantization error is typically 1/2 lsb and is inherent in the analog to digital conversion process. the only way to reduce quantization error is to increase the resolution of the a/d converter. offset error measures the ?st actual transition of a code versus the ?st ideal transition of a code. offset error shifts the entire transfer function. offset error can be calibrated out of a system or introduced into a system through the interaction of the total leakage current and source imped- ance at the analog input. gain error measures the maximum deviation of the last actual transition and the last ideal tran- sition adjusted for offset error. this error appears as a change in slope of the transfer function. the difference in gain error to full scale error is that full scale does not take offset error into account. gain error can be calibrated out in software. linearity error refers to the uniformity of the code changes. linearity errors cannot be calibrated out of the system. integral non-linearity error measures the actual code transition versus the ideal code transition adjusted by the gain error for each code. differential non-linearity measures the maximum actual code width versus the ideal code width. this measure is unadjusted. the maximum pin leakage current is speci?d in the device data sheet electrical speci?ation parameter d060 . in systems where the device frequency is low, use of the a/d rc clock is preferred. at moderate to high frequencies, t ad should be derived from the device oscillator. t ad must not violate the minimum and should be minimized to reduce inaccuracies due to noise and sampling capacitor bleed off. in systems where the device will enter sleep mode after the start of the a/d conversion, the rc clock source selection is required. in this mode, the digital noise from the modules in sleep are stopped. this method gives high accuracy.
picmicro mid-range mcu family ds31022a-page 22-16 1997 microchip technology inc. 22.9 effects of a reset a device reset forces all registers to their reset state. this forces the a/d module to be turned off, and any conversion is aborted. the value that is in the adres register is not modi?d for a power-on reset. the adres register will contain unknown data after a power-on reset. 22.10 connection considerations if the input voltage exceeds the rail values (v ss or v dd ) by greater than 0.2v, then the accuracy of the conversion is out of speci?ation. an external rc ?ter is sometimes added for anti-aliasing of the input signal. the r component should be selected to ensure that the total source impedance is kept under the 10 k w recom- mended speci?ation. any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. 22.11 transfer function the ideal transfer function of the a/d converter is as follows: the ?st transition occurs when the analog input voltage (v ain ) is 1 lsb (or analog v ref / 256) ( figure 22-6 ). figure 22-6: a/d transfer function note: care must be taken when using the ra0 pin in a/d conversions due to its proximity to the osc1 pin. digital code output ffh feh 04h 03h 02h 01h 00h 0.5 lsb 1 lsb 2 lsb 3 lsb 4 lsb 255 lsb 256 lsb (full scale) analog input voltage
1997 microchip technology inc. ds31022a-page 22-17 section 22. basic 8-bit a/d converter basic 8-bit a/d converter 22 22.12 initialization example 22-4 shows the initialization of the a/d module in the pic16c711. example 22-4: a/d initialization (for pic16c711) bsf status, rp0 ; select bank1 clrf adcon1 ; configure a/d inputs bcf status, rp0 ; select bank0 movlw 0xc1 ; rc clock, a/d is on, channel 0 selected movwf adcon0 ; bsf intcon, adie ; enable a/d interrupt bsf intcon, gie ; enable all interrupts ; ; ensure that the required sampling time for the selected input ; channel has elapsed. then the conversion may be started. ; bsf adcon0, go ; start a/d conversion : ; the adif bit will be set and the go/done bit : ; is cleared upon completion of the ; a/d conversion.
picmicro mid-range mcu family ds31022a-page 22-18 1997 microchip technology inc. 22.13 design tips question 1: i am using one of your pic16c7x devices, and i ?d that the analog to dig- ital converter result is not always accurate. what can i do to improve accu- racy? answer 1: 1. make sure you are meeting all of the timing speci?ations. if you are turning the adc off and on, there is a minimum delay you must wait before taking a sample, if you are chang- ing input channels, there is a minimum delay you must wait for this as well, and ?ally there is t ad , which is the time selected for each bit conversion. this is selected in adcon0 and should be between 2 and 6 m s. if t ad is too short, the result may not be fully converted before the conversion is terminated, and if tad is made too long the voltage on the sampling capacitor can droop before the conversion is complete. these timing speci- ?ations are provided in the data book in a table or by way of a formula, and should be looked up for your speci? part and circumstances. 2. often the source impedance of the analog signal is high (greater than 1k ohms) so the current drawn from the source to charge the sample capacitor can affect accuracy. if the input signal does not change too quickly, try putting a 0.1 m f capacitor on the analog input. this capacitor will charge to the analog voltage being sampled, and supply the instanta- neous current needed to charge the 51.2 pf internal holding capacitor. 3. on the pic16c71, one of the analog input pins is next to an oscillator pin. naturally if these traces are next to each other some noise can couple from the oscillator to the ana- log circuit. this is especially true when the clock source is an external canned oscillator, since its output is a square wave with a high frequency component to its sharp edge, as opposed to a crystal circuit which provides a slower rise sine wave. again, decoupling the analog pin can help, or if you can spare it, turn the pin into an output and drive it low. this will really help eliminate cross coupling into the analog circuit. 4. finally, straight from the data book: ?n systems where the device frequency is low, use of the a/d clock derived from the device oscillator is preferred...this reduces, to a large extent, the effects of digital switching noise. and ?n systems where the device will enter sleep mode after start of a/d conversion, the rc clock source selection is required. this method gives the highest accuracy. question 2: after starting an a/d conversion may i change the input channel (for my next conversion)? answer 2: after the holding capacitor is disconnected from the input channel, one t ad after the go bit is set, the input channel may be changed. question 3: do you know of a good reference on a/ds? answer 3: a very good reference for understanding a/d conversions is the ?nalog-digital conversion handbook third edition, published by prentice hall (isbn 0-13-03-2848-0).
1997 microchip technology inc. ds31022a-page 22-19 section 22. basic 8-bit a/d converter basic 8-bit a/d converter 22 22.14 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the basic 8-bit a/d module are: title application note # using the analog to digital converter an546 four channel digital voltmeter with display and keyboard an557
picmicro mid-range mcu family ds31022a-page 22-20 1997 microchip technology inc. 22.15 revision history revision a this is the initial released revision of the basic 8-bit a/d converter module description.
1997 microchip technology inc. preliminary ds31023a page 23-1 m 10-bit a/d converter 23 section 23. 10-bit a/d converter highlights this section of the manual contains the following major topics: 23.1 introduction ............................................................................................................... ...23-2 23.2 control register ........................................................................................................... 23-3 23.3 operation .................................................................................................................. ...23-5 23.4 a/d acquisition requirements .....................................................................................23-6 23.5 selecting the a/d conversion clock ............................................................................23-8 23.6 con?uring analog port pins.......................................................................................23-9 23.7 a/d conversions ........................................................................................................23-1 0 23.8 operation during sleep .............................................................................................23-14 23.9 effects of a reset.......................................................................................................23 -14 23.10 a/d accuracy/error ....................................................................................................23-1 5 23.11 connection considerations ........................................................................................23-16 23.12 transfer function .......................................................................................................23 -16 23.13 initialization ............................................................................................................ ....23-17 23.14 design tips ............................................................................................................... .23-18 23.15 related application notes..........................................................................................23-19 23.16 revision history .........................................................................................................2 3-20 note 1: at present no released mid-range mcu devices are available with this module. devices are planned, but there is no schedule for availability. please refer to micro- chips web site or bbs for release of product briefs which detail the features of devices. if your current design requires a 10-bit a/d, please look at the pic17c756 which has a 12-channel 10-bit a/d. this a/d has characteristics which are identical to this mod- ules description.
picmicro mid-range mcu family ds31023a-page 23-2 preliminary 1997 microchip technology inc. 23.1 introduction the analog-to-digital (a/d) converter module can have up to eight analog inputs for a device. the analog input charges a sample and hold capacitor. the output of the sample and hold capac- itor is the input into the converter. the converter then generates a digital result of this analog level via successive approximation. this a/d conversion, of the analog input signal, results in a corre- sponding 10-bit digital number. the analog reference voltages (positive and negative supply) are software selectable to either the devices supply voltages (av dd , avss) or the voltage level on the an3/v ref + and an2/v ref - pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. the a/d module has four registers. these registers are: a/d result high register (adresh) a/d result low register (adresl) a/d control register0 (adcon0) a/d control register1 (adcon1) the adcon0 register, shown in figure 23-1 , controls the operation of the a/d module. the adcon1 register, shown in figure 23-2 , con?ures the functions of the port pins. the port pins can be con?ured as analog inputs (an3 and an2 can also be the voltage references) or as dig- ital i/o. figure 23-1: 10-bit a/d block diagram (input voltage) v ain v ref + reference voltage av dd pcfg0 chs2:chs0 an7 an6 an5 an4 an3 an2 an1 an0 111 110 101 100 011 010 001 000 10-bit converter v ref - av ss a/d
1997 microchip technology inc. preliminary ds31023a-page 23-3 section 23. 10-bit a/d converter 10-bit a/d converter 23 23.2 control register register 23-1: adcon0 register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done adon bit 7 bit 0 bit 7:6 adcs1:adcs0 : a/d conversion clock select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from the internal a/d rc oscillator) bit 5:3 chs2:chs0 : analog channel select bits 000 = channel 0, (an0) 001 = channel 1, (an1) 010 = channel 2, (an2) 011 = channel 3, (an3) 100 = channel 4, (an4) 101 = channel 5, (an5) 110 = channel 6, (an6) 111 = channel 7, (an7) note: for devices that do not implement the full 8 a/d channels, the unimplemented selec- tions are reserved. do not select any unimplemented channel. bit 2 go/done : a/d conversion status bit when adon = 1 1 = a/d conversion in progress (setting this bit starts the a/d conversion which is automatically cleared by hardware when the a/d conversion is complete) 0 = a/d conversion not in progress bit 1 unimplemented: read as '0' bit 0 adon : a/d on bit 1 = a/d converter module is powered up 0 = a/d converter module is shut off and consumes no operating current legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31023a-page 23-4 preliminary 1997 microchip technology inc. register 23-2: adcon1 register u-0 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7:6 unimplemented: read as '0' bit 5 adfm : a/d result format select (also see figure 23-6 ). 1 = right justi?d. 6 most signi?ant bits of adresh are read as ?? 0 = left justi?d. 6 least signi?ant bits of adresl are read as ?? bit 4 unimplemented: read as '0' bit 3:0 pcfg3:pcfg0 : a/d port con?uration control bits legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset a = analog input d = digital i/o c/r = # of analog input channels / # of a/d voltage references pcfg an7 an6 an5 an4 an3 an2 an1 an0 v ref +v ref - c / r 0000 aaaa a a aaav dd av ss 8 / 0 0001 aaaav ref + a a a an3 av ss 7 / 1 0010 ddd a a a aaav dd av ss 5 / 0 0011 ddd av ref + a a a an3 av ss 4 / 1 0100 dddd a d aaav dd av ss 3 / 0 0101 ddddv ref + d a a an3 av ss 2 / 1 011x d d d d d d d d 0 / 0 1000 aaaav ref +v ref - a a an3 an2 6 / 2 1001 dd a a a a aaav dd av ss 6 / 0 1010 dd a av ref + a a a an3 av ss 5 / 1 1011 dd a av ref +v ref - a a an3 an2 4 / 2 1100 ddd av ref +v ref - a a an3 an2 3 / 2 1101 ddddv ref +v ref - a a an3 an2 2 / 2 1110 dddd d d daav dd av ss 1 / 0 1111 ddddv ref +v ref - d a an3 an2 1 / 2 note 1: on any device reset, the port pins that are multiplexed with analog functions (anx) are forced to be an analog input.
1997 microchip technology inc. preliminary ds31023a-page 23-5 section 23. 10-bit a/d converter 10-bit a/d converter 23 23.3 operation the adresh:adresl registers contains the 10-bit result of the a/d conversion. when the a/d conversion is complete, the result is loaded into this a/d result register pair, the go/done bit (adcon0<2>) is cleared, and a/d interrupt ?g bit, adif, is set. the block diagrams of the a/d module are shown in figure 23-1 . after the a/d module has been con?ured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as inputs. to determine sample time, see subsection 23.4 ?/d acquisition requirements. after this acquisition time has elapsed the a/d conversion can be started. the following steps should be followed for doing an a/d conversion: 1. con?ure the a/d module: con?ure analog pins / voltage reference/ and digital i/o (adcon1) select a/d input channel (adcon0) select a/d conversion clock (adcon0) turn on a/d module (adcon0) 2. con?ure a/d interrupt (if desired): clear the adif bit set the adie bit set the gie bit 3. wait the required acquisition time. 4. start conversion: set the go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or adif bit to be set or waiting for the a/d interrupt 6. read a/d result register pair (adresh:adresl), clear the adif bit, if required. 7. for next conversion, go to step 1 or step 2 as required. figure 23-2 shows the conversion sequence, and the terms that are used. acquisition time is the time that the a/d modules holding capacitor is connected to the external voltage level. then there is the conversion time of 12 t ad , which is started when the go bit is set. the sum of these two times is the sampling time. there is a minimum acquisition time to ensure that the holding capacitor is charged to a level that will give the desired accuracy for the a/d conversion. figure 23-2: a/d conversion sequence acquisition time a/d conversion time a/d sample time when a/d holding capacitor starts to charge. after a/d conversion, or when new a/d channel is selected when a/d conversion is started (setting the go bit) a/d conversion complete, result is loaded in adres register. holding capacitor begins acquiring voltage level on selected channel adif bit is set
picmicro mid-range mcu family ds31023a-page 23-6 preliminary 1997 microchip technology inc. 23.4 a/d acquisition requirements for the a/d converter to meet its speci?d accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 23-3 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) imped- ance varies over the device voltage (v dd ), figure 23-3 . the maximum recommended imped- ance for analog sources is 10 k w . as the impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 23-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its speci?d resolution. equation 23-1: a cquisition time equation 23-2: a/d minimum charging time example 23-1 shows the calculation of the minimum required acquisition time t acq . this calculation is based on the following application system assumptions. c hold = 120 pf rs = 10 k w conversion error 1/2 lsb v dd = 5v ? rss = 7 k w (see graph in figure 23-3 ) temperature = 50 c (system max.) v hold = 0v @ time = 0 example 23-1: calculating the minimum required acquisition time (case 1) t acq = ampli?r settling time + holding capacitor charging time + temperature coef?ient =t amp + t c + t coff v hold = (v ref - (v ref /2048)) ? (1 - e (-tc/c hold (r ic + r ss + r s )) ) or tc = -(120 pf)(1 k w + r ss + r s ) ln(1/2047) t acq = t amp + t c + t coff temperature coef?ient is only required for temperatures > 25 c. t acq =2 m s + tc + [(temp - 25 c)(0.05 m s/ c)] t c =-c hold (r ic + r ss + r s ) ln(1/2047) -120 pf (1 k w + 7 k w + 10 k w ) ln(0.0004885) -120 pf (18 k w ) ln(0.0004885) -2.16 m s (-7.6241) 16.47 m s t acq =2 m s + 16.47 m s + [(50 c - 25 c)(0.05 m s/ c)] 18.47 m s + 1.25 m s 19.72 m s
1997 microchip technology inc. preliminary ds31023a-page 23-7 section 23. 10-bit a/d converter 10-bit a/d converter 23 now to get an idea what happens to the acquisition time when the source impedance is a mini- mal value ( r s = 50 w ). example 23-2 shows the same conditions as in example 23-1 with only the source impedance made a minimal value ( r s = 50 w ). example 23-2: calculating the minimum required acquisition time (case 2) figure 23-3: analog input model t acq = t amp + t c + t coff temperature coef?ient is only required for temperatures > 25 c. t acq =2 m s + tc + [(temp - 25 c)(0.05 m s/ c)] t c =-c hold (r ic + r ss + r s ) ln(1/2047) -120 pf (1 k w + 7 k w + 50 w ) ln(0.0004885) -120 pf (8050 w ) ln(0.0004885) -0.966 m s (-7.6241) 7.36 m s t acq =2 m s + 16.47 m s + [(50 c - 25 c)(0.05 m s/ c)] 9.36 m s + 1.25 m s 10.61 m s note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. note 2: the charge holding capacitor (c hold ) is not discharged after each conversion. note 3: the maximum recommended impedance for analog sources is 10 k w . this is required to meet the pin leakage speci?ation. note 4: after a conversion has completed, a 2.0t ad delay must complete before acquisition can begin again. during this time the holding capacitor is not connected to the selected a/d input channel. v ain c pin rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 120 pf v ss 6v sampling switch 5v 4v 3v 2v 5 6 7 8 9 10 11 ( k w ) v dd 100 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
picmicro mid-range mcu family ds31023a-page 23-8 preliminary 1997 microchip technology inc. 23.5 selecting the a/d conversion clock the a/d conversion time per bit is de?ed as t ad . the a/d conversion requires 11.5t ad per 10-bit conversion. the source of the a/d conversion clock is software selected. the four possible options for t ad are: ?t osc ?t osc 32t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a mini- mum t ad time of 1.6 m s as shown in parameter 130 of the ?lectrical speci?ations section. table 23-1 show the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. these times are for standard voltage range devices. table 23-1: t ad vs. device operating frequencies (for standard, c, devices) table 23-2: t ad vs. device operating frequencies (for extended, lc, devices) ad clock source (t ad ) device frequency operation adcs1:adcs0 20 mhz 5 mhz 1.25 mhz 333.33 khz 2t osc 00 100 ns (2) 400 ns (2) 1.6 m s6 m s 8t osc 01 400 ns (2) 1.6 m s 6.4 m s 24 m s (3) 32t osc 10 1.6 m s 6.4 m s 25.6 m s (3) 96 m s (3) rc 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1) legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 4 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion, or the a/d accuracy may be out of speci?ation. ad clock source (t ad ) device frequency operation adcs1:adcs0 4 mhz 2 mhz 1.25 mhz 333.33 khz 2t osc 00 500 ns (2) 1.0 m s (2) 1.6 m s (2) 6 m s 8t osc 01 2.0 m s (2) 4.0 m s 6.4 m s 24 m s (3) 32t osc 10 8.0 m s 16.0 m s 25.6 m s (3) 96 m s (3) rc 11 3 - 9 m s (1,4) 3 - 9 m s (1,4) 3 - 9 m s (1,4) 3 - 9 m s (1,4) legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 6 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion, or the a/d accuracy may be out of speci?ation.
1997 microchip technology inc. preliminary ds31023a-page 23-9 section 23. 10-bit a/d converter 10-bit a/d converter 23 23.6 configuring analog port pins the adcon1 and tris registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. note 1: when reading the port register, any pin con?ured as an analog input channel will read as cleared (a low level). pins con?ured as digital inputs, will convert an analog input. analog levels on a digitally con?ured input will not affect the conversion accuracy. note 2: analog levels on any pin that is de?ed as a digital input (including the an7:an0 pins), may cause the input buffer to consume current that is out of the devices spec- i?ation.
picmicro mid-range mcu family ds31023a-page 23-10 preliminary 1997 microchip technology inc. 23.7 a/d conversions example 23-3 shows how to perform an a/d conversion for the pic17c756. the portf and lower four portg pins are con?ured as analog inputs. the analog references (v ref + and v ref -) are the device av dd and av ss . the a/d interrupt is enabled, and the a/d conversion clock is f rc . the conversion is performed on the an0 pin (channel 0). clearing the go/done bit during a conversion will abort the current conversion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. that is, the adresh:adresl registers will continue to contain the value of the last completed conver- sion (or the last value written to the adresh:adresl registers). after the a/d conversion is aborted, a 2t ad wait is required before the next acquisition is started. after this 2t ad wait, acqui- sition on the selected channel is automatically started. example 23-3: a/d conversion figure 23-4: a/d conversion t ad cycles note: the go/done bit should not be set in the same instruction that turns on the a/d, due to the required acquisition time requirement. bsf status, rp0 ; select bank1 clrf adcon1 ; configure a/d inputs, ; result is left justified bsf pie1, adie ; enable a/d interrupts bcf status, rp0 ; select bank0 movlw 0xc1 ; rc clock, a/d is on, channel 0 is selected movwf adcon0 ; bcf pir1, adif ; clear a/d interrupt flag bit bsf intcon, peie ; enable peripheral interrupts bsf intcon, gie ; enable all interrupts ; ; ensure that the required sampling time for the selected input ; channel has elapsed. then the conversion may be started. ; bsf adcon0, go ; start a/d conversion : ; the adif bit will be set and the go/done : ; bit is cleared upon completion of the : ; a/d conversion. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) holding capacitor is connected to analog input. b9 b8 b7 b6 b5 b4 b3 b2 t ad 9 t ad 10 b1 b0 tcy - t ad go bit is cleared, next q4: adres is loaded, adif bit is set, conversion starts b0
1997 microchip technology inc. preliminary ds31023a-page 23-11 section 23. 10-bit a/d converter 10-bit a/d converter 23 figure 23-5: flowchart of a/d operation acquire adon = 0 adon = 0? go = 0? a/d clock go = 0, adif = 0 abort conversion sleep power-down a/d wait 2t ad wake-up ye s no ye s no no ye s finish conversion go = 0, adif = 1 device in no ye s finish conversion go = 0, adif = 1 wait 2t ad stay in sleep selected channel = rc? sleep no ye s instruction? start of a/d conversion delayed 1 instruction cycle from sleep? power-down a/d ye s no wait 2t ad finish conversion go = 0, adif = 1 sleep?
picmicro mid-range mcu family ds31023a-page 23-12 preliminary 1997 microchip technology inc. 23.7.1 faster conversion - lower resolution trade-off not all applications require a result with 10-bits of resolution, but may instead require a faster conversion time. the a/d module allows users to make the trade-off of conversion speed to res- olution. regardless of the resolution required, the acquisition time is the same. to speed up the conversion, the clock source of the a/d module may be switched so that the t ad time violates the minimum speci?d time (see the applicable electrical speci?ation). once the t ad time vio- lates the minimum speci?d time, all the following a/d result bits are not valid (see a/d conver- sion timing in the electrical speci?ations section). the clock sources may only be switched between the three oscillator versions (cannot be switched from/to rc). the equation to deter- mine the time before the oscillator can be switched is as follows: conversion time = t ad + n ?t ad + (11 - n)(2t osc ) where: n = number of bits of resolution required. since the t ad is based from the device oscillator, the user must use some method (a timer, soft- ware loop, etc.) to determine when the a/d oscillator may be changed. example 23-4 shows a comparison of time required for a conversion with 4-bits of resolution, versus the 10-bit resolution conversion. the example is for devices operating at 20 mhz (the a/d clock is programmed for 32t osc ), and assumes that immediately after 6t ad , the a/d clock is programmed for 2t osc . the 2t osc violates the minimum t ad time since the last 4 bits will not be converted to correct values. example 23-4: 4-bit vs. 8-bit conversion times freq. (mhz) (1) resolution 4-bit 10-bit t ad 20 1.6 m s 1.6 m s t osc 20 50 ns 50 ns 2t ad + n ?t ad + (11 - n)(2t osc ) 20 8.7 m s 17.6 m s note 1: a minimum t ad time of 1.6 m s is required. 2: if the full 8-bit conversion is required, the a/d clock source should not be changed.
1997 microchip technology inc. preliminary ds31023a-page 23-13 section 23. 10-bit a/d converter 10-bit a/d converter 23 23.7.2 a/d result registers the adresh:adresl register pair is the location where the 10-bit a/d result is loaded at the completion of the a/d conversion. this register pair is 16-bits wide. the a/d module gives the ?xibility to left or right justify the 10-bit result in the 16-bit result register. the a/d format select bit (adfm) controls this justi?ation. figure 23-6 shows the operation of the a/d result justi?a- tion. the extra bits are loaded with ?s? when an a/d result will not overwrite these locations (a/d disable), these registers may be used as two general purpose 8-bit registers. figure 23-6: a/d result justi?ation 10-bit result adresh adresl 0000 00 adfm = 0 0 2 1 0 7 7 10-bits result adresh adresl 10-bits 0000 00 7 0 7 6 5 0 result adfm = 1 right justi?d left justi?d
picmicro mid-range mcu family ds31023a-page 23-14 preliminary 1997 microchip technology inc. 23.8 operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs1:adcs0 = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all internal digital switching noise from the conversion. when the conversion is completed the go/done bit will be cleared, and the result is loaded into the adres register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d module will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conversion to be aborted and the a/d module to be turned off (to conserve power), though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 23.9 effects of a reset a device reset forces all registers to their reset state. this forces the a/d module to be turned off, and any conversion is aborted. the value that is in the adresh:adresl registers is not modi?d for a power-on reset. the adresh:adresl registers will contain unknown data after a power-on reset. note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs1:adcs0 = 11 ). to allow the conversion to occur during sleep, ensure the sleep instruction immediately follows the instruction that sets the go/done bit.
1997 microchip technology inc. preliminary ds31023a-page 23-15 section 23. 10-bit a/d converter 10-bit a/d converter 23 23.10 a/d accuracy/error in systems where the device frequency is low, use of the a/d rc clock is preferred. at moderate to high frequencies, t ad should be derived from the device oscillator. the absolute accuracy speci?d for the a/d converter includes the sum of all contributions for quantization error, integral error, differential error, full scale error, offset error, and monotonicity. it is de?ed as the maximum deviation from an actual transition versus an ideal transition for any code. the absolute error of the a/d converter is speci?d at < 1 lsb for v dd = v ref (over the devices speci?d operating range). however, the accuracy of the a/d converter will degrade as v dd diverges from v ref . for a given range of analog inputs, the output digital code will be the same. this is due to the quantization of the analog input to a digital code. quantization error is typically 1/2 lsb and is inherent in the analog to digital conversion process. the only way to reduce quantization error is to increase the resolution of the a/d converter. offset error measures the ?st actual transition of a code versus the ?st ideal transition of a code. offset error shifts the entire transfer function. offset error can be calibrated out of a system or introduced into a system through the interaction of the total leakage current and source imped- ance at the analog input. gain error measures the maximum deviation of the last actual transition and the last ideal tran- sition adjusted for offset error. this error appears as a change in slope of the transfer function. the difference in gain error to full scale error is that full scale does not take offset error into account. gain error can be calibrated out in software. linearity error refers to the uniformity of the code changes. linearity errors cannot be calibrated out of the system. integral non-linearity error measures the actual code transition versus the ideal code transition adjusted by the gain error for each code. differential non-linearity measures the maximum actual code width versus the ideal code width. this measure is unadjusted. the maximum pin leakage current is speci?d in the device data sheet electrical speci?ation parameter d060 . in systems where the device frequency is low, use of the a/d rc clock is preferred. at moderate to high frequencies, t ad should be derived from the device oscillator. t ad must not violate the minimum and should be minimized to reduce inaccuracies due to noise and sampling capacitor bleed off. in systems where the device will enter sleep mode after the start of the a/d conversion, the rc clock source selection is required. in this mode, the digital noise from the modules in sleep are stopped. this method gives high accuracy.
picmicro mid-range mcu family ds31023a-page 23-16 preliminary 1997 microchip technology inc. 23.11 connection considerations if the input voltage exceeds the rail values (v ss or v dd ) by greater than 0.3v, then the accuracy of the conversion is out of speci?ation. an external rc ?ter is sometimes added for anti-aliasing of the input signal. the r component should be selected to ensure that the total source impedance is kept under the 10 k w recom- mended speci?ation. any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. 23.12 transfer function the ideal transfer function of the a/d converter is as follows: the ?st transition occurs when the analog input voltage (v ain ) is 1 lsb (or analog v ref / 1024) ( figure 23-7 ). figure 23-7: a/d transfer function digital code output 3feh 003h 002h 001h 000h 0.5 lsb 1 lsb 1.5 lsb 2 lsb 2.5 lsb 1022 lsb 1022.5 lsb 3 lsb analog input voltage 3ffh 1023 lsb 1023.5 lsb
1997 microchip technology inc. preliminary ds31023a-page 23-17 section 23. 10-bit a/d converter 10-bit a/d converter 23 23.13 initialization example 23-5 shows an initialization of the a/d module. example 23-5: a/d initialization bsf status, rp0 ; select bank1 clrf adcon1 ; configure a/d inputs bsf pie1, adie ; enable a/d interrupts bcf status, rp0 ; select bank0 movlw 0xc1 ; rc clock, a/d is on, channel 0 is selected movwf adcon0 ; bcf pir1, adif ; clear a/d interrupt flag bit bsf intcon, peie ; enable peripheral interrupts bsf intcon, gie ; enable all interrupts ; ; ensure that the required sampling time for the selected input ; channel has elapsed. then the conversion may be started. ; bsf adcon0, go ; start a/d conversion : ; the adif bit will be set and the go/done : ; bit is cleared upon completion of the : ; a/d conversion.
picmicro mid-range mcu family ds31023a-page 23-18 preliminary 1997 microchip technology inc. 23.14 design tips question 1: i ?d that the analog to digital converter result is not always accurate. what can i do to improve accuracy? answer 1: 1. make sure you are meeting all of the timing speci?ations. if you are turning the module off and on, there is a minimum delay you must wait before taking a sample. if you are changing input channels, there is a minimum delay you must wait for this as well, and ?ally there is t ad , which is the time selected for each bit conversion. this is selected in adcon0 and should be between 1.6 and 6 m s. if t ad is too short, the result may not be fully converted before the conversion is terminated, and if t ad is made too long the voltage on the sampling capacitor can droop before the conversion is complete. these timing speci?ations are provided in the ?lectrical speci?ations section. see the device data sheet for device speci? information. 2. often the source impedance of the analog signal is high (greater than 1k ohms) so the current drawn from the source to charge the sample capacitor can affect accuracy. if the input signal does not change too quickly, try putting a 0.1 m f capacitor on the analog input. this capacitor will charge to the analog voltage being sampled and supply the instanta- neous current needed to charge the 120 pf internal holding capacitor. 3. finally, straight from the data book: ?n systems where the device frequency is low, use of the a/d clock derived from the device oscillator is preferred...this reduces, to a large extent, the effects of digital switching noise. and ?n systems where the device will enter sleep mode after start of a/d conversion, the rc clock source selection is required.this method gives the highest accuracy. question 2: after starting an a/d conversion may i change the input channel (for my next conversion)? answer 2: after the holding capacitor is disconnected from the input channel, typically 100 ns after the go bit is set, the input channel may be changed. question 3: do you know of a good reference on a/ds? answer 3: a very good reference for understanding a/d conversions is the ?nalog-digital conversion handbook third edition, published by prentice hall (isbn 0-13-03-2848-0).
1997 microchip technology inc. preliminary ds31023a-page 23-19 section 23. 10-bit a/d converter 10-bit a/d converter 23 23.15 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the 10-bit a/d module are: title application note # using the analog to digital converter an546 four channel digital voltmeter with display and keyboard an557
picmicro mid-range mcu family ds31023a-page 23-20 1997 microchip technology inc. 23.16 revision history revision a this is the initial released revision of the 10-bit a/d module description.
1997 microchip technology inc. ds31024a page 24-1 m slope a/d 24 section 24. slope a/d highlights this section of the manual contains the following major topics: 24.1 introduction ............................................................................................................... ...24-2 24.2 control registers .........................................................................................................2 4-3 24.3 conversion process .....................................................................................................24-6 24.4 other analog modules ...............................................................................................24-12 24.5 calibration parameters ..............................................................................................24-13 24.6 design tips ................................................................................................................ 24-14 24.7 related application notes..........................................................................................24-15 24.8 revision history .........................................................................................................24 -16
picmicro mid-range mcu family ds31024a-page 24-2 1997 microchip technology inc. 24.1 introduction the components required to create a slope a/d converter include: precision comparator 4-bit programmable current source 16-channel analog mux 16-bit timer with capture register this section will discuss using these components for a slope a/d. each analog input channel is multiplexed to a single analog input source to be converted by means of a slope conversion method (using a single precision comparator). the programmable current source feeds an external capacitor to generate the ramp voltage used in the conversion. figure 24-1: slope a/d block diagram adoff osc1 1 0 fosc (con?uration bit) internal adtmrh adtmrl clock stop logic timer adcaph adcapl oscillator analog mux an12 7 6 5 4 3 2 1 0 an11 sreflo srefhi an2 an1 an0 slope a/d capture slope a/d capture interrupt (adcif) adoff cdac ~2.5ua~5ua~10ua~20ua adcon1<7:4> adrst (adcon0<1>) an3 8 ~100 w adoff bandgap ref. an13 9 ~ 1 k w an4 an5 an6 an7 10 11 12 13 an14 an15 14 15 amuxoe over?w internal data bus adrst 4 note 2 note 1: all current sources are disabled if adrst = ? 2: approximately 3.5 microsecond time constant 3: dependent on a/d resolution and input voltage range (see table 24-2 ) 4-bit current dac (note 1) adcon0<7:4> (slpcon<0>) (adcon0<2>) an0 note 3 c
1997 microchip technology inc. ds31024a-page 24-3 section 24. slope a/d slope a/d 24 24.2 control registers two a/d control registers are provided to control the conversion process. they are adcon0 and adcon1. both registers are readable and writable. register 24-1: adcon0 register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-1 r/w-0 adcs3 adcs2 adcs1 adcs0 amuxoe adrst adzero bit 7 bit 0 bit 7-4: adcs3:adcs0 : analog channel select bits 0000 = an0 input 0001 = an1 input 0010 = an2 input 0011 = an3 input 0100 = bandgap reference voltage input 0101 = slope reference srefhi input 0110 = slope reference sreflo input 0111 = an11 input 1000 = an12 input 1001 = an13 input 1010 = an4 input 1011 = an5 input 1100 = an6 input 1101 = an7 input 1110 = an14 input 1111 = an15 input note: for devices that do not use the full 16 a/d input channels, the unimplemented selec- tions are reserved. do not select any unimplemented channels. bit 3: unimplemented: read as '0' bit 2: amuxoe: analog mux output enable 1 = connect amux output to an0 pin (overrides tris setting) 0 = an0 pin normal bit 1: adrst: a/d reset control bit 1 = stop the a/d timer, discharge cdac capacitor 0 = normal operation (a/d running) bit 0: adzero : a/d zero select control 1 = enable zeroing operation on an1 and an5 0 = normal operation, sample an1 and an5 pins legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31024a-page 24-4 1997 microchip technology inc. register 24-2: adcon1 register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addac3 addac2 addac1 addac0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7-4: addac3:addac0 : programmable current source select bits 0000 = off - all current sources disabled 0001 = 2.25 m a 0010 = 4.5 m a 0011 = 6.75 m a 0100 = 9 m a 0101 = 11.25 m a 0110 = 13.5 m a 0111 = 15.75 m a 1000 = 18 m a 1001 = 20.25 m a 1010 = 22.5 m a 1011 = 24.75 m a 1100 = 27 m a 1101 = 29.25 m a 1110 = 31.5 m a 1111 = 33.75 m a bit 3-0: pcfg3:pcfg0 : port con?uration selects legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset a = analog input d = digital i/o pcfg3:pcfg2 an4 an5 an6 an7 00 aaaa 01 aaad 10 aadd 11 dddd pcfg1:pcfg0 an0 an1 an2 an3 00 aaaa 01 aaad 10 aadd 11 dddd note: on any device reset, all port pins multiplexed with analog functions (anx pins), are forced to be an analog input.
1997 microchip technology inc. ds31024a-page 24-5 section 24. slope a/d slope a/d 24 register 24-3: slpcon register r/w-0 u-0 r/w-1 r/w-1 u-1 r/w-1 r/w-1 r/w-1 resv refoff resv oscoff resv resv adoff bit 7 bit 0 bit 7: reserved: always maintain this bit cleared. bit 6: unimplemented: read as '0' bit 5: refoff: slope a/d voltage reference power control bit 1 = voltage references are disabled (not consuming current) 0 = voltage references are powered (consuming current) bit 4: reserved: always maintain this bit cleared. bit 3: oscoff: slope a/d oscillator sleep control bit 1 = slope a/d oscillator is disabled during sleep mode (not consuming current) 0 = slope a/d oscillator is enabled during sleep mode (consuming current) bit 2: reserved: always maintain this bit cleared. bit 1: reserved: always maintain this bit cleared. bit 0: adoff: slope a/d power control bit 1 = slope a/d is disabled (not consuming current) 0 = slope a/d is powered (consuming current) legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
picmicro mid-range mcu family ds31024a-page 24-6 1997 microchip technology inc. 24.3 conversion process there are two methods for performing a conversion. to determine the end of conversion, the ?st method uses the adtmr over?w interrupt (ovfif bit). the second method uses the a/d cap- ture interrupt (adcif bit). at the end of conversion both bits are used to determine if an over- range condition has occurred. method 1 uses a ?ed conversion time, this means that the capacitor voltage always ramps to the full scale voltage. immediately after the over?w of the adtmr, we recommend that the adrst bit is set to discharge the external capacitor. this will ensure that the residual voltage on the external capacitor, due to dielectric absorption, is independent of input voltage or previous conversions. method 2 uses a variable conversion time, which results in faster conversions for lower input volt- ages. steps for method 1 (xed conversion time?: 1. initialize the slope a/d module: a)clear the refoff bit (slpcon<5>) b)clear the adoff bit (slpcon<0>) c)initialize adcon1<7:4> to select the programmable current source. 2. set the adrst bit (adcon0<1>), until the ramp capacitor reaches ground. this is capac- itor dependent. a minimum of 200 m s is recommended. 3. select input channel 4. clear the ovfif and adcif bits. 5. initialize slope a/d timer (adtmr). adtmr value depends on bits of resolution required (see table 24-1 ). 6. to start a conversion, clear the adrst bit, this allows the ramp capacitor to begin charg- ing and the adtmr to increment. 7. conversion is complete when the slope a/d timer (adtmr) over?ws from ffffh to 0000h. this causes the ovfif bit to be set. 8. check if the adcif bit is set. if this bit is set, the value in the capture register adcap is valid. this method depends on minimum latency to verify the capture interrupt ?g bit after the adtmr over?ws. if the adcif bit is cleared, then the input voltage was out of the a/d input range. 9. set the adrst bit (adcon0<1>) to stop adtmr and discharge external capacitor 10. do conversion calculations 11. goto step 2
1997 microchip technology inc. ds31024a-page 24-7 section 24. slope a/d slope a/d 24 steps for method 2 (?ariable conversion time?: 1. initialize the slope a/d module: a)clear the refoff bit (slpcon<5>). b)clear the adoff bit (slpcon<0>). c)initialize adcon1<7:4> to select the programmable current source. 2. set the adrst bit (adcon0<1>), until the ramp capacitor reaches ground. this is capac- itor dependent. a minimum of 200 m s is recommended. 3. select input channel. 4. clear the ovfif and adcif bits. 5. initialize slope a/d timer (adtmr). adtmr value depends on bits of resolution required (see table 24-1 ). 6. to start a conversion, clear the adrst bit, this allows the ramp capacitor to begin charg- ing and the adtmr to increment. 7. conversion is complete when the ramp voltage exceeds the analog input so the compar- ator output changes from high to low. this causes the adcif bit to be set. 8. check if the adtmr did not increment more counts than the maximum resolution allowed. if there were more counts, then the input voltage was out of the a/d input range. 9. set the adrst bit (adcon0<1>) to stop adtmr and discharge external capacitor 10. do conversion calculations. 11. go to step 2. the maximum slope a/d timer count is 65,536. it can be clocked by the on-chip or external oscil- lator. at a 4 mhz oscillation frequency, the maximum conversion time is 16.38 ms for a full count. a typical conversion should complete before full-count is reached. the timer over?w ?g is set once the timer rolls over (ffffh to 0000h), and an interrupt occurs, if enabled. end-user calibration is simpli?d or eliminated by making use of the on-chip eprom. internal component values are measured at factory ?al test and stored in the memory for use by the application ?mware. periodic conversion cycles should be performed on the bandgap and slope references (described in subsection 24.4 ?ther analog modules ) to compensate for slope a/d compo- nent drift. measurements for the reference voltage counts are equated to the voltage value stored into eprom during calibration. since all measurements are relative to the reference, offset voltages inherent in the comparator are minimized. the slope a/d clock source does not require a precise frequency, only a stable frequency. see an624, ?ic14000 slope a/d theory and implementation for further details of slope a/d operation. note: the slope a/d timer continues to run following a capture event.
picmicro mid-range mcu family ds31024a-page 24-8 1997 microchip technology inc. 24.3.1 slope a/d timer (adtmr) the slope a/d timer (adtmr) is comprised of a 16-bit timer (adtmrh:adtmrl), which is incremented every oscillator cycle. the adtmr registers are cleared by a power-on reset; oth- erwise the software must initialize it after each conversion. a separate 16-bit capture register (adcaph:adcapl) is used to capture the adtmr count if a slope a/d capture event occurs (see below). both the slope a/d timer and capture registers are readable and writable. the 16-bit timer is a read/write register and is cleared on any device reset. during a conversion one or both of the following events will occur: capture event timer over?w in a capture event, the comparator trips when the slope voltage on the cdac output exceeds the input voltage from the selected slope a/d channel, causing the comparator output to transition from high to low. this causes a transfer of the current timer count to the capture register and sets the adcif ?g bit. an interrupt will be generated if the adcie bit is set (interrupt enabled). in addition, gie and pie bits must be set. software is responsible for clearing the adcif ?g bit prior to the next conver- sion cycle. this interrupt can only occur once per conversion cycle. in a timer over?w condition, the timer rolls over from ffffh to 0000h, and a capture over?w ?g (ovfif) is asserted. the timer continues to increment following a timer over?w. an interrupt can be generated if bit ovfie is set (interrupt enabled). in addition, the gie and pie bits must be set. software is responsible for clearing the ovfif ?g bit prior to the next conversion cycle. figure 24-2: example slope a/d conversion cycle note 1: reading or writing the adtmr register during an slope a/d conversion cycle can produce unpredictable results and is not recommended. note 2: the correct sequence for writing the adtmr register is hi byte followed by lo byte. reversing this order will prevent the slope a/d timer from running. xx capture clk adrst adcon0<1> capture register cdac xx+8 compare adcif (must be cleared by software) adtmr increments xx+1 xx+2 xx+3 adtmr count xx+8 xx+9 xx
1997 microchip technology inc. ds31024a-page 24-9 section 24. slope a/d slope a/d 24 24.3.2 sleep operation the slope a/d may operate when the device is in sleep mode. for the slope a/d to do a con- version during sleep mode, the slope a/d module must have a device clock. for a clock to be present the oscoff bit must be cleared before going to sleep. also the refoff and adoff bits must be cleared to ensure that the results re?ct the voltage on the input channel. by doing an a/d conversion during sleep mode, the result has improved accuracy due to a reduction of system noise. when the device clock is disabled, the slope a/d timer (adtmrh:adtmrl) stops increment- ing. even if the slope a/d module is not disabled, the slope a/d cannot wake-up the device. this is because the adcif bit cannot be set, which is one of the control bits used to wake the device from sleep mode. when the device awakes, if the comparator value has tripped, the capture and interrupt will occur. the value in the adcap registers is meaningless. for maximum power savings, all analog components of the slope a/d module should be disabled (no conversion in progress). 24.3.3 effects of a reset after any device reset, the slope a/d module is disabled (lowest current state) and the device i/o are con?ured as analog channels. 24.3.4 slope a/d comparator this module includes a high gain comparator for slope a/d conversions. the non-inverting input terminal of the slope a/d comparator is connected to the output of an analog mux through an rc low-pass ?ter. the inverting input terminal is connected to the external ramp capacitor. the output of the comparator is used to cause the capture event to occur. this causes the value in the adtmr registers to be loaded into the adcap registers. this output will also cause the adcif bit to be set. 24.3.5 analog mux a total of 16 channels are internally multiplexed to the single slope a/d comparator positive input. four con?uration bits (adcon0<7:4>) select the channel to be converted. 24.3.6 programmable current source four con?uration bits (adcon1<7:4>) are used to control a programmable current source for generating the ramp voltage to the slope a/d comparator. this allows compensation for full-scale input voltage, clock frequency and the external capacitor tolerance variations. setting the adrst bit disconnects the current source from the cdac pin. current ?w begins when the adrst bit is cleared. the programmable current source output is tied to the cdac pin. this current source is used to charge an external capacitor, which generates the ramp voltage for the slope a/d comparator ( figure 24-1 ).
picmicro mid-range mcu family ds31024a-page 24-10 1997 microchip technology inc. 24.3.7 slope a/d resolution, speed, voltage range, and capacitor selection the slope a/d module allows many trade-offs. for a conversion the user needs to make the fol- lowing trade-offs: the resolution of the result the speed of the conversion the analog input voltage range the external capacitor the resolution is the number of bits that is used by the adtmr to represent the measured input voltage. this resolution affects the time that the conversion can be completed in. table 24-1 shows the trade-off between the resolution of the conversion and the maximum conversion time. the conversion time for the slope a/d converter can be calculated using the equation: conversion time = (1/fosc) x 2 n where fosc is the oscillator frequency and n is the number of bits of resolution desired. therefore at 4 mhz, the conversion time for 16 bits is 16.384 msec. conversely, it is 256 m sec for 10-bits. table 24-1: adtmr initialization values and conversion times resolution bits value loaded into adtmr maximum conversion time cycles 20 mhz 4 mhz 16 0000h 65536 t osc 3.28 ms 16.38 ms 15 8000h 32768 t osc 1.64 ms 8.2 ms 14 c000h 16384 t osc 820 m s 4.1 ms 13 e000h 8192 t osc 410 m s 2.05 ms 12 f000h 4096 t osc 204.8 m s 1.03 ms 11 f800h 2048 t osc 102.4 m s 500 m s 10 fc00h 1024 t osc 51.2 m s 250 m s .
1997 microchip technology inc. ds31024a-page 24-11 section 24. slope a/d slope a/d 24 the selection of the external capacitor is determined by the desired characteristics of the appli- cation. these include input voltage range (widest range of all input channels) conversion time programmable current source output values the selection of these values should be done to minimize the time between a comparator trip (adcif bit is set) to the adtmr over?w (ovfif is set). this ensures that the entire range of the adtmr is used for the a/d conversion process. the equation for selecting the ramp capacitor value is: capacitor = (conversion time in seconds) x (current source output in amps) / (full scale in volts) table 24-2 provides example capacitor values for the desired slope a/d resolution, conversion time, and full scale voltage measurement. this capacitor on the cdac pin should have a low voltage-coef?ient as found in te?n, polypro- pylene, or polystyrene capacitors, for optimum results. this external capacitor must be dis- charged at the beginning of each conversion cycle by setting the adrst bit (adcon0<1>). the time for the adrst bit to be set depends on the characteristics of the external capacitor for a complete discharge. table 24-2: external capacitor selection (@ 4 mhz) slope a/d resolution (bits) conversion time (ms) full scale (volts) slope a/d current source select calculated cdac capacitor cdac capacitor nearest standard value addac3:addc0 typical output ( m amps) 16 16.384 3.5 1100 27 0.126 m f 0.12 m f 2.0 1010 22.5 0.184 m f 0.18 m f 1.5 1011 24.75 0.270 m f 0.27 m f 14 4.096 3.5 1101 29.25 34 nf 33 nf 2.0 1011 24.75 50.7 nf 47 nf 1.5 1100 27 73.7 nf 68 nf 12 1.024 3.5 1101 29.25 8.56 nf 8.2 nf 2.0 1001 20.25 10.4 nf 10 nf 1.5 1010 22.5 15.4 nf 15 nf 10 0.256 3.5 1011 24.75 1.81 nf 1.8 nf 2.0 1010 22.5 2.88 nf 2.7 nf 1.5 1011 24.75 4.22 nf 3.9 nf .
picmicro mid-range mcu family ds31024a-page 24-12 1997 microchip technology inc. 24.4 other analog modules additional analog modules for mixed signal applications are required. these include: bandgap voltage reference slope reference voltage divider 24.4.1 bandgap voltage reference the bandgap reference circuit is used to generate a 1.2v nominal stable voltage reference for the slope a/d, the low-voltage detector, and the slope reference divider. the bandgap reference voltage is available on the analog mux. to enable the bandgap reference refoff (slp- con<5>) must be cleared. the bandgap reference must be enabled for any slope a/d conver- sion. the bandgap reference calibration factor is stored in the calibration space eprom. 24.4.2 slope reference voltage divider the slope reference voltage divider circuit, consisting of a buffer ampli?r and resistor divider, is connected to the internal bandgap reference producing two other voltage references called srefhi and sreflo (see figure 24-3 ). srefhi is nominally the same as the bandgap voltage, 1.2v, and sreflo is nominally 0.13v. these reference voltages are available on two of the ana- log multiplexer channels. the slope a/d module and ?mware can measure the srefhi and sreflo voltages, and in conjunction with the k ref and k bg calibration data correct for the adc's offset and slope errors. see an624 for further details. figure 24-3: slope reference divider + bandgap reference _ refoff (slpcon<5>) adoff (slpcon<0>) srefhi sreflo v ref to slope a/d mux sreflo srefhi ~ 9 sreflo srefhi - sreflo k ref =
1997 microchip technology inc. ds31024a-page 24-13 section 24. slope a/d slope a/d 24 24.5 calibration parameters the slope a/d module has several analog components. like all cmos circuitry the parametric values vary with process, temperature, voltage, and time. devices have been designed to mini- mize the effect of these variations. in addition, each device, with the slope a/d module, is cali- brated at factory test by measuring several key parameters and storing these values into eprom at speci?d locations. the customers application program may access this data and use it to mathematically compensate for device variations. collectively, these data values are referred to as calibration constants. the calibration constants are listed in table 24-3 . the 32-bit ?ating point representation has an exponent byte, and three bytes of mantissa. for information on ?ating point algorithms, refer to an575. table 24-3: calibration constants for additional information on using the calibration parameters see application note 624. 24.5.1 using calibration data the calibration constants should be used by the application ?mware to obtain the best accuracy. k ref and k bg are used in a/d conversions. 24.5.2 parameter variation table 24-4 lists the ?aximum parameter variation attainable when the calibration data is not used as well as the ?xpected parameter variation with calibration. if the accuracies without calibration are adequate for the task at hand, no further calibrations of the module are necessary. if greater accuracy is needed, the calibration constants must be used. table 24-4: parameter variation 24.5.3 device programming 24.5.3.1 non-windowed parts non-windowed parts are programmed just like any pic16cxxx processor. the calibration area is write-protected during factory calibration. 24.5.3.2 windowed parts calibration data must be read out and saved before erasing a windowed part. there is no way to recreate these values, so if they are lost the part can no longer be calibrated. parameter symbol number of bytes representation of value a/d slope reference ratio k ref 4 32-bit floating point bandgap reference voltage k bg 4 32-bit floating point symbol parameter maximum variation without calibration achievable variation with calibration k ref a/d slope reference ratio +/- 2.2% +/- 0.13% k bg bandgap reference voltage +/- 4.2% +/- 0.058% caution: windowed parts must not be write-protected. if the parts are erased by ultraviolet light, the calibration parameters are lost and cannot be reprogrammed once the part has been write-protected.
picmicro mid-range mcu family ds31024a-page 24-14 1997 microchip technology inc. 24.6 design tips question 1: what are some recommended capacitor types? answer 1: polypropylene ?m capacitor is a good trade-off between cost, availability and performance question 2: can you suggest some sources for capacitors answer 2: a source is: southern electronics company telephone: (203) 876-7488 question 3: i used the recommended capacitor and programmable current source from table 24-2 , and my a/d input range does not match. answer 3: that table is meant to be a good starting point, but does not include variation that is the result of the device not operating at exactly 4 mhz; tolerance of the external capacitor and variations of the programmable current source, due to process and application temperature. a conversion on the bandgap reference can be used to judge how to adjust the programmable current source output to ensure proper a/d full scale conversions. example code (routine ad_optimize, in p14_rv10.asm) for this adjustment is available with the picdem-14a demo board, and may be also available on the microchip web site. question 4: i am using the pic14c000 which also has the on-chip temperature sensor. the sensor results seem to be a little high. answer 4: this may be caused by self heating of the die. self heating of the die may be caused by a few things, including: i/o sinking and/or sourcing signi?ant amount of current power dissipation of the device running (remember the pic14c000 can operate in sleep mode) package type due to junction to ambient temperature coef?ient of package for best results the power dissipation should be kept low. calibration is performed with the device in a low power state. question 5: my a/d conversion results seem affected by the operation of high current components on my board. what can i do to minimize this? answer 5: the high current components on your board may cause the ground potential difference across the ground trace or ground plane. to minimize this effect, you should employ two system grounds on the application board. the ?st ground, analog ground, used for the reference analog signals (slope a/d external capacitor ground, resistor divider ground, and etc.). no high current nor any digital power returns should go through this analog ground system. the second ground, digital ground, is used for all other digital logic in the system. the applica- tions digital logic will inject noise onto this ground. proper grounding techniques should be used to minimize this noise. these two grounds are connected at the picmicros ground pin. ideally the two grounds are implemented using separate ground planes. in most cases, this can still be implemented on a two layer board. one layer is used for both ground systems, where the two planes are separated by a gap. the second layer is used as the trace layer.
1997 microchip technology inc. ds31024a-page 24-15 section 24. slope a/d slope a/d 24 24.7 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the slope a/d are: title application note # pic14c000 calibration parameters an621 pic14c000 a/d theory and implementation an624 lead acid battery charger implementation using the pic14c000 an626
picmicro mid-range mcu family ds31024a-page 24-16 1997 microchip technology inc. 24.8 revision history revision a this is the initial released revision of the slope a/d module description.
1997 microchip technology inc. ds31025a page 25-1 m lcd 25 section 25. lcd highlights this section of the manual contains the following major topics: 25.1 introduction ............................................................................................................... ...25-2 25.2 control register ........................................................................................................... 25-3 25.3 lcd timing ................................................................................................................. .25-6 25.4 lcd interrupts............................................................................................................2 5-12 25.5 pixel control.............................................................................................................. .25-13 25.6 voltage generation ....................................................................................................25-15 25.7 operation during sleep .............................................................................................25-16 25.8 effects of a reset.......................................................................................................25 -17 25.9 con?uring the lcd module......................................................................................25-17 25.10 discrimination ratio ...................................................................................................25- 18 25.11 lcd voltage generation ............................................................................................25-20 25.12 contrast .................................................................................................................. ...25-22 25.13 lcd glass................................................................................................................. .25-22 25.14 initialization ............................................................................................................ ....25-23 25.15 design tips ............................................................................................................... .25-24 25.16 related application notes..........................................................................................25-25 25.17 revision history .........................................................................................................2 5-26
picmicro mid-range mcu family ds31025a-page 25-2 1997 microchip technology inc. 25.1 introduction the lcd module generates the timing control to drive a static or multiplexed lcd panel, with support for up to 32 segments multiplexed with up to four commons. it also provides control of the lcd pixel data. the interface to the module consists of three control registers (lcdcon, lcdse, and lcdps) used to de?e the timing requirements of the lcd panel and up to 16 lcd data registers (lcd00-lcd15) that represent the array of the pixel data. in normal operation, the control regis- ters are con?ured to match the lcd panel being used. primarily, the initialization information consists of selecting the number of commons and segments required by the lcd panel, and then specifying the lcd frame clock rate to be used by the panel. once the module is initialized for the lcd panel, the individual bits of the lcd data registers are cleared/set to represent a turned-on pixel respectively. once the module is con?ured, the lcden bit (lcdcon<7>) is used to enable or disable the lcd module. the lcd panel can also operate during sleep by clearing the slpen bit (lcdcon<6>). figure 25-1: lcd module block diagram com3:com0 32 x 4 clock source timing control data bus select and divide internal rc osc fosc/4 t1cki ram 128 to 32 mux seg<31:0> to i/o pads to i/o pads lcdcon lcdps lcdse lcd
1997 microchip technology inc. ds31025a-page 25-3 section 25. lcd lcd 25 25.2 control register register 25-1: lcdcon register r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lcden slpen vgen cs1 cs0 lmux1 lmux0 bit 7 bit 0 bit 7 lcden : module drive enable bit 1 = lcd drive enabled 0 = lcd drive disabled bit 6 slpen : lcd display sleep enable bit 1 = lcd module will stop operating during sleep 0 = lcd module will continue to display during sleep bit 5 unimplemented : read as '0' bit 4 vgen : voltage generator enable bit 1 = internal lcd voltage generator enabled, (powered-up) 0 = internal lcd voltage generator powered-down, voltage is expected to be provided externally bit 3:2 cs1:cs0 : clock source select bits 00 = fosc/256 01 = t1cki (timer1) 1x = internal rc oscillator bit 1:0 lmux1:lmux0 : common selection bits speci?s the number of commons and the bias method legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset lmux1:lmux0 multiplex bias max # of segments 00 01 10 11 static (com0) 1/2 (com0, 1) 1/3 (com0, 1, 2) 1/4 (com0, 1, 2, 3) static 1/3 1/3 1/3 32 31 30 29
picmicro mid-range mcu family ds31025a-page 25-4 1997 microchip technology inc. register 25-2: lcdps register register 25-3: generic lcdd (pixel data) register layout u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x lp3 lp2 lp1 lp0 bit 7 bit 0 bit 7:4 unimplemented, read as '0' bit 3:0 lp3:lp0 : frame clock prescale selection bits legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset lmux1:lmux0 multiplex frame frequency = 00 static clock source / (128 * (lp3:lp0 + 1)) 01 1/2 clock source / (128 * (lp3:lp0 + 1)) 10 1/3 clock source / ( 96 * (lp3:lp0 + 1)) 11 1/4 clock source / (128 * (lp3:lp0 + 1)) r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x segs comc segs comc segs comc segs comc segs comc segs comc segs comc segs comc bit 7 bit 0 bit 7:0 segscomc : pixel data bit for segment s and common c 1 = pixel on (dark) 0 = pixel off (clear) legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset
1997 microchip technology inc. ds31025a-page 25-5 section 25. lcd lcd 25 register 25-4: lcdse register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 se29 se27 se20 se16 se12 se9 se5 se0 bit 7 bit 0 bit 7 se29 : pin function select bits for com1/seg31 - com3/seg29 1 = pins have lcd segment driver function 0 = pins have digital input function note: the lmux1:lmux0 setting takes precedence over the se29 bit, causing pins to become common drivers. bit 6 se27 : pin function select for seg28 and seg27 1 = pins have lcd segment driver function 0 = pins have digital input function bit 5 se20 : pin function select bits for seg26 - seg20 1 = pins have lcd segment driver function 0 = pins have digital input function bit 4 se16 : pin function select bits for seg19 - seg16 1 = pins have lcd segment driver function 0 = pins have digital input function bit 3 se12 : pin function select bits for seg15 - seg12 1 = pins have lcd segment driver function 0 = pins have digital input function bit 2 se9 : pin function select bits for seg11 - seg09 1 = pins have lcd segment driver function 0 = pins have digital input function bit 1 se5 : pin function select bits for seg08 - seg05 1 = pins have lcd segment driver function 0 = pins have digital input function bit 0 se0 : pin function select bits for seg04 - seg00 1 = pins have lcd segment driver function 0 = pins have digital i/o function legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset note: on a power-on reset, the lcd pins are con?ured for lcd drive function.
picmicro mid-range mcu family ds31025a-page 25-6 1997 microchip technology inc. 25.3 lcd timing the lcd module has 3 possible clock source inputs and supports static, 1/2, 1/3, and 1/4 multi- plexing. 25.3.1 timing clock source selection the clock sources for the lcd timing generation are: internal rc oscillator used for device low frequency or sleep operation timer1 oscillator used for device low frequency or sleep operation system clock divided by 256 the ?st timing source is an internal rc oscillator which runs at a nominal frequency of 14 khz. this oscillator provides a lower speed clock which may be used to continue running the lcd while the processor is in sleep. the rc oscillator will power-down when it is not selected or when the lcd module is disabled. the second source is the timer1 external oscillator. this oscillator provides a lower speed clock which may be used to continue running the lcd while the processor is in sleep. it is assumed that the frequency provided on this oscillator will be 32 khz. to use the timer1 oscillator as a lcd module clock source, it is only necessary to set the t1oscen (t1con<3>) bit. the third source is the system clock divided by 256. this divider ratio is chosen to provide about 32 khz output when the external oscillator is 8 mhz. the divider is not programmable. instead the lcdps register is used to set the lcd frame clock rate. the clock sources are selected with bits cs1:cs0 (lcdcon<3:2>). refer to figure 25-1 for details of the register programming. figure 25-2: lcd clock generation cs1:cs0 tmr1 32 khz crystal oscillator internal rc oscillator nominal f rc = 14 khz static 1/2 1/3 1/4 ? 4 ? 32 lmux1:lmux0 4-bit programmable lcdps<3:0> ? 1,2,3,4 ring counter lmux1:lmux0 internal data bus com2 ? 256 ? 2 f osc prescaler com0 com1 com3
1997 microchip technology inc. ds31025a-page 25-7 section 25. lcd lcd 25 25.3.2 multiplex timing generation the timing generation circuitry will generate 1 to 4 commons based on the display mode selected. the mode is speci?d by bits lmux1:lmux0 (lcdcon<1:0>). table 25-1 shows the formulas for calculating the frame frequency. table 25-1: frame frequency formulas table 25-2: approximate frame frequency in hz using timer1 @ 32.768 khz or fosc @ 8 mhz table 25-3: approximate frame frequency in hz using internal rc osc @ 14 khz multiplex frame frequency = static clock source / (128 * (lp3:lp0 + 1)) 1/2 clock source / (128 * (lp3:lp0 + 1)) 1/3 clock source / (96 * (lp3:lp0 + 1)) 1/4 clock source / (128 * (lp3:lp0 + 1)) lp3:lp0 static 1/2 1/3 1/4 2 85 85 114 85 3 64 648564 4 51 516851 5 43 435743 6 37 374937 7 32 324332 lp3:lp0 static 1/2 1/3 1/4 0 109 109 146 109 1 55 557355 2 36 364936 3 27 273627
picmicro mid-range mcu family ds31025a-page 25-8 1997 microchip technology inc. figure 25-3: static waveforms v 1 v 0 com0 seg0 com0-seg0 com0-seg1 seg1 v 1 v 0 v 1 v 0 v 0 v 1 -v 1 v 0 1 frame (selected pixel waveform) (non-selected pixel waveform) com0 seg7 seg6 seg5 seg1 seg2 seg3 seg4 seg0 liquid crystal display and terminal connection
1997 microchip technology inc. ds31025a-page 25-9 section 25. lcd lcd 25 figure 25-4: 1/2 mux, 1/3 bias waveform v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0-seg3 com0-seg1 1 frame (non-selected pixel waveform) com1 seg1 seg2 seg3 seg0 com0 liquid crystal display and terminal connection (selected pixel waveform) com0 com1 seg3 seg1
picmicro mid-range mcu family ds31025a-page 25-10 1997 microchip technology inc. figure 25-5: 1/3 mux, 1/3 bias waveform v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0 com1 com2 seg0 seg2 com0-seg0 com0-seg2 1 frame com2 seg2 seg0 com0 liquid crystal display and terminal connection com1 seg1 (non-selected pixel waveform) (selected pixel waveform)
1997 microchip technology inc. ds31025a-page 25-11 section 25. lcd lcd 25 figure 25-6: 1/4 mux, 1/3 bias waveform v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0 com1 com2 com3 seg0 seg1 com0-seg1 com0-seg0 1 frame com2 seg1 seg0 com0 liquid crystal display and terminal connection com3 com1 (selected pixel waveform) (non-selected pixel waveform)
picmicro mid-range mcu family ds31025a-page 25-12 1997 microchip technology inc. 25.4 lcd interrupts the lcd timing generation provides an interrupt that de?es the lcd frame timing. this interrupt can be used to coordinate the writing of the pixel data with the start of a new frame. writing pixel data at the frame boundary allows a visually crisp transition of the image. this interrupt can also be used to synchronize external events to the lcd. for example, the interface to an external seg- ment driver, such as a microchip ay0438, can be synchronized for segment data update to the lcd frame. a new frame is de?ed to begin at the leading edge of the com0 common signal. the interrupt will be set immediately after the lcd controller completes accessing all pixel data required for a frame. this will occur at a certain ?ed time before the frame boundary as shown in figure 25-7 . the lcd controller will begin to access data for the next frame within t fwr after the interrupt. figure 25-7: example waveforms in 1/4 mux drive com0 com1 com2 com3 v3 v2 v1 v0 v3 v2 v1 v0 v3 v2 v1 v0 v3 v2 v1 v0 frame boundary frame boundary 1 frame lcd interrupt occurs controller accesses next frame data t fint t fwr t fwr = t frame /(lmux1:lmux0 + 1) t fint = (t fwr /2 - (2t cy + 40 ns)) ? min. (t fwr /2 - (1t cy + 40 ns)) ? max.
1997 microchip technology inc. ds31025a-page 25-13 section 25. lcd lcd 25 25.5 pixel control 25.5.1 lcdd (pixel data) registers the pixel registers contain bits which de?e the state of each pixel. each bit de?es one unique pixel. table 25-4 shows the correlation of each bit in the lcdd registers to the respective common and segment signals. any lcd pixel location not being used for display can be used as general purpose ram. table 25-4: lcdd registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets lcdd00 seg07 com0 seg06 com0 seg05 com0 seg04 com0 seg03 com0 seg02 com0 seg01 com0 seg00 com0 xxxx xxxx xxxx xxxx lcdd01 seg15 com0 seg14 com0 seg13 com0 seg12 com0 seg11 com0 seg10 com0 seg09 com0 seg08 com0 xxxx xxxx xxxx xxxx lcdd02 seg23 com0 seg22 com0 seg21 com0 seg20 com0 seg19 com0 seg18 com0 seg17 com0 seg16 com0 xxxx xxxx xxxx xxxx lcdd03 seg31 com0 seg30 com0 seg29 com0 seg28 com0 seg27 com0 seg26 com0 seg25 com0 seg24 com0 xxxx xxxx xxxx xxxx lcdd04 seg07 com1 seg06 com1 seg05 com1 seg04 com1 seg03 com1 seg02 com1 seg01 com1 seg00 com1 xxxx xxxx xxxx xxxx lcdd05 seg15 com1 seg14 com1 seg13 com1 seg12 com1 seg11 com1 seg10 com1 seg09 com1 seg08 com1 xxxx xxxx xxxx xxxx lcdd06 seg23 com1 seg22 com1 seg21 com1 seg20 com1 seg19 com1 seg18 com1 seg17 com1 seg16 com1 xxxx xxxx xxxx xxxx lcdd07 seg31 com 1 (1) seg30 com1 seg29 com1 seg28 com1 seg27 com1 seg26 com1 seg25 com1 seg24 com1 xxxx xxxx xxxx xxxx lcdd08 seg07 com2 seg06 com2 seg05 com2 seg04 com2 seg03 com2 seg02 com2 seg01 com2 seg00 com2 xxxx xxxx xxxx xxxx lcdd09 seg15 com2 seg14 com2 seg13 com2 seg12 com2 seg11 com2 seg10 com2 seg09 com2 seg08 com2 xxxx xxxx xxxx xxxx lcdd10 seg23 com2 seg22 com2 seg21 com2 seg20 com2 seg19 com2 seg18 com2 seg17 com2 seg16 com2 xxxx xxxx xxxx xxxx lcdd11 seg31 com 2 (1) seg30 com 2 (1) seg29 com2 seg28 com2 seg27 com2 seg26 com2 seg25 com2 seg24 com2 xxxx xxxx xxxx xxxx lcdd12 seg07 com3 seg06 com3 seg05 com3 seg04 com3 seg03 com3 seg02 com3 seg01 com3 seg00 com3 xxxx xxxx xxxx xxxx lcdd13 seg15 com3 seg14 com3 seg13 com3 seg12 com3 seg11 com3 seg10 com3 seg09 com3 seg08 com3 xxxx xxxx xxxx xxxx lcdd14 seg23 com3 seg22 com3 seg21 com3 seg20 com3 seg19 com3 seg18 com3 seg17 com3 seg16 com3 xxxx xxxx xxxx xxxx lcdd15 seg31 com 3 (1) seg30 com 3 (1) seg29 com 3 (1) seg28 com30 seg27 com3 seg26 com30 seg25 com3 seg24 com3 xxxx xxxx xxxx xxxx note 1: these pixels do not display, but can be used as general purpose ram.
picmicro mid-range mcu family ds31025a-page 25-14 1997 microchip technology inc. 25.5.2 segment enables the lcdse register is used to select the pin function for groups of pins. the selection allows each group of pins to operate as either lcd drivers or digital only pins. to con?ure the pins as a digital port, the corresponding bits in the lcdse register must be cleared. if the pin is a digital input the corresponding tris bit controls the data direction. any bit set in the lcdse register overrides any bit settings in the corresponding tris register. example 25-1: static mux with 32 segments example 25-2: 1/3 mux with 13 segments note 1: on a power-on reset, the lcd pins are con?ured as lcd drivers. note 2: the lmux1:lmux0 bits take precedence over the lcdse bit settings for pins rd7, rd6 and rd5. bcf status,rp0 ; select bank2 bsf status,rp1 ; bcf lcdcon,lmux1 ; select static mux bcf lcdcon,lmux0 ; movlw 0xff ; make portd,e,f,g lcd pins movwf lcdse ; configure rest of lcd bcf status,rp0 ; select bank2 bsf status,rp1 ; bsf lcdcon,lmux1 ; select 1/3 mux bcf lcdcon,lmux0 ; movlw 0x87 ; make portd<7:0> & porte<6:0> lcd pins movwf lcdse ; configure rest of lcd
1997 microchip technology inc. ds31025a-page 25-15 section 25. lcd lcd 25 25.6 voltage generation there are two methods for lcd voltage generation, internal charge pump, or external resistor ladder. 25.6.1 charge pump the lcd charge pump is shown in figure 25-8 . the 1.0v - 2.3v regulator will establish a stable base voltage from the varying battery voltage. this regulator is adjustable through the range by connecting a variable external resistor from vlcdadj to ground. the potentiometer provides contrast adjustment for the lcd. this base voltage is connected to v lcd 1 on the charge pump. the charge pump boosts v lcd 1 into v lcd 2 = 2 * v lcd 1 and v lcd 3 = 3 * v lcd 1. when the charge pump is not operating, v lcd 3 will be internally tied to v dd . see the electrical speci?ations sec- tion for charge pump capacitor and potentiometer values. 25.6.2 external r-ladder the lcd module can also use an external resistor ladder (r-ladder) to generate the lcd volt- ages. figure 25-8 shows external connections for static and 1/3 bias. the vgen (lcdcon<4>) bit must be cleared to use an external r-ladder. figure 25-8: charge pump and resistor ladder block diagram c2 v lcd 2 v lcd 1 v lcd 3 c1 v dd vlcdadj 10 m a connections for internal charge pump, vgen = 1. v dd v dd connections for external r-ladder, 1/3 bias, vgen = 0. connections for external r-ladder, static bias, vgen = 0. nominal charge pump lcden slpen 0.47 m f (2) 0.47 m f (2) 0.47 m f (2) 0.47 m f (2) 10k* 10k (2) 10k* 5k (2) 5k (2) 10k (2) 130k (2) 100k (2) external external external (1) (1) (1) (1) note 1: location of optional ?ter capacitor. 2: these values are provided for design guidance only and should be optimized to the application by the designer.
picmicro mid-range mcu family ds31025a-page 25-16 1997 microchip technology inc. 25.7 operation during sleep the lcd module can operate during sleep. the selection is controlled by bit slpen (lcdcon<6>). setting the slpen bit allows the lcd module to go to sleep. clearing the slpen bit allows the module to continue to operate during sleep. if a sleep instruction is executed and slpen = '1', the lcd module will cease all functions and go into a very low current consumption mode. the module will stop operation immediately and drive the minimum lcd voltage on both segment and common lines. figure 25-9 shows this operation. to ensure that the lcd completes the frame, the sleep instruction should be exe- cuted immediately after a lcd frame boundary. the lcd interrupt can be used to determine the frame boundary. see 25.4 ?cd interrupts for the formulas to calculate the delay. if a sleep instruction is executed and slpen = '0', the module will continue to display the current contents of the lcdd registers. to allow the module to continue operation while in sleep, the clock source must be either the internal rc oscillator or timer1 external oscillator. while in sleep, the lcd data cannot be changed. the lcd module current consumption will not decrease in this mode, however the overall consumption of the device will be lower due to shutdown of the core and other peripheral functions. figure 25-9:sleep entry/exit when slpen = 1 or cs1:cs0 = 00 note: the internal rc oscillator or external timer1 oscillator must be used to operate the lcd module during sleep. com0 com1 com3 3/3v 1/3v 0/3v 3/3v 3/3v 1/3v 2/3v 2/3v 1/3v 0/3v 2/3v 0/3v 3/3v 2/3v 1/3v 0/3v seg0 sleep instruction execution wake-up interrupted frame pin pin pin pin
1997 microchip technology inc. ds31025a-page 25-17 section 25. lcd lcd 25 25.8 effects of a reset the lcd module is disabled, but the lcd pins are con?ured as lcd drivers. this ensures that the microcontroller does not damage the lcd glass by accidently having a dc voltage across a segment. 25.9 con?uring the lcd module the following is the sequence of steps to follow to con?ure the lcd module. 1. select the frame clock prescale using the lp3:lp0 bits (lcdps<3:0>). 2. con?ure the appropriate pins to function as segment drivers using the lcdse register. 3. con?ure the lcd module for the following using the lcdcon register. - multiplex mode and bias, selected by the lmux1:lmux0 bits - timing source, selected by the cs1:cs0 bits - voltage generation, enabled by the vgen bit - sleep mode operation, enabled by the slpen bit 4. write initial values to pixel data registers, lcdd00 through lcdd15. 5. clear lcd interrupt ?g bit, lcdif, and if desired, enable the interrupt by setting the lcdie bit. 6. enable the lcd module, by setting the lcden bit (lcdcon<7>).
picmicro mid-range mcu family ds31025a-page 25-18 1997 microchip technology inc. 25.10 discrimination ratio discrimination ratio is a way to calculate the contrast levels that a panel can achieve. the ?st example is a static waveform from figure 25-3. the voltages v 1 and v 0 will be assigned values of 1 and 0. the next step is to construct an equation for one frame to help visualize the dc and rms voltages present on an individual pixel that is on and off. the rest of the following shows the calculation of the dc, rms, and discrimination ratio. example 25-3: discrimination ratio calculation for static mux comx - segx [on] comx - segx [off] = 1 - 1, = 0 + 0, v dc = 0 v dc = 0 v rms [on] = d v (1) 2 + (-1) 2 2 1 d v = v rms [off] = d v (0) 2 + (0) 2 2 0 d v = d = v rms [on] v rms [off] = 1 d v 0 d v = see figure 25-3 for static waveform.
1997 microchip technology inc. ds31025a-page 25-19 section 25. lcd lcd 25 the next example is for figure 25-6 which is a 1/4 mux, 1/3 bias waveform. for this example, the values 3, 2, 1 and 0 will be assigned to v 3 , v 2 , v 1 , and v 0 respectively. the frame equation, dc voltage, rms voltage and discrimination ratio calculations are shown in example 25-4 . example 25-4: discrimination ratio calculation 1/4 mux as shown in these examples, static displays have excellent contrast. the higher the multiplex ratio of the lcd, the lower the discrimination ratio, and therefore, the lower the contrast of the display. table 25-5 shows the v off , v on and discrimination ratios of the various combinations of mux and bias. as the multiplex of the lcd panel increases, the discrimination ratio decreases. the contrast of the panel will also decrease, so to provide better contrast the lcd voltages must be increased to provide greater separation between each level. table 25-5: discrimination ratio vs. mux and bias com0 - segx [on] = 3 - 3 + 1 - 1 + 1 - 1 + 1 - 1 v dc = 0 com0 - segx [off] = 1 - 1 - 1 + 1 - 1 + 1 - 1 + 1 v dc = 0 note: refer to figure 25-6 v rms [on] = d v (3) 2 + (-3) 2 + (1) 2 + (-1) 2 + (1) 2 + (-1) 2 + (1) 2 + (-1) 2 8 3 d v = v rms [off] = d v d v = (1) 2 + (-1) 2 + (-1) 2 + (1) 2 + (-1) 2 + (1) 2 + (-1) 2 + (1) 2 8 d = v rms [on] v rms [off] = 3 d v 1 d v = 1.732 1/3 bias v off v on d static 01 1/2 mux 0.333 0.745 2.236 1/3 mux 0.333 0.638 1.915 1/4 mux 0.333 0.577 1.732
picmicro mid-range mcu family ds31025a-page 25-20 1997 microchip technology inc. 25.11 lcd voltage generation among the many ways to generate lcd voltage, two methods stand out above the crowd: resistor ladder charge pump. the resistor ladder method, shown in figure 25-10 , is most commonly used for higher v cc volt- ages. this method uses inexpensive resistors to create the multi-level lcd voltages. regardless of the number of pixels that are energized the current remains constant. the voltage at point v3 is typically tied to v cc , either internally or externally. the resistance values are determined by two factors: display quality and power consumption. display quality is a function of the lcd drive waveforms. since the lcd panel is a capacitive load, the waveform is distorted due to the charging and discharging currents. this distortion can be reduced by decreasing the value of resistance. however, this change increases the power consumption due to the increased current now ?wing through the resistors. as the lcd panel increases in size, the resistance value must be decreased to maintain the image quality of the display. sometimes the addition of parallel capacitors to the resistance can reduce the distortion caused by charging/discharging currents. the capacitors act as charge storage to provide current as the display waveform transitions. in general, r is 1 k w to 50 k w and the potentiometer is 5 k w to 200 k w . figure 25-10: resistor ladder figure 25-11: resistor ladder with capacitors r v 2 v 1 v 0 v 3 r r v 3 v 2 v 1 v 0 r r r c c c +5v
1997 microchip technology inc. ds31025a-page 25-21 section 25. lcd lcd 25 a charge pump is ideal for low voltage battery operation because the v dd voltage can be boosted up to drive the lcd panel. the charge pump requires a charging capacitor and ?ter capacitor for each of the lcd voltages as seen in figure 25-12. these capacitors are typically low leakage types such as polyester, polypropylene, or polystyrene material. another feature that makes the charge pump ideal for battery applications is that the current consumption is proportional to the number of pixels that are energized. figure 25-12: charge pump c1 c2 v3 v2 v1 v0 vadj
picmicro mid-range mcu family ds31025a-page 25-22 1997 microchip technology inc. 25.12 contrast although contrast is heavily dependent on the light source available and the multiplex mode, it also varies with the lcd voltage levels. as previously seen, a potentiometer is used to control the contrast of the lcd panel. the potentiometer sets the separation between each of the lcd voltages. the larger the separation, the better the contrast achievable. 25.13 lcd glass the characteristics of the lcd glass vary depending on the materials used. appendix b gives a list of some lcd manufacturers. please contact them for the characteristics of your desired glass.
1997 microchip technology inc. ds31025a-page 25-23 section 25. lcd lcd 25 25.14 initialization example 25-5 shows the code for initializing the lcd module with all segments cleared. example 25-5: lcd initialization code bcf pir1,lcdif ; clear lcd interrupt flag bcf status,rp0 ; go to bank2 bsf status,rp1 movlw 0x06 ; set frame freq to ~37hz movwf lcdps movlw 0xff ; make all pin functions lcd drivers movwf lcdse movlw 0x17 ; drive during sleep, charge pump enabled movwf lcdcon ; timer1 clock source, 1/4 mux clrf lcdd00 ; clear all data registers to turn clrf lcdd01 ; all pixels off clrf lcdd02 clrf lcdd03 clrf lcdd04 clrf lcdd05 clrf lcdd06 clrf lcdd07 clrf lcdd08 clrf lcdd09 clrf lcdd10 clrf lcdd11 clrf lcdd12 clrf lcdd13 clrf lcdd14 clrf lcdd15 bsf pie1,lcdie ; enable lcd interrupts bsf lcdcon,lcden ; enable lcd module bcf status,rp1 ; go to bank0
picmicro mid-range mcu family ds31025a-page 25-24 1997 microchip technology inc. 25.15 design tips question 1: i? trying to use some of the lcd pins as inputs. answer 1: ensure that you have the control bits in the lcdse properly con?ured, since these bits override the tris bits. question 2: my lcd panel is ?ckering. answer 2: your frame frequency may be too low. the frame frequency can be changed in the lcdps register. question 3: the lcd segments are not very visible. answer 3: this may be due to misadjusted lcd voltage, some possibilities include: 1. if you are using the r-ladder, try different values of r, vary the r-ladder potentiometer. the vlcdadj pin should be connected to ground. 2. if you are using the charge pump, adjust the resistance value on the vlcdadj pin.
1997 microchip technology inc. ds31025a-page 25-25 section 25. lcd lcd 25 25.16 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the lcd driv- ers are: title application note # yet another clock using the pic16c92x an649 lcd fundamentals using pic16c92x microcontrollers an658 picdem3 demo board users guide ds51079
picmicro mid-range mcu family ds31025a-page 25-26 1997 microchip technology inc. 25.17 revision history revision a this is the initial released revision of the lcd module description.
1997 microchip technology inc. ds31026a page 26-1 watchdog timer and sleep mode 26 m section 26. watchdog timer and sleep mode highlights this section of the manual contains the following major topics: 26.1 introduction ............................................................................................................... ...26-2 26.2 control register ........................................................................................................... 26-3 26.3 watchdog timer (wdt) operation...............................................................................26-4 26.4 sleep (power-down) mode........................................................................................26-7 26.5 initialization ............................................................................................................. .....26-9 26.6 design tips ................................................................................................................ 26-10 26.7 related application notes..........................................................................................26-11 26.8 revision history .........................................................................................................26 -12
picmicro mid-range mcu family ds31026a-page 26-2 1997 microchip technology inc. 26.1 introduction the watchdog timer (wdt) is a free running on-chip rc oscillator which does not require any external components. the block diagram is shown in figure 26-1 . this rc oscillator is separate from the device rc oscillator of the osc1/clkin pin. this means that the wdt will run, even if the clock on the osc1 and osc2 pins has been stopped, for example, by execution of a sleep instruction. the watchdog timer (wdt) is enabled/disabled by a device con?uration bit. if the wdt is enabled, software execution may not disable this function. figure 26-1: watchdog timer block diagram from tmr0 clock source to tmr0 postscaler wdt timer wdt enable bit 0 1 m u x psa 8 - to - 1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option register. 8
1997 microchip technology inc. ds31026a-page 26-3 section 26. watchdog timer and sleep mode watchdog timer and sleep mode 26 26.2 control register the option_reg register is a readable and writable register which contains various control bits to con?ure the tmr0 prescaler/wdt postscaler, the external int interrupt, tmr0, and the weak pull-ups on portb. register 26-1: option_reg register note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu (1) intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu (1) : weak pull-up enable bit 1 = weak pull-ups are disabled 0 = weak pull-ups are enabled by individual port latch values bit 6 intedg : interrupt edge select bit 1 = interrupt on rising edge of int pin 0 = interrupt on falling edge of int pin bit 5 t0cs : tmr0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2:0 ps2:ps0 : tmr0 prescaler/wdt postscaler rate select bits legend r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate note 1: some devices call this bit gppu . devices that have the rbpu bit, have the weak pull-ups on portb, while devices that have the gppu have the weak pull-ups on the gp port.
picmicro mid-range mcu family ds31026a-page 26-4 1997 microchip technology inc. 26.3 watchdog timer (wdt) operation during normal operation, a wdt time-out generates a device reset. if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation, this is known as a wdt wake-up. the wdt can be permanently disabled by clearing the wdte con- ?uration bit. the postscaler assignment is fully under software control, i.e., it can be changed ?n the ? dur- ing program execution. in example 26-1 , the ?st modi?ation of the option_reg does not need to be included if the ?al desired prescaler is other then 1:1. if the ?al prescaler value is 1:1, then a temporary pres- cale value is set (other than 1:1), and the ?al prescale value is set in the last modi?ation of the option_reg. this sequence must be followed since the value in the tmr0 prescaler is unknown, and is being used as the wdt postscaler. if the option_reg is changed without this code sequence, the time before a wdt reset is unknown. note: to avoid an unintended device reset, the following instruction sequence (shown in example 26-1 ) must be executed when changing the prescaler assignment from timer0 to the postscaler of the wdt. this sequence must be followed even if the wdt is disabled.
1997 microchip technology inc. ds31026a-page 26-5 section 26. watchdog timer and sleep mode watchdog timer and sleep mode 26 example 26-1: changing prescaler (timer0 ? wdt) to change prescaler from the wdt to the timer0 module use the sequence shown in example 26-2 . example 26-2: changing prescaler (wdt ? timer0) bsf status, rp0 ; bank1 movlw b?x0x0xxx? ; select clock source and postscale value movwf option_reg ; other than 1:1 bcf status, rp0 ; bank0 clrf tmr0 ; clear tmr0 & prescaler bsf status, rp0 ; bank1 movlw b?xxx1xxx? ; select wdt, do not change prescale value movwf option_reg ; clrwdt ; clears wdt movlw b'xxxx1xxx' ; select new prescale value and wdt movwf option_reg ; bcf status, rp0 ; bank0 clrwdt ; clear wdt and postscaler bsf status, rp0 ; bank1 movlw b'xxxx0xxx' ; select tmr0, new prescale movwf option_reg ; value and clock source bcf status, rp0 ; bank0
picmicro mid-range mcu family ds31026a-page 26-6 1997 microchip technology inc. 26.3.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no postscaler). the time-out period var- ies with temperature, v dd and process variations from part to part (see dc specs). if longer time-outs are desired, a postscaler with a division ratio of up to 1:128 can be assigned to the wdt, under software control, by writing to the option_reg register. thus, time-out periods of up to 2.3 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler (if assigned to the wdt) and prevent it from timing out and generating a device reset. the t o bit in the status register will be cleared upon a watchdog timer time-out (wdt reset and wdt wake-up). 26.3.2 wdt programming considerations it should also be taken in account that under worst case conditions (v dd = minimum, tempera- ture = maximum, maximum wdt postscaler) it may take several seconds before a wdt time-out occurs. table 26-1: summary of watchdog timer registers note: when the postscaler is assigned to the wdt, always execute a clrwdt instruction before changing the postscale value, otherwise a wdt reset may occur. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 con?. bits mpeen boden cp1 cp0 pwr te wdte fosc1 fosc0 option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer.
1997 microchip technology inc. ds31026a-page 26-7 section 26. watchdog timer and sleep mode watchdog timer and sleep mode 26 26.4 sleep (power-down) mode sleep (power-down) mode is a mode where the device is placed in its lowest current consump- tion state. the device oscillator is turned off, so no system clocks are occurring in the device. sleep mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit in the status reg- ister is cleared, the t o bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had, before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, all i/o pins should be either at v dd , or v ss , with no external circuitry drawing current from the i/o pin and the modules that are speci?d to have a delta sleep current should be disabled. i/o pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by ?ating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). some features of the device that consume a delta sleep current are enabled / disabled by device con?uration bits. these include the watchdog timer (wdt) and brown-out reset (bor) cir- cuitry modules. 26.4.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. any device reset. 2. watchdog timer wake-up (if wdt was enabled). 3. any peripheral module which can set its interrupt ?g while in sleep, such as: - external int pin - change on port pin - comparators - a/d - timer1 - lcd - ssp - capture the ?st event will reset the device upon wake-up. however the latter two events will wake the device and then resume program execution. the t o and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up is cleared when sleep is invoked. the t o bit is cleared if wdt wake-up occurred. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the interrupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have an nop after the sleep instruction.
picmicro mid-range mcu family ds31026a-page 26-8 1997 microchip technology inc. 26.4.2 wake-up using interrupts when interrupts are globally disabled (gie cleared) and any interrupt source has both its inter- rupt enable bit and interrupt ?g set, one of the following events will occur: if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will complete as an nop. therefore, the wdt and wdt postscaler will not be cleared, the t o bit will not be set and pd bit will not be cleared. if the interrupt occurs during or after the execution of a sleep instruction, the device will immediately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the t o bit will be set and the pd bit will be cleared. even if the ?g bits were checked before executing a sleep instruction, it may be possible for ?g bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as an nop. to ensure that the wdt is clear, a clrwdt instruction should be executed before a sleep instruc- tion. figure 26-2: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf ?g (intcon<1>) gie bit (intcon<7>) instr uction flo w pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = '1' assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = '0', execution will continue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference.
1997 microchip technology inc. ds31026a-page 26-9 section 26. watchdog timer and sleep mode watchdog timer and sleep mode 26 26.5 initialization no initialization code at this time.
picmicro mid-range mcu family ds31026a-page 26-10 1997 microchip technology inc. 26.6 design tips question 1: my system voltage drops and then returns to the speci?d device voltage range. the device is not operating correctly and the wdt does not reset and return the device to proper operation. answer 1: the wdt was not designed to be a recovery from a brown-out condition. it was designed to recover from errant software operation (the device remaining in the speci?d operating ranges). if your system can be subjected to brown-outs, either the on-chip brown-out circuitry should be enabled or an external brown-out circuit should be implemented. question 2: device resets even though i do the clrwdt instruction in my loop. answer 2: make sure that the loop with the clrwdt instruction meets the minimum speci?ation of the wdt (not the typical). question 3: device never gets out of resets. answer 3: on power-up, you must take into account the oscillator start-up time (tost). sometimes it helps to put the clrwdt instruction at the beginning of the loop, since this start-up time may be variable.
1997 microchip technology inc. ds31026a-page 26-11 section 26. watchdog timer and sleep mode watchdog timer and sleep mode 26 26.7 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the wdt and sleep mode are: title application note # power-up trouble shooting an607
picmicro mid-range mcu family ds31026a-page 26-12 1997 microchip technology inc. 26.8 revision history revision a this is the initial released revision of the watchdog timer and sleep mode description.
1997 microchip technology inc. ds31027a page 27-1 m device con?uration bits 27 section 27. device con?uration bits highlights this section of the manual contains the following major topics: 27.1 introduction ............................................................................................................... ...27-2 27.2 con?uration word bits ...............................................................................................27-4 27.3 program veri?ation/code protection ..........................................................................27-8 27.4 id locations ............................................................................................................... ..27-9 27.5 design tips ................................................................................................................ 27-10 27.6 related application notes..........................................................................................27-11 27.7 revision history .........................................................................................................27 -12
picmicro mid-range mcu family ds31027a-page 27-2 1997 microchip technology inc. 27.1 introduction the device con?uration bits allow each user to customize certain aspects of the device to the needs of the application. when the device powers up, the state of these bits determines the modes that the device uses. subsection 27.2 ?on?uration word bits discusses the con?- uration bits, and the modes that they can be con?ured to. these bits are mapped in program memory location 2007h. this location is not accessible during normal device operation (can be accessed only during programming mode). the con?uration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device con?urations. the ability to change these settings once they have been programmed depends on the memory technology and the package type. for read only memory (rom) devices, these bits are speci?d at time of rom code submittal and once the device is masked may not be changed for those devices (would require a new mask code). for one time programmable (otp) devices, once these bits are programmed (??, they may not be changed. for windowed eprom devices, once these bits are programmed (??, the device must be uv erased to return the con?uration word to the erased state. uv erasing the device also erases the program memory. for flash devices, these bits may be erased and reprogrammed. note: microchip does not recommend code protecting windowed devices.
1997 microchip technology inc. ds31027a-page 27-3 section 27. device configuration bits device con?uration bits 27 section 27.2 is forced to the next page for formatting purposes.
picmicro mid-range mcu family ds31027a-page 27-4 1997 microchip technology inc. 27.2 con?uration word bits these con?uration bits specify some of the modes of the device, and are programmed by a device programmer, or by using the in-circuit serial programming (icsp) feature of the midrange devices. the device is not able to read the values of these bits, and there placement is automat- ically taken care of when you select the device in you device programmer. for additional infor- mation, please refer to the programming speci?ation of the device. note 1: always ensure that your device programmer has the same device selected as you are programming. note 2: microchip recommends that the desired con?uration bit states be embedded in to the application source code. this is easily done in the mpasm assembler by the use of the config directive. see subsection 27.2.1 ?pasms config directive. cp1:cp0: code protection bits 11 = code protection off 10 = see device data sheet 01 = see device data sheet 00 = all memory is code protected note: some devices may use more or less bits to determine the code protect. presently there are also some devices that use only one bit (cp0). for these devices the bit description is: 1 = code protection off 0 = code protection on dp: data eeprom memory code protection bit 1 = code protection off 0 = data eeprom memory is code protected note: this bit is used when a device with rom program memory also has data eeprom memory. boden : brown-out reset enable bit 1 = bor enabled 0 = bor disabled note: enabling brown-out reset automatically enables the power-up timer (pwrt) regardless of the value of bit pwr te . ensure the power-up timer is enabled any- time brown-out reset is enabled. pwr te : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled note 1: enabling brown-out reset automatically enables power-up timer (pwrt) regard- less of the value of bit pwr te . ensure the power-up timer is enabled anytime brown-out reset is enabled. note 2: some original picmicros have the polarity of this bit reversed. note 3: mclre : mclr pin function select bit 1 = pins function is mclr 0 = pins function is as a digital i/o. mclr is internally tied to v dd . wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled
1997 microchip technology inc. ds31027a-page 27-5 section 27. device configuration bits device con?uration bits 27 fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator fosc2:fosc0 : oscillator selection bits 111 = extrc oscillator, with clkout 110 = extrc oscillator 101 = intrc oscillator, with clkout 100 = intrc oscillator 011 = reserved 010 = hs oscillator 001 = xt oscillator 000 = lp oscillator unimplemented : read as '1' legend r = readable bit p = programmable bit u = unimplemented bit, read as ? - n = value at por reset u = unchanged from programmed state note: the bit position of the con?uration bits is device dependent. please refer to the device programming speci?ation for bit placement. the use of a microchip device programmer does not require you to know the bit locations.
picmicro mid-range mcu family ds31027a-page 27-6 1997 microchip technology inc. 27.2.1 mpasms config directive microchips assembler, mpasm, has a nice feature that allows you to specify, in the source code ?e, the selected states of the con?uration bits for this program. this ensures that when pro- gramming a device for an application the required con?uration is also programmed. this mini- mizes the risk of programming the wrong device con?uration, and wondering why it no longer works in the application. example 27-1 show a template for using the config directive. example 27-1:using the config directive, a source file template the symbols that are currently in the microchip device header ?es that make using the config directive straight forward are shown in table 27-1 . for the symbols available for your device, please refer to that devices microchip include ?e. list p = p16c77 ; list directive, ; revision history ; #include ; microchip device header file ; #include ; file which includes my standard macros #include ; file which includes macros specific ; to this application ; ; specify device configuration bits ; __config _xt_osc & _pwrte_on & _boden_off & _cp_off & _wdt_on ; org 0x00 ; start of program memory reset_addr : ; first instruction to execute after a reset end note: as long as the correct device is speci?d (in the list and include ?e directives), the correct polarity of all bits is ensured.
1997 microchip technology inc. ds31027a-page 27-7 section 27. device configuration bits device con?uration bits 27 table 27-1: __config directive symbols (from microchip header files) feature symbols oscillators _rc_osc _extrc_osc _extrc_osc_clkout _extrc_osc_noclkout _intrc_osc _intrc_osc_clkout _intrc_osc_noclkout _lp_osc _xt_osc _hs_osc watch dog timer _wdt_on _wdt_off power-up timer _pwrte_on _pwrte_off brown-out reset _boden_on _boden_off master clear enable _mclre_on _mclre_off code protect _cp_all _cp_on _cp_75 _cp_50 _cp_off code protect data eeprom _dp_on _dp_off code protect calibration space _cpc_on _cpc_off note 1: not all con?uration bit symbols may be available on any one device. please refer to the microchip include ?e of that device for available symbols.
picmicro mid-range mcu family ds31027a-page 27-8 1997 microchip technology inc. 27.3 program veri?ation/code protection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out for veri?ation purposes. 27.3.1 rom devices when a rom device also has data eeprom memory, an additional code protect con?uration bit may be implemented. the program memory con?uration bit is submitted as part of the rom code submittal. the data eeprom memory code protect con?uration bit will be an eeprom bit. when rom devices complete testing, the eeprom data memory code protect bit will be pro- grammed to the same state as the program memory code protect bit. that is data eeprom code protect is off, when program memory code protect is off, and data eeprom code protect is on for all other selections. in applications where the device is code protected and the data eeprom needs to be pro- grammed before the application can be released, the data eeprom memory must have the entire data eeprom memory erased. the device programming speci?ation details the steps to do this. microchip device programmers implement the speci?d sequence. once this sequence is complete, the data eeprom memory code protect is disabled. this allows the desired data to be programmed into the device. after programming the data eeprom memory array, the data eeprom memory code protect con?uration bit should be programmed as desired. note: microchip does not recommend code protecting windowed devices.
1997 microchip technology inc. ds31027a-page 27-9 section 27. device configuration bits device con?uration bits 27 27.4 id locations four memory locations (2000h - 2003h) are designated as id locations where the user can store checksum or other code-identi?ation numbers. these locations are not accessible during nor- mal execution but are readable and writable during program/verify. it is recommended that only the 4 least signi?ant bits of the id location are used.
picmicro mid-range mcu family ds31027a-page 27-10 1997 microchip technology inc. 27.5 design tips question 1: i have a jw device and i can no longer program it (reads scrambled data or all '0's). whats wrong with the device? answer 1: nothing. you probably code protected the device. if this is the case, the device is no longer usable. see subsection 27.3 ?rogram veri?ation/code protection for more details. question 2: in converting from a pic16c74 to a pic16c74a, my application no longer works. answer 2: 1. did you re-assemble the source ?e specifying the pic16c74a in the include ?e and list directives. the use of the config directive is highly recommended. 2. on the device programmer, did you specify the pic16c74a, and were all the con?uration bits as desired? question 3: when i erase the device, the program memory is blank but the con?ura- tion word is not yet erased. answer 3: that is by design. also remember that microchip does not recommend code protecting windowed devices.
1997 microchip technology inc. ds31027a-page 27-11 section 27. device configuration bits device con?uration bits 27 27.6 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to con?uration word are: title application note # no related application notes at this time.
picmicro mid-range mcu family ds31027a-page 27-12 1997 microchip technology inc. 27.7 revision history revision a this is the initial released revision of the con?uration word description.
1997 microchip technology inc. ds31028a page 28-1 m icsp 28 section 28. in-circuit serial programming (icsp) highlights this section of the manual contains the following major topics: 28.1 introduction ............................................................................................................... ...28-2 28.2 entering in-circuit serial programming mode .............................................................28-3 28.3 application circuit ........................................................................................................ 28-4 28.4 programmer ................................................................................................................. 28-6 28.5 programming environment ..........................................................................................28-6 28.6 other bene?s .............................................................................................................. 28-7 28.7 field programming of picmicro otp mcus................................................................28-8 28.8 field programming of flash picmicros...................................................................28-10 28.9 design tips ................................................................................................................ 28-12 28.10 related application notes..........................................................................................28-13 28.11 revision history .........................................................................................................2 8-14
picmicro mid-range mcu family ds31028a-page 28-2 1997 microchip technology inc. 28.1 introduction all midrange devices can be in-circuit serial programmed (icsp) while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. in-circuit serial programming (icsp) is a great way to reduce your inventory overhead and time-to-market for your product. by assembling your product with a blank microchip microcontrol- ler (mcu), you can stock one design. when an order has been placed, these units can be pro- grammed with the latest revision of ?mware, tested, and shipped in a very short time. this method also reduces scrapped inventory due to old ?mware revisions. this type of manufactur- ing system can also facilitate quick turnarounds on custom orders for your product. most people would think to use icsp with picmicro otp mcus only on an assembly line where the device is programmed once. however, there is a method by which an otp device can be programmed several times depending on the size of the ?mware. this method, explained later, provides a way to ?ld upgrade your ?mware in a way similar to eeprom- or flash-based devices.
1997 microchip technology inc. ds31028a-page 28-3 section 28. icsp icsp 28 28.2 entering in-circuit serial programming mode the device is placed into a program/verify mode by holding the rb6 and rb7 pins low while rais- ing the mclr (v pp ) pin from v il to v ihh (see programming speci?ation) and having v dd at the programming voltage. rb6 becomes the programming clock and rb7 becomes the program- ming data. both rb6 and rb7 are schmitt trigger inputs in this mode, and when rb7 is driving data it is a cmos output driver. after reset, to place the device into programming/verify mode, the program counter (pc) is at location 00h. a 6-bit command is then supplied to the device. some commands then specify that 14-bits of program data are then supplied to or read from the device, depending on if the com- mand was a load or a read. for complete details of serial programming, please refer to the device speci? programming speci?ations. during the in-circuit serial programming mode, the wdt circuitry is disabled from generating a device reset.
picmicro mid-range mcu family ds31028a-page 28-4 1997 microchip technology inc. 28.3 application circuit the application circuit must be designed to allow all the programming signals to be directly con- nected to the picmicro mcu. figure 28-1 shows a typical circuit that is a starting point for when designing with icsp. the application must compensate for the following issues: isolation of the mclr /v pp pin from the rest of the circuit loading of pins rb6 and rb7 capacitance on each of the v dd , mclr /v pp , rb6, and rb7 pins minimum and maximum operating voltage for v dd picmicro oscillator interface to the programmer the mclr /v pp pin is normally connected to an rc circuit. the pull-up resistor is tied to v dd and a capacitor is tied to ground. this circuit can affect the operation of icsp depending on the size of the capacitor since the v pp voltage must be isolated from the rest of the circuit (in most cases a resistor is not capable of isolating the circuit). it is, therefore, recommended that the circuit in figure 28-1 be used when an rc is connected to mclr /v pp . the diode should be a schot- tky-type device. another issue with mclr /v pp is that when the picmicro device is programmed, this pin is driven to approximately 13v and also to ground. therefore, the application circuit must be isolated from this voltage provided by the programmer. pins rb6 and rb7 are used by the picmicro for serial programming. rb6 is the clock line and rb7 is the data line. rb6 is driven by the programmer. rb7 is a bi-directional pin that is driven by the programmer when programming, and driven by the picmicro when verifying. these pins must be isolated from the rest of the application circuit so as not to affect the signals during pro- gramming. you must take into consideration the output impedance of the programmer when iso- lating rb6 and rb7 from the rest of the circuit. this isolation circuit must account for rb6 being an input on the picmicro, and for rb7 being bi-directional (can be driven by both the picmicro and the programmer). for instance, pro mate ii has an output impedance of 1k w . if the design permits, these pins should not be used by the application. this is not the case with most applications so it is recommended that the designer evaluate whether these signals need to be buffered. as a designer, you must consider what type of circuitry is connected to rb6 and rb7 and then make a decision on how to isolate these pins. figure 28-1 does not show any circuitry to isolate rb6 and rb7 on the application circuit because this is very application dependent. to simplify this interface the optimal usage of these i/o in the application are (in order): 1. do not use rb6/rb7 so they are dedicated to icsp. 2. use these pins as outputs with minimal loading on signal line. 3. isolation circuitry so that these signals can be driven to the icsp speci?ations. figure 28-1: typical in-circuit serial programming (icsp) application circuit application pcb pic16cxxx mclr /v pp v dd v ss rb7 rb6 v dd v dd to application circuit isolation circuits icsp connector
1997 microchip technology inc. ds31028a-page 28-5 section 28. icsp icsp 28 the total capacitance on the programming pins affects the rise rates of these signals as they are driven out of the programmer. typical circuits use several hundred microfarads of capacitance on v dd which helps to dampen noise and ripple. however, this capacitance requires a fairly strong driver in the programmer to meet the rise rate timings for v dd . most programmers are designed to simply program the picmicro itself and don? have strong enough drivers to power the appli- cation circuit. one solution is to use a driver board between the programmer and the application circuit. the driver board requires a separate power supply that is capable of driving the v pp and v dd pins with the correct rise rates and should also provide enough current to power the appli- cation circuit. rb6 and rb7 are not buffered on this schematic but may require buffering depend- ing upon the application. a sample driver board schematic is shown in figure 28-2 . the microchip programming speci?ation states that the device should be programmed at 5v. special considerations must be made if your application circuit operates at 3v only. these con- siderations may include totally isolating the picmicro during programming. the other issue is that the device must be veri?d at the minimum and maximum voltages at which the application circuit will be operating. for instance, a battery operated system may operate from three 1.5v cells giv- ing an operating voltage range of 2.7v to 4.5v. the programmer must program the device at 5v and must verify the program memory contents at both 2.7v and 4.5v to ensure that proper pro- gramming margins have been achieved. this ensures the picmicro operation over the voltage range of the system. the ?al issue deals with the oscillator circuit on the application board. the voltage on mclr /v pp must rise to the speci?d program mode entry voltage before the device executes any code. the crystal modes available on the picmicro are not affected by this issue because the oscillator start-up timer waits for 1024 oscillations before any code is executed. however, rc oscillators do not require any start-up time and, therefore, the oscillator start-up timer is not used. the programmer must drive mclr /v pp to the program mode entry voltage before the rc oscillator toggles four times. if the rc oscillator toggles four or more times, the program counter will be incremented to some value x. now when the device enters programming mode, the pro- gram counter will not be zero and the programmer will start programming your code at an offset of x. there are several alternatives that can compensate for a slow rise rate on mclr /v pp . the ?st method would be to not populate the r, program the device, and then insert the r. the other method would be to have the programming interface drive the osc1 pin of the picmicro to ground while programming. this will prevent any oscillations from occurring during programming. now all that is left is how to connect the application circuit to the programmer. this depends a lot on the programming environment and will be discussed in that section. note: the driver board design must be tested in the user's application to determine the effects of the application circuit on the programming signals timing. changes may be required if the application places a signi?ant load on v dd , v pp , rb6 or rb7.
picmicro mid-range mcu family ds31028a-page 28-6 1997 microchip technology inc. 28.4 programmer the second consideration is the programmer. pic16cxxx mcus only use serial programming and therefore all programmers supporting these devices will support icsp. one issue with the programmer is the drive capability. as discussed before, it must be able to provide the speci?d rise rates on the icsp signals and also provide enough current to power the application circuit. figure 28-2 shows an example driver board. this driver schematic does not show any buffer cir- cuitry for rb6 and rb7. it is recommended that an evaluation be performed to determine if buff- ering is required. another issue with the programmer is what v dd levels are used to verify the memory contents of the picmicro. for instance, the pro mate ii veri?s program memory at the minimum and maximum v dd levels for the speci?d device and is therefore considered a pro- duction quality programmer. on the other hand, the picstart plus only veri?s at 5v and is for prototyping use only. the microchip programming speci?ations state that the program mem- ory contents should be veri?d at both the minimum and maximum v dd levels that the application circuit will be operating. this implies that the application circuit must be able to handle the varying v dd voltages. there are also several third party programmers that are available. you should select a program- mer based on the features it has and how it ?s into your programming environment. the micro- chip development systems ordering guide (ds30177) provides detailed information on all our development tools. the microchip third party guide (ds00104) provides information on all of our third party tool developers. please consult these two references when selecting a programmer. many options exist including serial or parallel pc host connection, stand-alone operation, and single or gang programmers. some of the third party developers include advanced transdata corporation, bp microsystems, data i/o, emulation technology and logical devices. 28.5 programming environment the programming environment will affect the type of programmer used, the programmer cable length, and the application circuit interface. some programmers are well suited for a manual assembly line while others are desirable for an automated assembly line. you may want to choose a gang programmer to program multiple systems at a time. the physical distance between the programmer and the application circuit affects the load capac- itance on each of the programming signals. this will directly affect the drive strength needed to provide the correct signal rise rates and current. this programming cable must also be as short as possible and properly terminated and shielded, or the programming signals may be corrupted by ringing or noise. finally, the application circuit interface to the programmer depends on the size constraints of the application circuit itself and the assembly line. a simple header can be used to interface the appli- cation circuit to the programmer. this might be more desirable for a manual assembly line where a technician plugs the programmer cable into the board. a different method is the use of spring loaded test pins (commonly referred to as pogo pins). the application circuit has pads on the board for each of the programming signals. then there is a ?ture that has pogo pins in the same con?uration as the pads on the board. the application circuit or ?ture is moved into position such that the pogo pins come into contact with the board. this method might be more suitable for an automated assembly line. after taking into consideration the issues with the application circuit, the programmer, and the programming environment, anyone can build a high quality, reliable manufacturing line based on icsp.
1997 microchip technology inc. ds31028a-page 28-7 section 28. icsp icsp 28 28.6 other bene?s icsp provides other bene?s, such as calibration and serialization. if program memory permits, it would be cheaper and more reliable to store calibration constants in program memory instead of using an external serial eeprom. for example, if your system has a thermistor which can vary from one system to another, storing some calibration information in a table format allows the microcontroller to compensate (in software) for external component tolerances. system cost can be reduced without affecting the required performance of the system by using software calibra- tion techniques. but how does this relate to icsp? the picmicro has already been programmed with ?mware that performs a calibration cycle. the calibration data is transferred to a calibration ?ture. when all calibration data has been transferred, the ?ture places the picmicro in pro- gramming mode and programs the picmicro with the calibration data. application note an656, in-circuit serial programming of calibration parameters using a picmicro microcontroller , shows exactly how to implement this type of calibration data programming. the other bene? of icsp is serialization. each individual system can be programmed with a unique or random serial number. one such application of a unique serial number would be for security systems. a typical system might use dip switches to set the serial number. instead, this number can be burned into program memory, thus reducing the overall system cost and lowering the risk of tampering.
picmicro mid-range mcu family ds31028a-page 28-8 1997 microchip technology inc. 28.7 field programming of picmicro otp mcus an otp device is not normally capable of being reprogrammed, but the picmicro architecture gives you this ?xibility provided the size of your ?mware is at least half that of the desired device and the device is not code protected. if your target device does not have enough program mem- ory, microchip provides a wide spectrum of devices from 0.5k to 8k program memory with the same set of peripheral features that will help meet the criteria. the pic16cxxx microcontrollers have two vectors, reset and interrupt, at locations 0x0000 and 0x0004. when the picmicro encounters a reset or interrupt condition, the code located at one of these two locations in program memory is executed. the ?st listing of example 28-2 shows the code that is ?st programmed into the picmicro. the second listing of example 28-2 shows the code that is programmed into the picmicro for the second time. example 28-2 shows that to program the picmicro a second time the memory location 0x0000, originally goto main (0x2808), is reprogrammed to all 0s which happens to be a nop instruction. this location cannot be reprogrammed to the new opcode (0x2860) because the bits that are 0s cannot be reprogrammed to 1s, only bits that are 1s can be reprogrammed to 0s. the next mem- ory location 0x0001 was originally blank (all 1s) and now becomes a goto main (0x2860). when a reset condition occurs, the picmicro executes the instruction at location 0x0000 which is the nop , a completely benign instruction, and then executes the goto main to start the execution of code. the example also shows that all program memory locations after 0x005a are blank in the original program so that the second time the picmicro is programmed, the revised code can be programmed at these locations. the same descriptions can be given for the interrupt vector at location 0x0004. this method changes slightly for picmicros with >2k words of program memory. each of the goto main and goto isr instructions are replaced by the following code segment is example 28-1 due to paging on devices with >2k words of program memory. example 28-1: crossing program memory pages now your one-time programmable picmicro is exhibiting eeprom- or flash-like qualities. movlw movlw movwf pclath movwf pclath goto main goto isr
1997 microchip technology inc. ds31028a-page 28-9 section 28. icsp icsp 28 example 28-2: programming cycle listing files first program cycle second program cycle _________________________________________________________________________________________ prog opcode assembly | prog opcode assembly mem instruction | mem instruction ----------------------------------------------------------------------------------------- 0000 2808 goto main ;main loop | 0000 0000 nop 0001 3fff ; at 0x0008 | 0001 2860 goto main; main now 0002 3fff | 0002 3fff ; at 0x0060 0003 3fff | 0003 3fff 0004 2848 goto isr ; isr at | 0004 0000 nop 0005 3fff ; 0x0048 | 0005 28a8 goto isr ; isr now at 0006 3fff | 0006 3fff ; 0x00a8 0007 3fff | 0007 3fff 0008 1683 bsf status,rp0 | 0008 1683 bsf status,rp0 0009 3007 movlw 0x07 | 0009 3007 movlw 0x07 000a 009f movwf adcon1 | 000a 009f movwf adcon1 . | . . | . . | . 0048 1c0c btfss pir1,rbif | 0048 1c0c btfss pir1,rbif 0049 284e goto endisr | 0049 284e goto endisr 004a 1806 btfsc portb,0 | 004a 1806 btfsc portb,0 . | . . | . . | . 0060 3fff | 0060 1683 bsf status,rp0 0061 3fff | 0061 3005 movlw 0x05 0062 3fff | 0062 009f movwf adcon1 . | . . | . . | . 00a8 3fff | 00a8 1c0c btfss pir1,rbif 00a9 3fff | 00a9 28ae goto endisr 00aa 3fff | 00aa 1806 btfsc portb,0 . | . . | . . | . -----------------------------------------------------------------------------------------
picmicro mid-range mcu family ds31028a-page 28-10 1997 microchip technology inc. 28.8 field programming of flash picmicros with the icsp interface circuitry already in place, flash-based picmicros can be easily repro- grammed in the ?ld. these flash devices allow you to reprogram them even if they are code protected. a portable icsp programming station might consist of a laptop computer and pro- grammer. the technician plugs the icsp interface cable into the application circuit and down- loads the new ?mware into the picmicro. the next thing you know the system is up and running without those annoying ?ugs. another instance would be that you want to add an additional fea- ture to your system. all of your current inventory can be converted to the new ?mware and ?ld upgrades can be performed to bring your installed base of systems up to the latest revision of ?mware.
1997 microchip technology inc. ds31028a-page 28-11 section 28. icsp icsp 28 figure 28-2: example driver board schematic c6 0.1 prb6 pv dd 2 3 1 1 4 7 u2a 74hc126 5 6 4 u2b 74hc126 r3 1 rb6 +8v pv dd r6 100 r7 100 3 2 1 q1 2n2907 1 2 3 q3 2n2222 12 13 14 u1d tle2144a r5 100 c7 0.001 v dd 3 2 1 4 1 1 u1a tle2144a c3 0.1 +15v r1 5.1k r8 100 3 2 1 q2 2n2907 r4 1 pv pp 9 8 1 0 u2c 74hc126 12 11 1 3 u2d 74hc126 rb7 prb6 pv pp pv dd 1 2 3 4 5 jp3 header +15v r2 5.1k r9 100 1 2 3 q4 2n2222 10 9 8 u1c tle2144a r10 100 c8 0.001 rb7 v pp v pp v dd 1 2 3 4 5 jp1 header 5 6 7 u1b tle2144a rb6 +15v 1 2 jp2 header c5 0.1 v in 1 gnd 3 v out 2 vr1 lm7808 c9 100 +15v c4 0.1 +8v note : all resistors are in ohms, all capacitors are in m f.
picmicro mid-range mcu family ds31028a-page 28-12 1997 microchip technology inc. 28.9 design tips question 1: when i try to do icsp, the entire program is shifted (offset) in the device program memory. answer 1: if the mclr pin does not rise fast enough, while the devices voltage is in the valid operating range, the internal program counter (pc) can increment. this means that the pc is no longer pointing to the address that you expected to be at. the exact location depends on the number of device clocks that occurred in the valid operating region of the device. question 2: i am using a pro mate ii with a socket that i designed to bring the pro- gramming signal to my application board. sometimes when i try to do icsp, the program memory is programmed wrong. answer 2: the voltages / timings may be violated at the device. this could be due to the: application board circuitry cable length from programmer to target large capacitance on v dd which affects levels / timings
1997 microchip technology inc. ds31028a-page 28-13 section 28. icsp icsp 28 28.10 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to in-circuit serial programming are: title application note # in-circuit serial programming of calibration parameters using a picmicro an656 in-circuit serial programming guide ds30277
picmicro mid-range mcu family ds31028a-page 28-14 1997 microchip technology inc. 28.11 revision history revision a this is the initial released revision of the in-circuit serial programming description.
1997 microchip technology inc. ds31029a page 29-1 m instruction set 29 section 29. instruction set highlights this section of the manual contains the following major topics: 29.1 introduction ............................................................................................................... ...29-2 29.2 instruction formats ......................................................................................................29 -4 29.3 special function registers as source/destination ......................................................29-6 29.4 q cycle activity........................................................................................................... .29-7 29.5 instruction descriptions................................................................................................29- 8 29.6 design tips ................................................................................................................ 29-45 29.7 related application notes..........................................................................................29-47 29.8 revision history .........................................................................................................29 -48
picmicro mid-range mcu family ds31029a-page 29-2 1997 microchip technology inc. 29.1 introduction each midrange instruction is a 14-bit word divided into an opcode which speci?s the instruc- tion type and one or more operands which further specify the operation of the instruction. the midrange instruction set summary in table 29-1 lists the instructions recognized by the mpasm assembler. the instruction set is highly orthogonal and is grouped into three basic categories: byte-oriented operations bit-oriented operations literal and control operations table 29-2 gives the opcode ?ld descriptions. for byte-oriented instructions, 'f' represents a ?e register designator and 'd' represents a des- tination designator. the ?e register designator speci?s which ?e register is to be used by the instruction. the destination designator speci?s where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the ?e register speci?d in the instruction. for bit-oriented instructions, 'b' represents a bit ?ld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ?e in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. all instructions are executed in one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. in these cases, the execution takes two instruction cycles with the second cycle executed as an nop. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execu- tion time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 m s.
1997 microchip technology inc. ds31029a-page 29-3 section 29. instruction set instruction set 29 table 29-1: midrange instruction set mnemonic, operands description cycles 14-bit instruction word status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z t o , pd z t o , pd c,dc,z z note 1: when an i/o register is modi?d as a function of itself (e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin con?ured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modi?d or a conditional test is true, the instruction requires two cycles. the sec- ond cycle is executed as a nop.
picmicro mid-range mcu family ds31029a-page 29-4 1997 microchip technology inc. 29.2 instruction formats figure 29-1 shows the three general formats that the instructions can have. as can be seen from the general format of the instructions, the opcode portion of the instruction word varies from 3-bits to 6-bits of information. this is what allows the midrange instruction set to have 35 instruc- tions. all instruction examples use the following format to represent a hexadecimal number: 0xhh where h signi?s a hexadecimal digit. to represent a binary number: 00000100b where b is a binary string identi?r. figure 29-1: general format for instructions note 1: any unused opcode is reserved. use of any reserved opcode may cause unex- pected operation. note 2: to maintain upward compatibility with future midrange products, do not use the option and tris instructions. byte-oriented ?e register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit ?e register address bit-oriented ?e register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit ?e register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit literal (immediate) value 13 11 10 0 opcode k (literal) k = 11-bit literal (immediate) value general call and goto instructions only
1997 microchip technology inc. ds31029a-page 29-5 section 29. instruction set instruction set 29 table 29-2: instruction description conventions field description f register ?e address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit ?e register (0 to 7) k literal ?ld, constant data or label (may be either an 8-bit or an 11-bit value) x don't care (0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in ?e register f. dest destination either the w register or the speci?d register ?e location label label name tos top of stack pc program counter pclath program counter high latch gie global interrupt enable bit wdt watchdog timer t o time-out bit pd power-down bit [ ] optional ( ) contents ? assigned to < > register bit ?ld ? in the set of italics user de?ed term (font is courier)
picmicro mid-range mcu family ds31029a-page 29-6 1997 microchip technology inc. 29.3 special function registers as source/destination the section 29. instruction sets orthogonal instruction set allows read and write of all ?e regis- ters, including special function registers. some special situations the user should be aware of are explained in the following subsections: 29.3.1 status register as destination if an instruction writes to the status register, the z, c, dc and ov bits may be set or cleared as a result of the instruction and overwrite the original data bits written. for example, executing clrf status will clear register status, and then set the z bit leaving 0000 0100b in the reg- ister. 29.3.2 pcl as source or destination read, write or read-modify-write on pcl may have the following results: read pc: pcl ? dest; pclath does not change; write pcl: pclath ? pch; 8-bit destination value ? pcl read-modify-write: pcl ? alu operand pclath ? pch; 8-bit result ? pcl where pch = program counter high byte (not an addressable register), pclath = program counter high holding latch, dest = destination, w register or register ?e f. 29.3.3 bit manipulation all bit manipulation instructions will ?st read the entire register, operate on the selected bit and then write the result back (read-modify-write (r-m-w)) the speci?d register. the user should keep this in mind when operating on some special function registers, such as ports. note: status bits that are manipulated by the device (including the interrupt ?g bits) are set or cleared in the q1 cycle. so there is no issue with executing r-m-w instructions on registers which contain these bits.
1997 microchip technology inc. ds31029a-page 29-7 section 29. instruction set instruction set 29 29.4 q cycle activity each instruction cycle (tcy) is comprised of four q cycles (q1-q4). the q cycle is the same as the device oscillator cycle (t osc ). the q cycles provide the timing/designation for the decode, read, process data, write etc., of each instruction cycle. the following diagram shows the rela- tionship of the q cycles to the instruction cycle. the four q cycles that make up an instruction cycle (tcy) can be generalized as: q1: instruction decode cycle or forced no operation q2: instruction read cycle or no operation q3: process the data q4: instruction write cycle or no operation each instruction will show the detailed q cycle operation for the instruction. figure 29-2: q cycle activity q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 tcy1 tcy2 tcy3 tosc
picmicro mid-range mcu family ds31029a-page 29-8 1997 microchip technology inc. 29.5 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k ? w status affected: c, dc, z encoding: 11 111x kkkk kkkk description: the contents of the w register are added to the eight bit literal 'k' and the result is placed in the w register . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w register example1 addlw 0x15 before instruction w = 0x10 after instruction w = 0x25 example 2 addlw myreg before instruction w = 0x10 address of myreg ? = 0x37 ? myreg is a symbol for a data memory location after instruction w = 0x47 example 3 addlw high (lu_table) before instruction w = 0x10 address of lu_table ? = 0x9375 ? lu_table is a label for an address in program memory after instruction w = 0xa3 example 4 addlw myreg before instruction w = 0x10 address of pcl ? = 0x02 ? pcl is the symbol for the program counter low byte location after instruction w = 0x12
1997 microchip technology inc. ds31029a-page 29-9 section 29. instruction set instruction set 29 addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d ? [0,1] operation: (w) + (f) ? destination status affected: c, dc, z encoding: 00 0111 dfff ffff description: add the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0xd9 fsr = 0xc2 example 2 addwf indf, 1 before instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x20 after instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x37 example 3 addwf pcl case 1: before instruction w = 0x10 pcl = 0x37 c = x after instruction pcl = 0x47 c = 0 case 2: before instruction w = 0x10 pcl = 0xf7 pch = 0x08 c = x after instruction pcl = 0x07 pch = 0x08 c = 1
picmicro mid-range mcu family ds31029a-page 29-10 1997 microchip technology inc. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w).and. (k) ? w status affected: z encoding: 11 1001 kkkk kkkk description: the contents of w register are and?d with the eight bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w register example 1 andlw 0x5f before instruction w = 0xa3 after instruction w = 0x03 ; 0101 1111 (0x5f) ; 1010 0011 (0xa3) ;---------- ------ ; 0000 0011 (0x03) example 2 andlw myreg before instruction w = 0xa3 address of myreg ? = 0x37 ? myreg is a symbol for a data memory location after instruction w = 0x23 example 3 andlw high (lu_table) before instruction w = 0xa3 address of lu_table ? = 0x9375 ? lu_table is a label for an address in program memory after instruction w = 0x83
1997 microchip technology inc. ds31029a-page 29-11 section 29. instruction set instruction set 29 andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d ? [0,1] operation: (w).and. (f) ? destination status affected: z encoding: 00 0101 dfff ffff description: and the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 andwf fsr, 1 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x17 fsr = 0x02 ; 0001 0111 (0x17) ; 1100 0010 (0xc2) ;---------- ------ ; 0000 0010 (0x02) example 2 andwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x02 fsr = 0xc2 ; 0001 0111 (0x17) ; 1100 0010 (0xc2) ;---------- ------ ; 0000 0010 (0x02) example 3 andwf indf, 1 before instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x5a after instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x15
picmicro mid-range mcu family ds31029a-page 29-12 1997 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 ? f status affected: none encoding: 01 00bb bfff ffff description: bit 'b' in register 'f' is cleared . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example 1 bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 ; 1 100 0111 ; 0 100 0111 example 2 bcf indf, 3 before instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x2f after instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x27
1997 microchip technology inc. ds31029a-page 29-13 section 29. instruction set instruction set 29 bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 ? f status affected: none encoding: 01 01bb bfff ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example 1 bsf flag_reg, 7 before instruction flag_reg =0x0a after instruction flag_reg =0x8a ; 0 000 1010 ; 1 000 1010 example 2 bsf indf, 3 before instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x20 after instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x28
picmicro mid-range mcu family ds31029a-page 29-14 1997 microchip technology inc. btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 01 10bb bfff ffff description: if bit 'b' in register 'f' is '0' then the next instruction is skipped. if bit 'b' is '0' then the next instruction (fetched during the current instruction execu- tion) is discarded, and a nop is executed instead, making this a 2 cycle instruction . words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip (2nd cycle): q1 q2 q3 q4 no operation no operation no operation no operation example 1 here false true btfsc goto flag, 4 process_code case 1: before instruction pc = address here flag= xxx0 xxxx after instruction since flag<4>= 0, pc = address true case 2: before instruction pc = address here flag= xxx1 xxxx after instruction since flag<4>=1, pc = address false
1997 microchip technology inc. ds31029a-page 29-15 section 29. instruction set instruction set 29 btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 01 11bb bfff ffff description: if bit 'b' in register 'f' is '1' then the next instruction is skipped. if bit 'b' is '1', then the next instruction (fetched during the current instruc- tion execution) is discarded and a nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip (2nd cycle): q1 q2 q3 q4 no operation no operation no operation no operation example 1 here false true btfss goto flag, 4 process_code case 1: before instruction pc = address here flag= xxx0 xxxx after instruction since flag<4>= 0, pc = address false case 2: before instruction pc = address here flag= xxx1 xxxx after instruction since flag<4>=1, pc = address true
picmicro mid-range mcu family ds31029a-page 29-16 1997 microchip technology inc. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none encoding: 10 0kkk kkkk kkkk description: call subroutine. first, the 13-bit return address (pc+1) is pushed onto the stack. the eleven bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath<4:3>. call is a two cycle instruction. words: 1 cycles: 2 q cycle activity: 1st cycle: q1 q2 q3 q4 decode read literal 'k' process data no operation 2nd cycle: q1 q2 q3 q4 no operation no operation no operation no operation example 1 here call there before instruction pc = address here after instruction tos = address here+1 pc = address there
1997 microchip technology inc. ds31029a-page 29-17 section 29. instruction set instruction set 29 clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h ? f 1 ? z status affected: z encoding: 00 0001 1fff ffff description: the contents of register 'f' are cleared and the z bit is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example 1 clrf flag_reg before instruction flag_reg=0x5a after instruction flag_reg=0x00 z=1 example 2 clrf indf before instruction fsr = 0xc2 contents of address (fsr)=0xaa after instruction fsr = 0xc2 contents of address (fsr)=0x00 z=1
picmicro mid-range mcu family ds31029a-page 29-18 1997 microchip technology inc. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? w 1 ? z status affected: z encoding: 00 0001 0xxx xxxx description: w register is cleared. zero bit (z) is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'w' example 1 clrw before instruction w = 0x5a after instruction w = 0x00 z=1
1997 microchip technology inc. ds31029a-page 29-19 section 29. instruction set instruction set 29 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler count, 1 ? t o 1 ? pd status affected: t o , pd encoding: 00 0000 0110 0100 description: clrwdt instruction clears the watchdog timer. it also clears the pres- caler count of the wdt. status bits t o and pd are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data clear wdt counter example 1 clrwdt before instruction wdt counter= x wdt prescaler =1:128 after instruction wdt counter=0x00 wdt prescaler count=0 t o =1 pd =1 wdt prescaler =1:128 note: the clrwdt instruction does not affect the assignment of the wdt prescaler.
picmicro mid-range mcu family ds31029a-page 29-20 1997 microchip technology inc. comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d ? [0,1] operation: (f ) ? destination status affected: z encoding: 00 1001 dfff ffff description: the contents of register 'f' are 1s complemented. if 'd' is 0 the result is stored in w. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 comf reg1, 0 before instruction reg1= 0x13 after instruction reg1= 0x13 w = 0xec example 2 comf indf, 1 before instruction fsr = 0xc2 contents of address (fsr)=0xaa after instruction fsr = 0xc2 contents of address (fsr)=0x55 example 3 comf reg1, 1 before instruction reg1= 0xff after instruction reg1= 0x00 z=1
1997 microchip technology inc. ds31029a-page 29-21 section 29. instruction set instruction set 29 decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? destination status affected: z encoding: 00 0011 dfff ffff description: decrement register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 example 2 decf indf, 1 before instruction fsr = 0xc2 contents of address (fsr) = 0x01 z=0 after instruction fsr = 0xc2 contents of address (fsr) = 0x00 z=1 example 3 decf cnt, 0 before instruction cnt = 0x10 w=x z=0 after instruction cnt = 0x10 w = 0x0f z=0
picmicro mid-range mcu family ds31029a-page 29-22 1997 microchip technology inc. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? destination; skip if result = 0 status affected: none encoding: 00 1011 dfff ffff description: the contents of register 'f' are decremented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, then the next instruction (fetched during the current instruction execution) is discarded and a nop is executed instead, mak- ing this a 2 cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip (2nd cycle): q1 q2 q3 q4 no operation no operation no operation no operation example here decfsz cnt, 1 goto loop continue case 1: before instruction pc = address here cnt = 0x01 after instruction cnt = 0x00 pc = address continue case 2: before instruction pc = address here cnt = 0x02 after instruction cnt = 0x01 pc = address here + 1
1997 microchip technology inc. ds31029a-page 29-23 section 29. instruction set instruction set 29 goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none encoding: 10 1kkk kkkk kkkk description: goto is an unconditional branch. the eleven bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two cycle instruction. words: 1 cycles: 2 q cycle activity: 1st cycle: q1 q2 q3 q4 decode read literal 'k'<7:0> process data no operation 2nd cycle: q1 q2 q3 q4 no operation no operation no operation no operation example goto there after instruction pc =address there
picmicro mid-range mcu family ds31029a-page 29-24 1997 microchip technology inc. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? destination status affected: z encoding: 00 1010 dfff ffff description: the contents of register 'f' are incremented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1 example 2 incf indf, 1 before instruction fsr = 0xc2 contents of address (fsr) = 0xff z=0 after instruction fsr = 0xc2 contents of address (fsr) = 0x00 z=1 example 3 incf cnt, 0 before instruction cnt = 0x10 w=x z=0 after instruction cnt = 0x10 w = 0x11 z=0
1997 microchip technology inc. ds31029a-page 29-25 section 29. instruction set instruction set 29 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? destination, skip if result = 0 status affected: none encoding: 00 1111 dfff ffff description: the contents of register 'f' are incremented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, then the next instruction (fetched during the current instruction execution) is discarded and a nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip (2nd cycle): q1 q2 q3 q4 no operation no operation no operation no operation example here incfsz cnt, 1 goto loop continue case 1: before instruction pc = address here cnt = 0xff after instruction cnt = 0x00 pc = address continue case 2: before instruction pc = address here cnt = 0x00 after instruction cnt = 0x01 pc = address here + 1
picmicro mid-range mcu family ds31029a-page 29-26 1997 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w).or. k ? w status affected: z encoding: 11 1000 kkkk kkkk description: the contents of the w register is or?d with the eight bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w register example 1 iorlw 0x35 before instruction w = 0x9a after instruction w = 0xbf z=0 example 2 iorlw myreg before instruction w = 0x9a address of myreg ? = 0x37 ? myreg is a symbol for a data memory location after instruction w = 0x9f z=0 example 3 iorlw high (lu_table) before instruction w = 0x9a address of lu_table ? = 0x9375 ? lu_table is a label for an address in program memory after instruction w = 0x9b z=0 example 4 iorlw 0x00 before instruction w = 0x00 after instruction w = 0x00 z=1
1997 microchip technology inc. ds31029a-page 29-27 section 29. instruction set instruction set 29 iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d ? [0,1] operation: (w).or. (f) ? destination status affected: z encoding: 00 0100 dfff ffff description: inclusive or the w register with register 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 iorwf result, 0 before instruction result=0x13 w = 0x91 after instruction result=0x13 w = 0x93 z=0 example 2 iorwf indf, 1 before instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x30 after instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x37 z=0 example 3 iorwf result, 1 case 1: before instruction result=0x13 w = 0x91 after instruction result=0x93 w = 0x91 z=0 case 2: before instruction result=0x00 w = 0x00 after instruction result=0x00 w = 0x00 z=1
picmicro mid-range mcu family ds31029a-page 29-28 1997 microchip technology inc. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k ? w status affected: none encoding: 11 00xx kkkk kkkk description: the eight bit literal 'k' is loaded into w register . the don? cares will assemble as 0s. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w register example 1 movlw 0x5a after instruction w = 0x5a example 2 movlw myreg before instruction w = 0x10 address of myreg ? = 0x37 ? myreg is a symbol for a data memory location after instruction w = 0x37 example 3 movlw high (lu_table) before instruction w = 0x10 address of lu_table ? = 0x9375 ? lu_table is a label for an address in program memory after instruction w = 0x93
1997 microchip technology inc. ds31029a-page 29-29 section 29. instruction set instruction set 29 movf move f syntax: [ label ] movf f,d operands: 0 f 127 d ? [0,1] operation: (f) ? destination status affected: z encoding: 00 1000 dfff ffff description: the contents of register ? is moved to a destination dependent upon the status of d? if d = 0, destination is w register. if d = 1, the destination is ?e register ? itself. d = 1 is useful to test a ?e register since status ?g z is affected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 movf fsr, 0 before instruction w = 0x00 fsr = 0xc2 after instruction w = 0xc2 z= 0 example 2 movf indf, 0 before instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x00 after instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x00 z= 1 example 3 movf fsr, 1 case 1: before instruction fsr = 0x43 after instruction fsr = 0x43 z= 0 case 2: before instruction fsr = 0x00 after instruction fsr = 0x00 z= 1
picmicro mid-range mcu family ds31029a-page 29-30 1997 microchip technology inc. movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) ? f status affected: none encoding: 00 0000 1fff ffff description: move data from w register to register 'f' . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example 1 movwf option_reg before instruction option_reg=0xff w = 0x4f after instruction option_reg=0x4f w = 0x4f example 2 movwf indf before instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x00 after instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x17
1997 microchip technology inc. ds31029a-page 29-31 section 29. instruction set instruction set 29 nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 00 0000 0xx0 0000 description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example here nop : before instruction pc = address here after instruction pc = address here + 1
picmicro mid-range mcu family ds31029a-page 29-32 1997 microchip technology inc. option load option register syntax: [ label ] option operands: none operation: (w) ? option status affected: none encoding: 00 0000 0110 0010 description: the contents of the w register are loaded in the option register. this instruction is supported for code compatibility with pic16c5x products. since option is a readable/writable register, the user can directly address it. words: 1 cycles: 1 to maintain upward compatibility with future pic16cxx products, do not use this instruction.
1997 microchip technology inc. ds31029a-page 29-33 section 29. instruction set instruction set 29 retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none encoding: 00 0000 0000 1001 description: return from interrupt. the 13-bit address at the top of stack (tos) is loaded in the pc. the global interrupt enable bit, gie (intcon<7>), is automatically set, enabling interrupts. this is a two cycle instruction. words: 1 cycles: 2 q cycle activity: 1st cycle: q1 q2 q3 q4 decode no operation process data no operation 2nd cycle: q1 q2 q3 q4 no operation no operation no operation no operation example retfie after instruction pc = tos gie = 1
picmicro mid-range mcu family ds31029a-page 29-34 1997 microchip technology inc. retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k ? w; tos ? pc status affected: none encoding: 11 01xx kkkk kkkk description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded 13-bit address at the top of stack (the return address). this is a two cycle instruction. words: 1 cycles: 2 q cycle activity: 1st cycle: q1 q2 q3 q4 decode read literal 'k' process data write to w register 2nd cycle: q1 q2 q3 q4 no operation no operation no operation no operation example here table call table ; w contains table ; offset value ? ; w now has table value addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 pc = tos = address here + 1
1997 microchip technology inc. ds31029a-page 29-35 section 29. instruction set instruction set 29 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none encoding: 00 0000 0000 1000 description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two cycle instruc- tion. words: 1 cycles: 2 q cycle activity: 1st cycle: q1 q2 q3 q4 decode no operation process data no operation 2nd cycle: q1 q2 q3 q4 no operation no operation no operation no operation example here return after instruction pc = tos
picmicro mid-range mcu family ds31029a-page 29-36 1997 microchip technology inc. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1101 dfff ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 rlf reg1,0 before instruction reg1 = 1110 0110 c =0 after instruction reg1 =1110 0110 w =1100 1100 c =1 example 2 rlf indf, 1 case 1: before instruction w= xxxx xxxx fsr = 0xc2 contents of address (fsr) = 0011 1010 c =1 after instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0111 0101 c =0 case 2: before instruction w= xxxx xxxx fsr = 0xc2 contents of address (fsr) = 1011 1001 c =0 after instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0111 0010 c =1 register f c
1997 microchip technology inc. ds31029a-page 29-37 section 29. instruction set instruction set 29 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1100 dfff ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 rrf reg1,0 before instruction reg1 = 1110 0110 w = xxxx xxxx c =0 after instruction reg1 = 1110 0110 w = 0111 0011 c =0 example 2 rrf indf, 1 case 1: before instruction w= xxxx xxxx fsr = 0xc2 contents of address (fsr) = 0011 1010 c =1 after instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 1001 1101 c =0 case 2: before instruction w= xxxx xxxx fsr = 0xc2 contents of address (fsr) = 0011 1001 c =0 after instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0001 1100 c =1 register f c
picmicro mid-range mcu family ds31029a-page 29-38 1997 microchip technology inc. sleep syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler count, 1 ? t o , 0 ? pd status affected: t o , pd encoding: 00 0000 0110 0011 description: the power-down status bit, pd is cleared. time-out status bit, t o is set. watchdog timer and its prescaler count are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation go to sleep example: sleep note: the sleep instruction does not affect the assignment of the wdt prescaler
1997 microchip technology inc. ds31029a-page 29-39 section 29. instruction set instruction set 29 sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ? w status affected: c, dc, z encoding: 11 110x kkkk kkkk description: the w register is subtracted (2s complement method) from the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w register example 1: sublw 0x02 case 1: before instruction w = 0x01 c=x z=x after instruction w = 0x01 c = 1 ; result is positive z=0 case 2: before instruction w = 0x02 c=x z=x after instruction w = 0x00 c = 1 ; result is zero z=1 case 3: before instruction w = 0x03 c=x z=x after instruction w = 0xff c = 0 ; result is negative z=0 example 2 sublw myreg before instruction w = 0x10 address of myreg ? = 0x37 ? myreg is a symbol for a data memory location after instruction w = 0x27 c = 1 ; result is positive
picmicro mid-range mcu family ds31029a-page 29-40 1997 microchip technology inc. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d ? [0,1] operation: (f) - (w) ? destination status affected: c, dc, z encoding: 00 0010 dfff ffff description: subtract (2s complement method) w register from register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in reg- ister 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1: subwf reg1,1 case 1: before instruction reg1= 3 w=2 c=x z=x after instruction reg1= 1 w=2 c = 1 ; result is positive z=0 case 2: before instruction reg1= 2 w=2 c=x z=x after instruction reg1= 0 w=2 c = 1 ; result is zero z=1 case 3: before instruction reg1= 1 w=2 c=x z=x after instruction reg1= 0xff w=2 c = 0 ; result is negative z=0
1997 microchip technology inc. ds31029a-page 29-41 section 29. instruction set instruction set 29 swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d ? [0,1] operation: (f<3:0>) ? destination<7:4>, (f<7:4>) ? destination<3:0> status affected: none encoding: 00 1110 dfff ffff description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0 the result is placed in w register. if 'd' is 1 the result is placed in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 swapf reg, 0 before instruction reg1= 0xa5 after instruction reg1= 0xa5 w = 0x5a example 2 swapf indf, 1 before instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x20 after instruction w = 0x17 fsr = 0xc2 contents of address (fsr) = 0x02 example 3 swapf reg, 1 before instruction reg1= 0xa5 after instruction reg1= 0x5a
picmicro mid-range mcu family ds31029a-page 29-42 1997 microchip technology inc. tris load tris register syntax: [ label ] tris f operands: 5 f 7 operation: (w) ? tris register f; status affected: none encoding: 00 0000 0110 0fff description: the instruction is supported for code compatibility with the pic16c5x prod- ucts. since tris registers are readable and writable, the user can directly address them. words: 1 cycles: 1 example to maintain upward compatibility with future pic16cxx products, do not use this instruction.
1997 microchip technology inc. ds31029a-page 29-43 section 29. instruction set instruction set 29 xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w).xor. k ? w status affected: z encoding: 11 1010 kkkk kkkk description: the contents of the w register are xor?d with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w register example 1 xorlw 0xaf ; 1010 1111 (0xaf) before instruction ; 1011 0101 (0xb5) w = 0xb5 ; --------- ------ after instruction ; 0001 1010 (0x1a) w = 0x1a z=0 example 2 xorlw myreg before instruction w = 0xaf address of myreg ? = 0x37 ? myreg is a symbol for a data memory location after instruction w = 0x18 z=0 example 3 xorlw high (lu_table) before instruction w = 0xaf address of lu_table ? = 0x9375 ? lu_table is a label for an address in program memory after instruction w = 0x3c z=0
picmicro mid-range mcu family ds31029a-page 29-44 1997 microchip technology inc. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d ? [0,1] operation: (w).xor. (f) ? destination status affected: z encoding: 00 0110 dfff ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in regis- ter 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 xorwf reg, 1 ; 1010 1111 (0xaf) before instruction ; 1011 0101 (0xb5) reg= 0xaf w = 0xb5 ; --------- ------ ; 0001 1010 (0x1a) after instruction reg= 0x1a w = 0xb5 example 2 xorwf reg, 0 ; 1010 1111 (0xaf) before instruction ; 1011 0101 (0xb5) reg= 0xaf w = 0xb5 ; --------- ------ ; 0001 1010 (0x1a) after instruction reg= 0xaf w = 0x1a example 3 xorwf indf, 1 before instruction w = 0xb5 fsr = 0xc2 contents of address (fsr) = 0xaf after instruction w = 0xb5 fsr = 0xc2 contents of address (fsr) = 0x1a
1997 microchip technology inc. ds31029a-page 29-45 section 29. instruction set instruction set 29 29.6 design tips question 1: how can i modify the value of w directly? i want to decrement w. answer 1: there are a few possibilities, two are: 1. for the midrange devices, there are several instructions that work with a literal and w. for instance, if it were desired to decrement w, this can be done with an addlw 0xff . (the 0x pre? denotes hex to the assembler) 2. notice that all of the instructions can modify a value right where it sits in the ?e register. this means you can decrement it right where it is. you do not even need to move it to w. if you want to decrement it and move it somewhere else, then you make w the desti- nation of the decrement ( decf register,w) then put it where you want it. it is the same number of instructions as a straight move, but it gets decremented along the way. question 2: is there any danger in using the tris instruction for the pic16cxxx since there is a warning in the data book suggesting it not be used? answer 2: for code compatibility and upgrades to later parts, the use of the tris instruction is not recom- mended. you should note the tris instruction is limited to ports a, b and c. future devices may not support these instructions. question 3: do i have to switch to bank1 of data memory before using the tris instruc- tion (for parts with tris registers in the memory map)? answer 3: no. the tris instruction is bank independent. again the use of the tris instruction is not rec- ommended. question 4: i have seen references to ?ead-modify-write instructions in your data sheet, but i do not know what that is. can you explain what it is and why i need to know this? answer 4: an easy example of a read-modify-write (r-m-w) instruction is the bit clear instruction bcf . you might think that the processor just clears the bit, which on a port output pin would clear the pin. what actually happens is the whole port (or register) is ?st read, then the bit is cleared, then the new modi?d value is written back to the port (or register). actually, any instruction that depends on a value currently in the register is going to be a read-modify-write instruction. this includes addwf, subwf, bcf, bsf, incf, xorwf , etc... instructions that do not depend on the current register value, like movwf, clrf , and so on are not r-m-w instructions. one situation where you would want to consider the affects of a r-m-w instruction is a port that is continuously changed from input to output and back. for example, say you have trisb set to all outputs, and write all ones to the portb register, all of the portb pins will go high. now, say you turn pin rb3 into an input, which happens to go low. a bcf portb,6 is then executed to drive pin rb6 low. if you then turn rb3 back into an output, it will now drive low, even though the last value you put there was a one. what happened was that the bcf of the other pin (rb6) caused the whole port to be read, including the zero on rb3 when it was an input. then, bit 6 was changed as requested, but since rb3 was read as a zero, zero will also be placed back into that port latch, overwriting the one that was there before. when the pin is turned back into an output, the new value was re?cted.
picmicro mid-range mcu family ds31029a-page 29-46 1997 microchip technology inc. question 5: when i perform a bcf other pins get cleared in the port. why? answer 5: there are a few possibilities, two are: 1. another case where a r-m-w instruction may seem to change other pin values unexpect- edly can be illustrated as follows: suppose you make portc all outputs and drive the pins low. on each of the port pins is an led connected to ground, such that a high output lights it. across each led is a 100 m f capacitor. let's also suppose that the processor is running very fast, say 20 mhz. now if you go down the port setting each pin in order; bsf portc,0 then bsf portc,1 then bsf portc,2 and so on, you may see that only the last pin was set, and only the last led actually turns on. this is because the capacitors take a while to charge. as each pin was set, the pin before it was not charged yet and so was read as a zero. this zero is written back out to the port latch (r-m-w, remember) which clears the bit you just tried to set the instruction before. this is usually only a concern at high speeds and for successive port operations, but it can happen so take it into consid- eration. 2. if this is on a pic16c7x device, you may not have con?ured the i/o pins properly in the adcon1 register. if a pin is con?ured for analog input, any read of that pin will read a zero, regardless of the voltage on the pin. this is an exception to the normal rule that the pin state is always read. you can still con?ure an analog pin as an output in the tris reg- ister, and drive the pin high or low by writing to it, but you will always read a zero. therefore if you execute a read-modify-write instruction (see previous question) all analog pins are read as zero, and those not directly modi?d by the instruction will be written back to the port latch as zero. a pin con?ured as analog is expected to have values that may be nei- ther high nor low to a digital pin, or ?ating. floating inputs on digital pins are a no-no, and can lead to high current draw in the input buffer, so the input buffer is disabled.
1997 microchip technology inc. ds31029a-page 29-47 section 29. instruction set instruction set 29 29.7 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the instruc- tion set are: currently no related application notes
picmicro mid-range mcu family ds31029a-page 29-48 1997 microchip technology inc. 29.8 revision history revision a this is the initial released revision of the instruction set description.
1997 microchip technology inc. ds31030a page 30-1 m electrical speci?ations 30 section 30. electrical speci?ations highlights 30.1 introduction ............................................................................................................... ...30-2 30.2 absolute maximums.....................................................................................................30-3 30.3 device selection table .................................................................................................30-4 30.4 device voltage speci?ations ......................................................................................30-5 30.5 device current speci?ations ......................................................................................30-6 30.6 input threshold levels .................................................................................................30-9 30.7 i/o current speci?ations ..........................................................................................30-10 30.8 output drive levels....................................................................................................30-1 1 30.9 i/o capacitive loading...............................................................................................30-12 30.10 data eeprom / flash ...............................................................................................30-13 30.11 lcd....................................................................................................................... .....30-14 30.12 comparators and voltage reference .........................................................................30-15 30.13 timing parameter symbology....................................................................................30-16 30.14 example external clock timing waveforms and requirements ................................30-17 30.15 example power-up and reset timing waveforms and requirements.......................30-19 30.16 example timer0 and timer1 timing waveforms and requirements .........................30-20 30.17 example ccp timing waveforms and requirements................................................30-21 30.18 example parallel slave port (psp) timing waveforms and requirements ...............30-22 30.19 example ssp and master ssp spi mode timing waveforms and requirements ....30-23 30.20 example ssp i 2 c mode timing waveforms and requirements ................................30-27 30.21 example master ssp i 2 c mode timing waveforms and requirements ....................30-30 30.22 example usart/sci timing waveforms and requirements ....................................30-32 30.23 example 8-bit a/d timing waveforms and requirements .........................................30-34 30.24 example 10-bit a/d timing waveforms and requirements .......................................30-36 30.25 example slope a/d timing waveforms and requirements .......................................30-38 30.26 example lcd timing waveforms and requirements ................................................30-40 30.27 related application notes..........................................................................................30-41 30.28 revision history .........................................................................................................3 0-42
picmicro mid-range mcu family ds31030a-page 30-2 1997 microchip technology inc. 30.1 introduction this section is intended to show you the electrical speci?ations that may be speci?d in a par- ticular device data sheet and what is meant by the speci?ation. this section is not intended to give the values of these speci?ations. for the device speci? values you must refer to the devices data sheet. all values show in this section should be considered as example values. in the description of the device and the functional modules (previous sections), there have been references to electrical speci?ation parameters. these references have been hyperlinked in the electronic version to aid in the use of this manual. throughout this section, certain terms will be used. table 30-1 shows the conventions that will be used. table 30-1: term conventions note: before starting any design, microchip highly recommends that you acquire the most recent copy of the device data sheet and review the electrical speci?ations to ensure that they will meet your requirements. term description pic16 c xxx for devices tested to standard voltage range pic16 lc xxx for devices tested to extended voltage range pic16 f xxx for devices tested to standard voltage range pic16 lf xxx for devices tested to extended voltage range pic16 cr xxx for devices tested to standard voltage range pic16 lcr xxx for devices tested to extended voltage range pic16xxxx- 04 for devices that have been tested up to 4 mhz operation pic16xxxx- 08 for devices that have been tested up to 8 mhz operation pic16xxxx- 10 for devices that have been tested up to 10 mhz operation pic16xxxx- 20 for devices that have been tested up to 20 mhz operation lp osc for devices con?ured with the lp device oscillator selected xt osc for devices con?ured with the xt device oscillator selected hs osc for devices con?ured with the hs device oscillator selected rc osc for devices con?ured with the rc device oscillator selected commercial for devices with the commercial temperature range grading (0?c t a +70?c) industrial for devices with the industrial temperature range grading (-40?c t a +85?c) extended for devices with the extended temperature range grading (-40?c t a +125?c)
1997 microchip technology inc. ds31030a-page 30-3 section 30. electrical specifications electrical speci?ations 30 30.2 absolute maximums the absolute maximum ratings specify the worst case conditions that can be applied to the device. these ratings are not meant as operational speci?ations, and stresses above the listed values may cause damage to the device. speci?ations are not always stand-alone, that is, the speci?ation may have other requirements as well. an example of this is the ?aximum current sourced/sunk by any i/o pin? the number of i/o pins that can be sinking/sourcing current, at any one time, is dependent upon the maximum current sunk/source by the port(s) (combined) and the maximum current into the v dd pin or out of the v ss pin. in this example, the physical reason is the power and ground bus width to the i/o ports and internal logic. if these speci?ations are exceeded, then electromigration may occur on these power and ground buses. over time electromigration would cause these buses to open (be dis- connected from the pin), and therefore cause the logic attached to these buses to stop operating. so exceeding the absolute speci?ations may cause device reliability issues. input clamp current is de?ed as the current through the diode to v ss /v dd if pin voltage exceeds speci?ation. example absolute maximum ratings ? ambient temperature under bias........................................................................... . -55 to +125?c storage temperature .......................................................................................... -65?c to +150?c voltage on any pin with respect to v ss (except v dd , mclr , and ra4)..... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ....................................................................... -0.3 to +7.5v voltage on mclr with respect to v ss (2) ...................................................................... 0 to +14v voltage on ra4 with respect to vss .............................................................................. 0 to +14v total power dissipation (1) .................................................................................................... 1.0w maximum current out of v ss pin ...................................................................................... 300 ma maximum current into v dd pin ......................................................................................... 250 ma input clamp current, i ik (v i < 0 or v i > v dd ).................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................. 20 ma maximum output current sunk by any i/o pin..................................................................... 25 ma maximum output current sourced by any i/o pin ............................................................... 25 ma maximum current sunk by porta, portb, and porte (combined)............................. 200 ma maximum current sourced by porta, portb, and porte (combined) ....................... 200 ma maximum current sunk by portc and portd (combined) ........................................... 200 ma maximum current sourced by portc and portd (combined)...................................... 200 ma maximum current sourced by portc and portd (combined)...................................... 200 ma maximum current sourced by portf and portg (combined) ...................................... 100 ma maximum current sourced by portf and portg (combined) ...................................... 100 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd - v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when apply- ing a ?ow level to the mclr pin rather than pulling this pin directly to v ss . ? notice: stresses above those listed under ?bsolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?a- tion is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
picmicro mid-range mcu family ds31030a-page 30-4 1997 microchip technology inc. 30.3 device selection table this table in the device data sheet is intended to assist you in determining which oscillators are tested for which devices, and some of the speci?ations that are tested. any oscillator may be selected at time of programming, but only the speci?d oscillator is tested by microchip. since the rc and xt oscillators are only rated to 4 mhz, they are only tested on the -04 (4 mhz) devices. picmicros rated for 10 mhz or 20 mhz are only tested in hs mode. in table 30-2 the i pd is grayed out for the hs mode since there is not an i pd test point within the voltage range of the hs oscillator. the value shown is a typical value from characterization. battery applications usually require an extended voltage range. devices marked lc have an extended voltage range and have the rc, xt, and lp oscillators tested. windowed devices are superset devices and have had the oscillators tested to all the speci?a- tion ranges of the -04, -20, and lc devices. the temperature range that the device is tested to should be considered commercial, though at a later time they may be tested to industrial or extended temperature levels. table 30-2: example cross reference of device speci?ations for oscillator con?urations and frequencies of operation (commercial devices) osc pic16cxxx-04 pic16cxxx-10 pic16cxxx-20 pic16lcxxx-04 windowed devices rc v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 ma max. at 3.0v i pd : 5 m a max. at 3v freq: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. xt v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 ma max. at 3.0v i pd : 5 m a max. at 3v freq: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not recommended for use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 10 ma max. at 5.5v i dd : 20 ma max. at 5.5v i dd : 20 ma max. at 5.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v freq: 4 mhz max. freq: 10 mhz max. freq: 20 mhz max. freq: 20 mhz max. lp v dd : 4.0v to 6.0v i dd : 52.5 m a typ. at 32 khz, 4.0v i pd : 0.9 m a typ. at 4.0v freq: 200 khz max. not recommended for use in lp mode not recommended for use in lp mode v dd : 2.5v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v freq: 200 khz max. v dd : 2.5v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recommended that the user select the device type that ensures the speci?ations required. note: devices that are marked with engineering sample (eng smp) are tested to the cur- rent engineering test program at time of the device testing. there is no implied war- ranty that these devices have been tested to any or all speci?ations in the device data sheet.
1997 microchip technology inc. ds31030a-page 30-5 section 30. electrical specifications electrical speci?ations 30 30.4 device voltage speci?ations these speci?ations relate to the device v dd and the device power-up and function. supply voltage is the voltage level that must be applied to the device for the proper functional operation. ram data retention voltage is the level that the device voltage may be at and still retain the data value. v dd start voltage to ensure the internal power-on reset signal, is the level that v dd must start from to ensure that the por circuitry will operate properly. v dd rise rate to ensure internal power-on reset signal, is the minimum slope that v dd must rise at to cause the por circuitry to trip. brown-out reset voltage is the voltage range where the brown-out circuitry may trip. when the bor circuitry trips, the device will either be in brown-out reset, or just came out of brown-out reset. table 30-3: example dc characteristics dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial and -40?c t a +85?c for industrial -40?c t a +125?c for extended param no. symbol characteristic min typ? max units conditions v dd supply voltage d001 pic16 c xxx 4.0 6.0 v xt, rc and lp osc mode pic16 lc xxx 2.5 6.0 v d001a pic16 c xxx 4.5 5.5 v hs osc mode d002 v dr ram data retention voltage (1) 1.5 v d003 v por v dd start voltage to ensure internal power-on reset signal ? ss v see section on power-on reset for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 v/ms see section on power-on reset for details v bor brown-out reset voltage d005 3.7 4.0 4.3 v boden bit in con?uration word enabled d005a 3.7 4.0 4.4 v extended temperature range devices only ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data.
picmicro mid-range mcu family ds31030a-page 30-6 1997 microchip technology inc. 30.5 device current speci?ations i dd is the current ( i ) that the device consumes when the device is in operating mode. this test is taken with all i/o as inputs, either pulled high or low. that is, there are no ?ating inputs, nor are any pins driving an output (with a load). i pd is the current ( i ) that the device consumes when the device is in sleep mode (power-down), referred to as power-down current. these tests are taken with all i/o as inputs, either pulled high or low. that is, there are no ?ating inputs, nor are any pins driving an output (with a load), weak pull-ups are disabled. a device may have certain features and modules that can operate while the device is in sleep mode. some on these modules are: watchdog timer (wdt) brown-out reset (bor) circuitry timer1 analog to digital converter lcd module comparators voltage reference when all features are disabled, the device will consume the lowest possible current (the leakage current). if any of these features are operating while the device is in sleep, a higher current will occur. the difference between the lowest power mode (everything off) at only that one feature enabled (such as the wdt) is what we call the module differential current . if more then one feature is enabled then the expected current can easily be calculated as: the base current (every- thing disabled and in sleep mode) plus all module differential currents (delta currents). example 30-1 shows an example of calculating the typical currents for a device at 5v, with the wdt and timer1 oscillator enabled. example 30-1: i pd calculations with wdt and timer1 oscillator enabled (@ 5v) base current 14 na ; device leakage current wdt delta current 14 m a ; 14 m a - 14 na = 14 m a timer1 delta current 22 m a ; 22 m a - 14 na = 22 m a total sleep current 36 m a ;
1997 microchip technology inc. ds31030a-page 30-7 section 30. electrical specifications electrical speci?ations 30 table 30-4: example dc characteristics dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial and -40?c t a +85?c for industrial -40?c t a +125?c for extended param no. symbol characteristic min typ? max units conditions d010 d010a d010c d013 i dd supply current (2,4,5) 2.7 2.0 22.5 7.7 13.5 5 3.8 48 5 30 ma ma m a ma ma xt, rc osc con?uration (pic16 c xxx- 04 ) f osc = 4 mhz, v dd = 5.5v f osc = 4 mhz, v dd = 3.0v lp osc con?uration f osc = 32 khz, v dd = 3.0v, wdt disabled intrc osc con?uration, fosc = 4 mhz, v dd = 5.5v hs osc con?uration (pic16 c xxx- 20 ) fosc = 20 mhz, v dd = 5.5v d020 d021 d021a d021b i pd power-down current (3,5) 10.5 7.5 1.5 0.9 1.5 0.9 1.5 42 30 21 13.5 24 18 m a m a m a m a m a m a m a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -0 c to +70 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 4.0v, wdt disabled, -40 c to +85 c v dd = 3.0v, wdt disabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -40 c to +125 c * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: not applicable. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from character- ization and is for design guidance only. this is not tested.
picmicro mid-range mcu family ds31030a-page 30-8 1997 microchip technology inc. table 30-5: example dc characteristics dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial, -40?c t a +85?c for industrial and -40?c t a +125?c for extended param no. symbol characteristic min typ? max units conditions module differential current (5) d022 d i wdt watchdog timer 6.0 20 25 m a m a v dd = 4.0v -40 c to +125 c d022a d i bor brown-out reset 350 425 m a boden bit is clear, v dd = 5.0v d023 d i comp comparator (per comparator) 85 100 m av dd = 4.0v d023a d i vref voltage reference 94 300 m av dd = 4.0v d024 d i lcdrc lcd internal rc osc enabled 6.0 20 m av dd = 3.0v d024a d i lcdvg lcd voltage generation tbd tbd m av dd = 3.0v d025 d i t 1 osc timer1 oscillator 3.1 6.5 m av dd = 3.0v d026 d i ad a/d converter 1.0 m a a/d on, not converting d027 d i sad slope a/d (total) 165 * 250 * m a refoff = 0 d027a d i sadvr slope a/d bandgap voltage reference 20 * 30 * m a refoff = 0 d027b d i sadcdac slope a/d programmable current source 50 * 70 * m a adcon1<7:4> = 1111 b d027c d i sadsref slope a/d reference voltage divider 55 * 85 * m a adoff = 0 d027d d i sadcmp slope a/d comparator 40 * 65 * m a adoff = 0 ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested.
1997 microchip technology inc. ds31030a-page 30-9 section 30. electrical specifications electrical speci?ations 30 30.6 input threshold levels the input low voltage (v il ) is the voltage level that will be read as a logic ?? an input may not read a ? at a voltage level above this. all designs should be to the speci?ation since device to device (and to a much lesser extent pin to pin) variations will cause this level to vary. the input high voltage (v ih ) is the voltage level that will be read as a logic ?? an input may read a ? at a voltage level below this. all designs should be to the speci?ation since device to device (and to a much lesser extent pin to pin) variations will cause this level to vary. the i/o pins with ttl levels are shown with two speci?ations. one is the industry standard ttl speci?ation, which is speci?d for the voltage range of 4.5v to 5.5v. the other is a speci?ation that operates over the entire voltage range of the device. the better of these two speci?ations may be used in the design. table 30-6: example dc characteristics dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial, -40?c t a +85?c for industrial and -40?c t a +125?c for extended operating voltage v dd range as described in dc spec table 30-3 . param no. symbol characteristic min typ? max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss 0.15v dd v for entire v dd range (4) d030a 0.8 v 4.5v v dd 5.5v (4) d031 with schmitt trigger buffer v ss 0.2v dd v for entire v dd range d032 mclr , osc1 (rc mode) v ss 0.2v dd v d033 osc1 (xt, hs and lp modes) (1) v ss 0.3v dd v v ih input high voltage i/o ports: d040 with ttl buffer 0.25v dd + 0.8v ? dd v for entire v dd range (4) d040a 2.0 v dd v 4.5v v dd 5.5v (4) d041 with schmitt trigger buffer 0.8v dd ? dd v for entire v dd range d042 mclr 0.8v dd ? dd v d042a osc1 (xt, hs and lp modes) (1) 0.7v dd ? dd v d043 osc1 (rc mode) 0.9v dd ? dd v d050 v hys hysteresis of schmitt trigger inputs tbd v ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the picmicro be driven with an external clock while in rc mode. 2: not applicable. 3: not applicable. 4: the better of the two speci?ations may be used. for v il this would be the higher voltage and for v ih this would be the lower voltage.
picmicro mid-range mcu family ds31030a-page 30-10 1997 microchip technology inc. 30.7 i/o current speci?ations the port/gio weak pull-up current is the additional current that the device will draw when the weak pull-ups are enabled. leakage currents are the currents that the device consumes, since the devices are manufac- tured in the real world and do not adhere to their ideal characteristics. ideally there should be no current on an input, but due to the real world there is always some parasitic path that consumes negligible current. table 30-7: example dc characteristics dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial, -40?c t a +85?c for industrial and -40?c t a +125?c for extended operating voltage v dd range as described in dc spec table 30-3 . param no. symbol characteristic min typ? max units conditions i il input leakage current (2,3) d060 i/o ports 1 m a vss v pin v dd , pin at hi-impedance d060a cdac 1 m a vss v pin v dd , pin at hi-impedance d061 mclr 5 m a vss v pin v dd d063 5 m a vss v pin v dd , xt, hs and lp osc modes i pu weak pull-up current d070 i purb portb weak pull-up current 50 250 400 m av dd = 5v, v pin = v ss d070a i pugio gio weak pull-up current 50 250 400 m av dd = 5v, v pin = v ss programmable current source (slope a/d devices) cdac pin = 0v d160 output current 18.75 33.75 48.75 m a adcon1<7:4> = 1111 b (full-scale) d160a 1.25 2.25 3.25 m a adcon1<7:4> = 0001 b (1 lsb) d160b -0.5 0 0.5 m a adcon1<7:4> = 0000 b (zero-scale) ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the picmicro be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d lev- els represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
1997 microchip technology inc. ds31030a-page 30-11 section 30. electrical specifications electrical speci?ations 30 30.8 output drive levels the output low voltage (v ol ) of an i/o pin depends on the external connections to that i/o. if an i/o pin is shorted to v dd , no matter the drive capability of the i/o pin, a low level would not be reached (and the device would consume excessive drive current). the v ol is the output voltage that the i/o pin will drive, given the i/o does not need to sink more then the i ol current (at the speci?d device voltage) as speci?d in the conditions portion of the speci?ation. the output high voltage (v oh ) of an i/o pin depends on the external connections to that i/o. if an i/o pin is shorted to v ss , no matter the drive capability of the i/o pin, a high level would not be reached (and the device would consume excessive drive current). the v oh is the output volt- age that the i/o pin will drive, given the i/o does not need to source more then the i oh current (at the speci?d device voltage) as speci?d in the conditions portion of the speci?ation. table 30-8: example dc characteristics dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial, -40?c t a +85?c for industrial and -40?c t a +125?c for extended operating voltage v dd range as described in dc spec table 30-3 . param no. symbol characteristic min typ? max units conditions v ol output low voltage d080 i/o ports 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clkout (rc mode) 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d083a 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c v oh output high voltage (3) d090 i/o ports v dd - 0.7 v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd - 0.7 v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clkout (rc mode) v dd - 0.7 v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d092a v dd - 0.7 v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d150 v od open-drain high voltage 12 v ra4 pin programmable current source d170 v pcs output voltage range vss v dd - 1.4 v cdac pin d171 sn pcs output voltage sensitivity - 0.1 - 0.01 %/v vss v cdac v dd - 1.4 bandgap reference d180 v bgr output voltage range 1.14 1.19 1.24 v on an0 pin when amuxoe =1 and adcs3:adsc0 = 0100b ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the picmicro be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d lev- els represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
picmicro mid-range mcu family ds31030a-page 30-12 1997 microchip technology inc. 30.9 i/o capacitive loading these speci?ations indicate the conditions that the i/o pins have on them from the device tester. these loadings effect the speci?ations for the timing speci?ations. if the loading in you appli- cation are different, then you will need to determine how this will effect the characteristic of the device in your system. capacitances less then these speci?ations should not have effects on a system. table 30-9: example dc characteristics dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial -40?c t a +85?c for industrial and -40?c t a +125?c for extended operating voltage v dd range as described in dc spec table 30-3 . param no. symbol characteristic min typ? max units conditions capacitive loading specs on output pins d100 c osc 2 osc2 pin 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 c io all i/o pins and osc2 (in rc mode) 50 pf to meet the timing speci?ations of the device d102 c b scl, sda 400 pf in i 2 c mode ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the picmicro be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d lev- els represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
1997 microchip technology inc. ds31030a-page 30-13 section 30. electrical specifications electrical speci?ations 30 30.10 data eeprom / flash table 30-10: example data eeprom / flash characteristics dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial, -40?c t a +85?c for industrial and -40?c t a +125?c for extended operating voltage v dd range as described in dc spec table 30-3 . param no. symbol characteristic min typ? max units conditions data eeprom memory d120 e d endurance 1m 10m e/w 25 c at 5v d121 v drw v dd for read/write v min 6.0 v v min = minimum operating voltage d122 t dew erase/write cycle time 10 ms program flash memory d130 e p endurance 100 1000 e/w d131 v pr v dd for read v min 6.0 v v min = minimum operating voltage d132 v pew v dd for erase/write 4.5 5.5 v d133 t pew erase/write cycle time 10 ms ? data in ?yp column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
picmicro mid-range mcu family ds31030a-page 30-14 1997 microchip technology inc. 30.11 lcd table 30-11: example lcd module electrical characteristics table 30-12: example v lcd charge pump electrical characteristics dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial, -40?c t a +85?c for industrial and -40?c t a +125?c for extended operating voltage v dd range as described in dc spec table 30-3 . param no. symbol characteristic min typ? max units conditions d200 v lcd 3 lcd voltage on pin v lcd 3 v dd - 0.3 vss + 7.0 v d201 v lcd 2 lcd voltage on pin v lcd 2 v lcd 3v d202 v lcd 1 lcd voltage on pin v lcd 1 v dd v d210 r com com output source impedance 1k w com outputs d211 r seg seg output source impedance 10k w seg outputs d220 v oh output high voltage max (v lcdn ) - 0.1 max (v lcdn ) v com outputs i oh = 25 m a seg outputs i oh = 3 m a d221 v ol output low voltage min (v lcdn ) min (v lcdn ) + 0.1 v com outputs i ol = 25 m a seg outputs i ol = 3 m a ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: 0 ohm source impedance at v lcd . dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial, -40?c t a +85?c for industrial and -40?c t a +125?c for extended operating voltage v dd range as described in dc spec table 30-3 . param no. symbol characteristic min typ max units conditions d250 i vadj vlcdadj regulated current output 10 m a d251 ivr vlcdadj current consumption 20 m a d252 d i vadj d v dd vlcdadj current v dd rejection 0.1/1 m a/v d253 d i vadj d t vlcdadj current variation with tem- perature 0.1/70 m a/?c d260 (1) r vadj vlcdadj external resistor 100 230 k w d265 v vadj vlcdadj voltage limits 1.0 2.3 v d271 (1) c ecpc external charge pump capacitance 0.5 m f note 1: for design guidance only.
1997 microchip technology inc. ds31030a-page 30-15 section 30. electrical specifications electrical speci?ations 30 30.12 comparators and voltage reference table 30-13: example comparator characteristics table 30-14: example voltage reference characteristics dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial, -40?c t a +85?c for industrial and -40?c t a +125?c for extended operating voltage v dd range as described in dc spec table 30-3 . param no. symbol characteristics min typ max units comments d300 v ioff input offset voltage 5.0 10 mv d301 v icm input common mode voltage 0 v dd - 1.5 v d302 cmrr common mode rejection ratio 35 70 db 300 t resp response time (1) pic16 c xxx 150 400 ns 300a pic16 lc xxx 210 600 ns 301 t mc 2 ov comparator mode change to output valid 10 m s note 1: response time measured with one comparator input at (v dd - 1.5)/2 while the other input transitions from v ss to v dd . dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial, -40?c t a +85?c for industrial and -40?c t a +125?c for extended operating voltage v dd range as described in dc spec table 30-3 . param no. symbol characteristics min typ max units comments d310 v res resolution v dd /32 v dd /24 v d311 vr aa absolute accuracy 1/4 1/2 lsb lsb low range (vrr = 1) high range (vrr = 0) d312 vr ur unit resistor value (r) 2k w 310 t set settling time (1) 10 m s note 1: settling time measured while vrr = 1 and vr3:vr0 transitions from 0000 to 1111 .
picmicro mid-range mcu family ds31030a-page 30-16 1997 microchip technology inc. 30.13 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 30-1: example load conditions 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 load condition 2
1997 microchip technology inc. ds31030a-page 30-17 section 30. electrical specifications electrical speci?ations 30 30.14 example external clock timing waveforms and requirements figure 30-2: example external clock timing waveforms table 30-15: example external clock timing requirements param. no. symbol characteristic min typ? max units conditions 1a fosc external clkin frequency (1) dc 4 mhz xt and rc osc pic16 c xxx- 04 pic16 lc xxx- 04 dc 10 mhz hs osc pic16 c xxx- 10 dc 20 mhz pic16 c xxx- 20 dc 200 khz lp osc pic16 lc xxx- 04 oscillator frequency (1) dc 4 mhz rc osc pic16 c xxx- 04 pic16 lc xxx- 04 0.1 4 mhz xt osc pic16 c xxx- 04 pic16 lc xxx- 04 4 10 mhz hs osc pic16 c xxx- 10 4 20 mhz pic16 c xxx- 20 5 200 khz lp osc mode pic16 lc xxx- 04 1 tosc external clkin period (1) 250 ns xt and rc osc pic16 c xxx- 04 pic16 lc xxx- 04 100 ns hs osc pic16 c xxx- 10 50 ns pic16 c xxx- 20 5 m s lp osc pic16 lc xxx- 04 oscillator period (1) 250 ns rc osc pic16 c xxx- 04 pic16 lc xxx- 04 250 10,000 ns xt osc pic16 c xxx- 04 pic16 lc xxx- 04 100 50 250 250 ns ns hs osc pic16 c xxx- 10 pic16 c xxx- 20 5 m s lp osc pic16 lc xxx- 04 2 t cy instruction cycle time (1) 200 dc ns t cy = 4/f osc 3 tosl, tosh external clock in (osc1) high or low time 50 ns xt osc pic16 c xxx- 04 60 ns xt osc pic16 lc xxx- 04 2.5 m s lp osc pic16 lc xxx- 04 15 ns hs osc pic16 c xxx- 20 4 tosr, tosf external clock in (osc1) rise or fall time ? 25 ns xt osc pic16 c xxx- 04 ? 50 ns lp osc pic16 lc xxx- 04 15 ns hs osc pic16 c xxx- 20 ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4
picmicro mid-range mcu family ds31030a-page 30-18 1997 microchip technology inc. figure 30-3: example clkout and i/o timing waveforms table 30-16: example clkout and i/o timing requirements param. no. symbol characteristic min typ? max units conditions 10 tosh2ckl osc1 - to clkout 75 200 ns (1) 11 tosh2ckh osc1 - to clkout - 75 200 ns (1) 12 tckr clkout rise time 35 100 ns (1) 13 tckf clkout fall time 35 100 ns (1) 14 tckl2iov clkout to port out valid 0.5t cy + 20 ns (1) 15 tiov2ckh port in valid before clkout - 0.25t cy + 25 ns (1) 16 tckh2ioi port in hold after clkout - 0ns (1) 17 tosh2iov osc1 - (q1 cycle) to port out valid 50 150 ns 18 tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) pic16 c xxx 100 ns 18a pic16 lc xxx 200 ns 19 tiov2osh port input valid to osc1 - (i/o in setup time) 0ns 20 tior port output rise time pic16 c xxx 10 25 ns 20a pic16 lc xxx 60 ns 21 tiof port output fall time pic16 c xxx 10 25 ns 21a pic16 lc xxx 60 ns 22?? tinp int pin high or low time t cy ns 23?? trbp rb7:rb4 change int high or low time t cy ns 24?? trcp rc7:rc4 change int high or low time 20 ns ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ??these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 30-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
1997 microchip technology inc. ds31030a-page 30-19 section 30. electrical specifications electrical speci?ations 30 30.15 example power-up and reset timing waveforms and requirements figure 30-4: example reset, watchdog timer, oscillator start-up timer and power-up timer timing waveforms figure 30-5: brown-out reset timing table 30-17: example reset, watchdog timer, oscillator start-up timer, brown-out reset, and power-up timer requirements param. no. symbol characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 m sv dd = 5v, -40?c to +125?c 31 twdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40?c to +125?c 32 tost oscillation start-up timer period 1024t osc t osc = osc1 period 33 tpwrt power up timer period 28 72 132 ms v dd = 5v, -40?c to +125?c 34 t ioz i/o hi-impedance from mclr low or watchdog timer reset 2.1 m s 35 t bor brown-out reset pulse width 100 m sv dd b vdd (see d005 ) ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 30-1 for load conditions. v dd bv dd 35
picmicro mid-range mcu family ds31030a-page 30-20 1997 microchip technology inc. 30.16 example timer0 and timer1 timing waveforms and requirements figure 30-6: example timer0 and timer1 external clock timings waveforms table 30-18: example timer0 and timer1 external clock requirements param no. symbol characteristic min typ ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns with prescaler 10 ns 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns with prescaler 10 ns 42 tt0p t0cki period g reater of : 20 m s or t cy + 40 n ns n = prescale value (1, 2, 4,..., 256) 45 tt1h t1cki high time synchronous, no prescaler 0.5t cy + 20 ns synchronous, with prescaler pic16 c xxx 15 ns pic16 lc xxx 25 ns asynchronous pic16 c xxx 30 ns pic16 lc xxx 50 ns 46 tt1l t1cki low time synchronous, no prescaler 0.5t cy + 20 ns synchronous, with prescaler pic16 c xxx 15 ns pic16 lc xxx 25 ns asynchronous pic16 c xxx 2t cy ns pic16 lc xxx 47 tt1p t1cki input period synchronous g reater of : 20 m s or t cy + 40 n ns n = prescale value (1, 2, 4, 8) asynchronous greater of: 20 m s or 4t cy ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting the t1oscen bit) dc 200 khz 48 tcke2tmr i delay from external clock edge to timer increment 2tosc 7tosc ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 30-1 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t1cki tmr0 or tmr1
1997 microchip technology inc. ds31030a-page 30-21 section 30. electrical specifications electrical speci?ations 30 30.17 example ccp timing waveforms and requirements figure 30-7: example capture/compare/pwm timings waveforms table 30-19: example capture/compare/pwm requirements param. no. symbol characteristic min typ? max units conditions 50 tccl ccpx input low time no prescaler 0.5t cy + 20 ns with prescaler pic16 c xxx 10 ns pic16 lc xxx 20 ns 51 tcch ccpx input high time no prescaler 0.5t cy + 20 ns with prescaler pic16 c xxx 10 ns pic16 lc xxx 20 ns 52 tccp ccpx input period 3t cy + 40 n ns n = prescale value (1,4 or 16) 53 tccr ccpx output fall time pic16 c xxx 10 25 ns pic16 lc xxx 25 45 ns 54 tccf ccpx output fall time pic16 c xxx 10 25 ns pic16 lc xxx 25 45 ns ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 30-1 for load conditions. (capture mode) 50 51 52 53 54 ccpx ccpx (compare or pwm mode)
picmicro mid-range mcu family ds31030a-page 30-22 1997 microchip technology inc. 30.18 example parallel slave port (psp) timing waveforms and requirements figure 30-8: example parallel slave port timing waveforms table 30-20: example parallel slave port requirements param. no. symbol characteristic min typ? max units conditions 62 tdtv2wrh data in valid before wr - or cs - (setup time) 20 ns 63 twrh2dti wr - or cs - to data?n invalid (hold time) pic16 c xxx 20 ns pic16 lc xxx 35 ns 64 trdl2dtv rd and cs to data?ut valid 80 ns 65 trdh2dti rd - or cs to data?ut invalid 10 30 ns 66 tibfinh inhibit of the ibf ?g bit being cleared from wr - or cs - 3tcy ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. note: refer to figure 30-1 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
1997 microchip technology inc. ds31030a-page 30-23 section 30. electrical specifications electrical speci?ations 30 30.19 example ssp and master ssp spi mode timing waveforms and requirements figure 30-9: example spi master mode timing (cke = 0) table 30-21: example spi mode requirements (master mode, cke = 0) param. no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time pic16 c xxx 10 25 ns pic16 lc xxx 20 45 ns 76 tdof sdo data output fall time 10 25 ns 78 tscr sck output rise time (master mode) pic16 c xxx 10 25 ns pic16 lc xxx 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic16 c xxx 50 ns pic16 lc xxx 100 ns ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: speci?ation 73a is only required if speci?ations 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 refer to figure 30-1 for load conditions.
picmicro mid-range mcu family ds31030a-page 30-24 1997 microchip technology inc. figure 30-10: example spi master mode timing (cke = 1) table 30-22: example spi mode requirements (master mode, cke = 1) param. no. symbol characteristic min typ? max units conditions 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time pic16 c xxx 10 25 ns pic16 lc xxx 20 45 ns 76 tdof sdo data output fall time 10 25 ns 78 tscr sck output rise time (master mode) pic16 c xxx 10 25 ns pic16 lc xxx 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic16 c xxx 50 ns pic16 lc xxx 100 ns 81 tdov2sch, tdov2scl sdo data output setup to sck edge t cy ns ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: speci?ation 73a is only required if speci?ations 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb refer to figure 30-1 for load conditions.
1997 microchip technology inc. ds31030a-page 30-25 section 30. electrical specifications electrical speci?ations 30 figure 30-11: example spi slave mode timing (cke = 0) table 30-23: example spi mode requirements (slave mode timing (cke = 0) param. no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time pic16 c xxx 10 25 ns pic16 lc xxx 20 45 ns 76 tdof sdo data output fall time 10 25 ns 77 tssh2doz ss - to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic16 c xxx 10 25 ns pic16 lc xxx 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic16 c xxx 50 ns pic16 lc xxx 100 ns 83 tsch2ssh, tscl2ssh ss - after sck edge 1.5t cy + 40 ns ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: speci?ation 73a is only required if speci?ations 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 refer to figure 30-1 for load conditions.
picmicro mid-range mcu family ds31030a-page 30-26 1997 microchip technology inc. figure 30-12: example spi slave mode timing (cke = 1) table 30-24: example spi slave mode mode requirements (cke = 1) param. no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time pic16 c xxx 10 25 ns pic16 lc xxx 20 45 ns 76 tdof sdo data output fall time 10 25 ns 77 tssh2doz ss - to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic16 c xxx 10 25 ns pic16 lc xxx 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic16 c xxx 50 ns pic16 lc xxx 100 ns 82 tssl2dov sdo data output valid after ss edge pic16 c xxx 50 ns pic16 lc xxx 100 ns 83 tsch2ssh, tscl2ssh ss - after sck edge 1.5t cy + 40 ns ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: speci?ation 73a is only required if speci?ations 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 refer to figure 30-1 for load conditions.
1997 microchip technology inc. ds31030a-page 30-27 section 30. electrical specifications electrical speci?ations 30 30.20 example ssp i 2 c mode timing waveforms and requirements figure 30-13: example ssp i 2 c bus start/stop bits timing waveforms table 30-25: example ssp i 2 c bus start/stop bits requirements param. no. symbol characteristic min typ max units conditions 90 t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91 t hd : sta start condition 100 khz mode 4000 ns after this period the ?st clock pulse is generated hold time 400 khz mode 600 92 t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 note: refer to figure 30-1 for load conditions. 91 93 scl sda start condition stop condition 90 92
picmicro mid-range mcu family ds31030a-page 30-28 1997 microchip technology inc. figure 30-14: example ssp i 2 c bus data timing waveforms note: refer to figure 30-1 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
1997 microchip technology inc. ds31030a-page 30-29 section 30. electrical specifications electrical speci?ations 30 table 30-26: example ssp i 2 c bus data requirements param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 m s pic16cxxx must operate at a minimum of 1.5 mhz 400 khz mode 0.6 m s pic16cxxx must operate at a minimum of 10 mhz ssp module 1.5t cy 101 t low clock low time 100 khz mode 4.7 m s pic16cxxx must operate at a minimum of 1.5 mhz 400 khz mode 1.3 m s pic16cxxx must operate at a minimum of 10 mhz ssp module 1.5t cy 102 t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91 t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the ?st clock pulse is generated 400 khz mode 0.6 m s 106 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107 t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92 t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109 t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110 t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s d102 cb bus capacitive loading 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the unde?ed region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement tsu;dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. t r max. + tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus speci?ation) before the scl line is released.
picmicro mid-range mcu family ds31030a-page 30-30 1997 microchip technology inc. 30.21 example master ssp i 2 c mode timing waveforms and requirements figure 30-15: example master ssp i 2 c bus start/stop bits timing waveforms table 30-27: example master ssp i 2 c bus start/stop bits requirements param. no. symbol characteristic min typ max units conditions 90 t su : sta start condition 100 khz mode 2(t osc )(brg + 1) ns only relevant for repeated start condition setup time 400 khz mode 2(t osc )(brg + 1) 1 mhz mode (1) 2(t osc )(brg + 1) 91 t hd : sta start condition 100 khz mode 2(t osc )(brg + 1) ns after this period the ?st clock pulse is generated hold time 400 khz mode 2(t osc )(brg + 1) 1 mhz mode (1) 2(t osc )(brg + 1) 92 t su : sto stop condition 100 khz mode 2(t osc )(brg + 1) ns setup time 400 khz mode 2(t osc )(brg + 1) 1 mhz mode (1) 2(t osc )(brg + 1) 93 t hd : sto stop condition 100 khz mode 2(t osc )(brg + 1) ns hold time 400 khz mode 2(t osc )(brg + 1) 1 mhz mode (1) 2(t osc )(brg + 1) this speci?ation ensured by design. for the value required by the i 2 c speci?ation, please refer to figure a-11 of the ?ppendix. maximum pin capacitance = 10 pf for all i 2 c pins. note: refer to figure 30-1 for load conditions. 91 93 scl sda start condition stop condition 90 92
1997 microchip technology inc. ds31030a-page 30-31 section 30. electrical specifications electrical speci?ations 30 figure 30-16: example master ssp i 2 c bus data timing table 30-28: example master ssp i 2 c bus data requirements param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) ?s 400 khz mode 2(t osc )(brg + 1) ?s 1 mhz mode (1) 2(t osc )(brg + 1) ?s 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) ?s 400 khz mode 2(t osc )(brg + 1) ?s 1 mhz mode (1) 2(t osc )(brg + 1) ?s 102 t r sda and scl rise time 100 khz mode 1000 ns cb is speci?d to be from 10 to 400 pf 400 khz mode 20 + 0.1cb 300 ns 1 mhz mode (1) 300 ns 103 t f sda and scl fall time 100 khz mode 300 ns cb is speci?d to be from 10 to 400 pf 400 khz mode 20 + 0.1cb 300 ns 1 mhz mode (1) 100 ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ms only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) ?s 1 mhz mode (1) 2(t osc )(brg + 1) ?s 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ms after this period the ?st clock pulse is generated 400 khz mode 2(t osc )(brg + 1) ?s 1 mhz mode (1) 2(t osc )(brg + 1) ?s 106 t hd : dat data input hold time 100 khz mode 0 ?s 400 khz mode 0 0.9 ms 1 mhz mode (1) tbd ?s 107 t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ?s 1 mhz mode (1) tbd ?s 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ?s 400 khz mode 2(t osc )(brg + 1) ?s 1 mhz mode (1) 2(t osc )(brg + 1) ?s 109 t aa output valid from clock 100 khz mode 3500 ns 400 khz mode 1000 ns 1 mhz mode (1) ?s 110 t buf bus free time 100 khz mode 4.7 ms time the bus must be free before a new transmis- sion can start 400 khz mode 1.3 ?s 1 mhz mode (1) tbd ?s d102 cb bus capacitive loading 400 pf this speci?ation ensured by design. for the value required by the i 2 c speci?ation, please refer to figure a-11 of the ?ppendix. these parameters are for design guidance only and are not tested, nor characterized. note 1: maximum pin capacitance = 10 pf for all i 2 c pins. 2: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but parameter 107 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. parameter 102 .+ parameter 107 = 1000 + 250 = 1250 ns (for 100 khz-mode) before the scl line is released. note: refer to figure 30-1 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
picmicro mid-range mcu family ds31030a-page 30-32 1997 microchip technology inc. 30.22 example usart/sci timing waveforms and requirements figure 30-17: example usart synchronous transmission (master/slave) timing waveforms table 30-29: example usart synchronous transmission requirements param. no. symbol characteristic min typ? max units conditions 120 tckh2dtv sync xmit (master & sla ve) clock high to data out valid pic16 c xxx 80 ns pic16 lc xxx 100 ns 121 tckrf clock out rise time and fall time (master mode) pic16 c xxx 45 ns pic16 lc xxx 50 ns 122 tdtrf data out rise time and fall time pic16 c xxx 45 ns pic16 lc xxx 50 ns ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 30-1 for load conditions. 121 121 122 tx/ck pin rx/dt pin 120
1997 microchip technology inc. ds31030a-page 30-33 section 30. electrical specifications electrical speci?ations 30 figure 30-18: example usart synchronous receive (master/slave) timing waveforms table 30-2: example usart synchronous receive requirements param. no. symbol characteristic min typ? max units conditions 125 tdtv2ckl sync rcv (master & sla ve) data hold before ck (dt hold time) 15 ns 126 tckl2dtl data hold after ck (dt hold time) 15 ns ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 30-1 for load conditions. 125 126 tx/ck pin rx/dt pin
picmicro mid-range mcu family ds31030a-page 30-34 1997 microchip technology inc. 30.23 example 8-bit a/d timing waveforms and requirements table 30-30: example 8-bit a/d converter characteristics param no. symbol characteristic min typ? max units conditions a01 n r resolution 8-bits bit v ref = v dd = 5.12v, v ss v ain v ref a02 e abs total absolute error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a05 e fs full scale error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 monotonicity guaran- teed v ss v ain v ref a20 v ref reference voltage 3.0v v dd + 0.3 v a25 v ain analog input voltage v ss - 0.3 v ref + 0.3 v a30 z ain recommended impedance of analog voltage source 10.0 k w a40 i ad a/d conversion current (v dd ) pic16 c xxx 180 m a average current con- sumption when a/d is on (note 1) pic16 lc xxx 90 m a a50 i ref v ref input current (note 2) 10 1000 10 m a m a during v ain acquisition. based on differential of v hold to v ain to charge c hold see the ?-bit a/d con- verter section during a/d conversion cycle ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. v ref current is from ra3 pin or v dd pin, whichever is selected as reference input.
1997 microchip technology inc. ds31030a-page 30-35 section 30. electrical specifications electrical speci?ations 30 figure 30-19: example 8-bit a/d conversion timing waveforms table 30-31: example 8-bit a/d conversion requirements param no. symbol characteristic min typ? max units conditions 130 t ad a/d clock period pic16 c xxx 1.6 m st osc based, v ref 3 3.0v pic16 lc xxx 2.0 m st osc based, v ref full range pic16 c xxx 2.0 4.0 6.0 m s a/d rc mode pic16 lc xxx 3.0 6.0 9.0 m s a/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) 11 11 t ad 132 t acq acquisition time note 2 5 20 m s m s the minimum time is the ampli?r settling time. this may be used if the ?ew input voltage has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start 2t osc if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 136 t amp ampli?r settling time (note 2) 1 m s this may be used if the ?ew input voltage has not changed by more than 1lsb (i.e. 5 mv @ 5.12v) from the last sampled volt- age (as stated on c hold ). 135 t swc switching time from convert ? sample 1 1 t ad ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. note 1: adres register may be read on the following t cy cycle. see the ?-bit a/d converter section for minimum requirements. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy
picmicro mid-range mcu family ds31030a-page 30-36 1997 microchip technology inc. 30.24 example 10-bit a/d timing waveforms and requirements table 30-32: example 10-bit a/d converter characteristics param no. symbol characteristic min typ? max units conditions a01 n r resolution 10 bit v ref = v dd = 5.12v, v ss v ain v ref a02 e abs absolute error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a05 e fs full scale error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 monotonicity guaran- teed v ss v ain v ref a20 v ref reference voltage (v refh - v refl ) 0v v for no latch-up a20a 3v v for 10-bit resolution a21 v refh reference voltage high av ss ?v dd + 0.3v v a22 v refl reference voltage low av ss - 0.3v av dd v a25 v ain analog input voltage av ss - 0.3v v ref + 0.3v v a30 z ain recommended impedance of analog voltage source 10.0 k w a40 i ad a/d conversion current (v dd ) pic16 c xxx 180 m a average current con- sumption when a/d is on. (note 1) pic16 lc xxx ?0 m a a50 i ref v ref input current (note 2) 10 1000 10 m a m a during v ain acquisition. based on differential of v hold to v ain . to charge c hold see the ?0-bit a/d converter section. during a/d conversion cycle ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. v ref current is from rg0 and rg1 pins or av dd and av ss pins, whichever is selected as reference input.
1997 microchip technology inc. ds31030a-page 30-37 section 30. electrical specifications electrical speci?ations 30 figure 30-20: example 10-bit a/d conversion timing waveforms table 30-33: example 10-bit a/d conversion requirements param no. symbol characteristic min typ? max units conditions 130 t ad a/d clock period pic16 c xxx 1.6 m s t osc based, v ref 3 3.0v pic16 lc xxx 3.0 m st osc based, v ref full range pic16 c xxx 2.0 4.0 6.0 m s a/d rc mode pic16 lc xxx 3.0 6.0 9.0 m s a/d rc mode 131 t cnv conversion time (not including acquisition time) (note 1) 11 12 t ad 132 t acq acquisition time (note 3) 15 10 m s m s -40 c temp 125 c 0 c temp 125 c 136 t amp ampli?r settling time (note 2) 1 m s this may be used if the ?ew input voltage has not changed by more than 1lsb (i.e. 5 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 135 t swc switching time from convert ? sample note 4 ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. note 1: adres register may be read on the following t cy cycle. 2: see the ?0-bit a/d converter section for minimum conditions when input voltage has changed more than 1 lsb. 3: the time for the holding capacitor to acquire the ?ew input voltage when the voltage changes full scale after the conversion (av dd to av ss , or av ss to av dd ). the source impedance ( r s ) on the input channels is 50 w . 4: on the next q4 cycle of the device clock 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data note 2 987 21 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . t cy
picmicro mid-range mcu family ds31030a-page 30-38 1997 microchip technology inc. 30.25 example slope a/d timing waveforms and requirements figure 30-21: example slope a/d conversion cycle xx capture clk adrst adcon0<1> capture register cdac xx+8 compare adcif (must be cleared by software) adtmr increments xx+1 xx+2 xx+3 adtmr count xx+8 xx+9 xx
1997 microchip technology inc. ds31030a-page 30-39 section 30. electrical specifications electrical speci?ations 30 table 30-34: example slope a/d component characteristics dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial, -40?c t a +85?c for industrial and -40?c t a +125?c for extended operating voltage v dd range as described in dc spec table 30-3 . param no. symbol characteristic min typ max units conditions slope a/d comparator a100 v ain analog input voltage range v ss ? dd - 1.4 v a101 input offset voltage - 10 2 10 mv measured over common-mode range a102 g dv differential voltage gain (note 1) 100 db a103 cmrr common mode rejection ratio (note 1) 80 db v dd = 5v, t a = 25 c, over common-mode range a104 rradc power supply rejection ratio (note 1) 70 db t a = 25 c, v dd min v dd v dd max t set turn-on settling time 140 band gap reference (to < 0.1% (note 1) 1 10 ms refoff bit in slpcon register 1 ? 0 141 programmable current source (to < 0.1%) 1 10 ms bias generator (reference) turn-on time (refoff 1 ? 0) (reference start-up) (note 1) 141a 1 10 m s refoff = 0 (constant), adcon1<7:4> 0000b ? 1111b (reference already on and stable) (note 3) tc temperature coef?ient (note 1) a110 tc bgr band gap reference + 50 - 50 ppm/ c - 40 c t a +25 c 25 c t a +85 c a110a + 20 - 20 ppm/ c0 c t a +25 c 25 c t a +70 c a111 tc pcs programmable current source + 0.1 - 0.1 %/ c - 40 c t a +25 c 25 c t a +85 c a112 tckref slope reference divider 20 ppm/ c - 40 c t a +85 c ca calibration accuracy (note3, 5) all parameters calibrated at v dd = 5v and t a = +25 c a120 ca bgr band gap reference 0.01 % a121 ca srv slope reference divider 0.02 % sn supply sensitivity (note 1) a130 sn bgr band gap reference 0.04 ? % / v from v dd min to v dd max a131 sn pcs programmable current source 0.2 % / v from v dd min to v dd max a132 snkref slope reference divider % / v from v dd min to v dd max programmable current source a140 i res resolution 1.25 2.25 3.25 m a 1 lsb a141 e il relative accuracy (linearity error) - 1/2 +1/2 lsb cdac = 0v
picmicro mid-range mcu family ds31030a-page 30-40 1997 microchip technology inc. 30.26 example lcd timing waveforms and requirements figure 30-22: example lcd voltage waveform table 30-35: example lcd module timing requirements param no. symbol characteristic min typ? max units conditions 200 f lcdrc l cdrc oscillator frequency 14 22 khz v dd = 5v, -40?c to +85?c 201 tr lcd output rise time 200 m s com outputs cload = 5,000 pf seg outputs cload = 500 pf v dd = 5.0v, t = 25 c 202 tf lcd output fall time (note 1) tr lcd - 0.05tr lcd ?r lcd + 0.05tr lcd m s com outputs cload = 5,000 pf seg outputs cload = 500 pf v dd = 5.0v, t = 25 c ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: 0 w source impedance at v lcd . v lcd 3 v lcd 2 v lcd 1 v ss 201 202
1997 microchip technology inc. ds31030a-page 30-41 section 30. electrical specifications electrical speci?ations 30 30.27 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or high-end families), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to the electrical speci?ations are: title application note # no related application notes
picmicro mid-range mcu family ds31030a-page 30-42 1997 microchip technology inc. 30.28 revision history revision a this is the initial released revision of the electrical speci?ations description.
1997 microchip technology inc. ds31031a page 31-1 device characteristics 31 m section 31. device characteristics highlights 31.1 introduction ............................................................................................................... ...31-2 31.2 characterization vs. electrical speci?ation ................................................................31-2 31.3 dc and ac characteristics graphs and tables ...........................................................31-2 31.4 revision history .........................................................................................................31 -22
picmicro mid-range mcu family ds31031a-page 31-2 1997 microchip technology inc. 31.1 introduction microchip technology inc. provides characterization information on the devices that it manufac- tures. this information becomes available after the devices have undergone a complete charac- terization and the data has been analyzed. this data is taken on both device testers and on bench setups. the characterization data gives the designer a better understanding of the device characteristics, to better judge the acceptability of the device to the application. 31.2 characterization vs. electrical speci?ation the difference between this information and the electrical speci?ations can be classi?d as what the user should expect the devices to do vs. what microchip tests the devices to. the char- acterization graphs and tables provided are for design guidance and are not tested or guaran- teed. there may be differences between what the characterization shows as the limits vs. that which is tested, as shown in the electrical speci?ation section. this results from capabilities of the pro- duction tester equipment, plus whatever guard band that may be necessary. 31.3 dc and ac characteristics graphs and tables each table gives speci? information that may be useful design information. these values are taken under ?ed circumstances. measurements taken in your application may not lead to the same values if your circumstances are not the same. in some graphs or tables the data presented are outside speci?d operating range (i.e., outside speci?d v dd range). this is for information only and devices will operate properly only within the speci?d range. note: the data presented in the device data sheet characterization section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'typical' represents the mean of the distribution at, 25 c, while 'max' or 'min' represents (mean +3 s ) and (mean -3 s ) respectively where s is stan- dard deviation.
1997 microchip technology inc. ds31031a-page 31-3 section 31. device characteristics device characteristics 31 31.3.1 i pd vs. v dd i pd is the current ( i ) that the device consumes when the device is in sleep mode (power-down), referred to as power-down current. these tests are taken with all i/o as inputs, either pulled high or low. that is, there are no ?ating inputs, nor are any pins driving an output (with a load). the characterization shows graphs for both the watchdog timer (wdt) disabled and enabled. this is required since the wdt requires an on-chip rc oscillator which consumes additional cur- rent. since the device may have certain features and modules that can operate while the device is in sleep mode. some of these modules are: watchdog timer (wdt) brown-out reset (bor) circuitry timer1 analog to digital converter lcd module comparators voltage reference if these features are operating while the device is in sleep mode, a higher current will be con- sumed. when all features are disabled, the device will consume the lowest possible current (the leakage current). if more then one feature is enabled then the expected current can easily be cal- culated as the base current (everything disabled and in sleep mode) plus all delta currents. example 31-1 shows an example of calculating the typical currents for a device at 5v, with the wdt and timer1 oscillator enabled. example 31-1:i pd calculations with wdt and timer1 oscillator enabled (@ 5v) base current 14 na ; device leakage current wdt delta current 14 m a ; 14 m a - 14 na = 14 m a timer1 delta current 22 m a ; 22 m a - 14 na = 22 m a total sleep current 36 m a ;
picmicro mid-range mcu family ds31031a-page 31-4 1997 microchip technology inc. figure 31-1: example typical i pd vs. v dd (wdt disabled, rc mode) figure 31-2: example maximum i pd vs. v dd (wdt disabled, rc mode) 35 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd (na) v dd (volts) i pd ( m a) v dd (volts) 10.000 1.000 0.100 0.010 0.001 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 85 c 70 c 25 c 0 c -40 c
1997 microchip technology inc. ds31031a-page 31-5 section 31. device characteristics device characteristics 31 figure 31-3: example typical i pd vs. v dd @ 25 c (wdt enabled, rc mode) figure 31-4: example maximum i pd vs. v dd (wdt enabled, rc mode) 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) 35 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) -40 c 0 c 70 c 85 c
picmicro mid-range mcu family ds31031a-page 31-6 1997 microchip technology inc. figure 31-5: example typical i pd vs. v dd brown-out detect enabled (rc mode) figure 31-6: example maximum i pd vs. v dd brown-out detect enabled (85 c to -40 c, rc mode) the shaded region represents the built-in hysteresis of the brown-out reset circuitry. 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1400 1200 1000 800 600 400 200 0 v dd (volts) i pd ( m a) device in brown-out device not in brown-out reset reset the shaded region represents the built-in hysteresis of the brown-out reset circuitry. 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1400 1200 1000 800 600 400 200 0 v dd (volts) i pd ( m a) 4.3 1600 device not in brown-out reset device in brown-out reset
1997 microchip technology inc. ds31031a-page 31-7 section 31. device characteristics device characteristics 31 figure 31-7: example typical i pd vs. timer1 enabled (32 khz, rc0/rc1 = 33 pf/33 pf, rc mode) figure 31-8: example maximum i pd vs. timer1 enabled (32 khz, rc0/rc1 = 33 pf/33 pf, 85 c to -40 c, rc mode) 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) i pd ( m a) 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) i pd ( m a) 35 40 45
picmicro mid-range mcu family ds31031a-page 31-8 1997 microchip technology inc. 31.3.2 i dd vs. frequency i dd is the current ( i ) that the device consumes when the device is in operating mode. this test is taken with all i/o as inputs, either pulled high or low. that is, there are no ?ating inputs, nor are any pins driving an output (with a load). the i dd vs. frequency charts measure the results on a microchip automated bench setup, called the dcs ( d ata c ollection s ystem). the dcs accurately re?cts the device and speci?d com- ponent values, that is, it does not add stray capacitance or current. 31.3.2.1 rc measurements for the rc measurement, the dcs selects a resistor and capacitor value, and then varies the voltage over the speci?d range. as the voltage is changed, the frequency of operation changes. for a ?ed rc, as v dd increases, the frequency increases. after the measurement, at this rc, has been taken, the rc value is changed and the measurements are taken again. each point on the graph corresponds to a device voltage, resistor value (r), and capacitor value (c). figure 31-9: example typical i dd vs. frequency (rc mode @ 22 pf, 25 c) 2000 1800 1600 1400 1200 800 1000 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 frequency (mhz) i dd ( m a) shaded area is 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v beyond recommended range ? r = 5 k w ? r = 10 k w ?
1997 microchip technology inc. ds31031a-page 31-9 section 31. device characteristics device characteristics 31 figure 31-10: example maximum i dd vs. frequency (rc mode @ 22 pf, -40 c to 85 c) figure 31-11: example typical i dd vs. frequency (rc mode @ 100 pf, 25 c) 2000 1800 1600 1400 1200 800 1000 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 frequency (mhz) i dd ( m a) shaded area is 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v beyond recommended range 1600 1400 1200 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 frequency (khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v shaded area is beyond recommended range
picmicro mid-range mcu family ds31031a-page 31-10 1997 microchip technology inc. figure 31-12: example maximum i dd vs. frequency (rc mode @ 100 pf, -40 c to 85 c) figure 31-13: example typical i dd vs. frequency (rc mode @ 300 pf, 25 c) 1600 1400 1200 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 frequency (khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v shaded area is beyond recommended range 1200 1000 800 600 400 200 0 0 100 200 300 400 500 600 700 frequency (khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v
1997 microchip technology inc. ds31031a-page 31-11 section 31. device characteristics device characteristics 31 figure 31-14: example maximum i dd vs. frequency (rc mode @ 300 pf, -40 c to 85 c) figure 31-15: example typical i dd vs. capacitance @ 500 khz (rc mode) 1200 1000 800 600 400 200 0 0 100 200 300 400 500 600 700 frequency (khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v capacitance (pf) 600 i dd ( m a) 500 400 300 200 100 0 20 pf 100 pf 300 pf 5.0v 4.0v 3.0v
picmicro mid-range mcu family ds31031a-page 31-12 1997 microchip technology inc. 31.3.2.2 crystal oscillator measurements on the data collection system, there are several crystals. for this test a crystal is multiplexed into the device circuit, and the crystals capacitance values can be varied. the capacitance and voltage values are varied to determine the best characteristics (current, oscillator waveform, and oscillator start-up), and then the currents are measured over voltage. the next crystal oscillator is then switched in and the procedure is repeated. figure 31-16: example typical i dd vs. frequency (lp mode, 25 c) figure 31-17: example maximum i dd vs. frequency (lp mode, 85 c to -40 c) 120 100 80 60 40 20 0 0 50 100 150 200 frequency (khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 120 100 80 60 40 20 0 0 50 100 150 200 frequency (khz) i dd ( m a) 140 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v
1997 microchip technology inc. ds31031a-page 31-13 section 31. device characteristics device characteristics 31 figure 31-18: example typical i dd vs. frequency (xt mode, 25 c) figure 31-19: example maximum i dd vs. frequency (xt mode, -40 c to 85 c) 1200 1000 800 600 400 200 0 0.0 0.4 frequency (mhz) i dd ( m a) 1400 1600 1800 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 1200 1000 800 600 400 200 0 0.0 0.4 frequency (mhz) i dd ( m a) 1400 1600 1800 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v
picmicro mid-range mcu family ds31031a-page 31-14 1997 microchip technology inc. figure 31-20: example typical i dd vs. frequency (hs mode, 25 c) figure 31-21: example maximum i dd vs. frequency (hs mode, -40 c to 85 c) 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 12 4 6 8 10 12 14 16 18 20 frequency (mhz) i dd (ma) 6.0v 5.5v 5.0v 4.5v 4.0v 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 12 4 6 8 10 12 14 16 18 20 frequency (mhz) i dd (ma) 6.0v 5.5v 5.0v 4.5v 4.0v
1997 microchip technology inc. ds31031a-page 31-15 section 31. device characteristics device characteristics 31 31.3.3 rc oscillator frequency these tables show the effects of the rc oscillator frequency as the device voltage varies. in these measurements a capacitor and resistor value are selected and then the frequency of the rc is measured as the device voltage varies. the table shows the typical frequency for a r and c value at 5v, as well as the variation from this frequency that can be expected due to device processing. figure 31-22: example typical rc oscillator frequency vs. v dd figure 31-23: example typical rc oscillator frequency vs. v dd 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 fosc (mhz) c ext = 22 pf, t = 25 c r = 100k r = 10k r = 5k shaded area is beyond recommended range. 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 fosc (mhz) c ext = 100 pf, t = 25 c r = 100k r = 10k r = 5k r = 3.3k
picmicro mid-range mcu family ds31031a-page 31-16 1997 microchip technology inc. figure 31-24: example typical rc oscillator frequency vs. v dd table 31-1: example rc oscillator frequencies c ext r ext average fosc @ 5v, 25 c 22 pf 5k 4.12 mhz 1.4% 10k 2.35 mhz 1.4% 100k 268 khz 1.1% 100 pf 3.3k 1.80 mhz 1.0% 5k 1.27 mhz 1.0% 10k 688 khz 1.2% 100k 77.2 khz 1.0% 300 pf 3.3k 707 khz 1.4% 5k 501 khz 1.2% 10k 269 khz 1.6% 100k 28.3 khz 1.1% the percentage variation indicated here is part to part variation due to normal process distri- bution. the variation indicated is 3 standard deviation from average value for v dd = 5v. 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) 1000 900 800 700 600 500 400 300 200 100 0 fosc (khz) c ext = 300 pf, t = 25 c r = 3.3k r = 5k r = 10k r = 100k
1997 microchip technology inc. ds31031a-page 31-17 section 31. device characteristics device characteristics 31 31.3.4 oscillator transconductance transconductance of the oscillator indicates the gain of the oscillator. as the transconductance increases, the gain of the oscillator circuit increases which causes the current consumption of the oscillator circuit to increase. also as the transconductance increases the maximum frequency that the oscillator circuit can support also increases, or the start-up time of the oscillator decreases. figure 31-25: example transconductance (gm) of hs oscillator vs. v dd figure 31-26: example transconductance (gm) of lp oscillator vs. v dd 4.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm (ma/v) v dd (volts) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 max -40 c typ 25 c min 85 c shaded area is beyond recommended range 110 100 90 80 70 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm (ma/v) v dd (volts) max -40 c typ 25 c min 85 c shaded areas are beyond recommended range
picmicro mid-range mcu family ds31031a-page 31-18 1997 microchip technology inc. figure 31-27: example transconductance (gm) of xt oscillator vs. v dd 1000 900 800 700 600 500 400 300 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm (ma/v) v dd (volts) max -40 c typ 25 c min 85 c shaded areas are beyond recommended range
1997 microchip technology inc. ds31031a-page 31-19 section 31. device characteristics device characteristics 31 31.3.5 crystal start-up time these graphs show the start-up time that one should expect to see at the speci?d voltage level, for a given crystal/capacitor combination. figure 31-28: example typical xtal start-up time vs. v dd (lp mode, 25 c) figure 31-29: example typical xtal start-up time vs. v dd (hs mode, 25 c) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) start-up time (seconds) 32 khz, 33 pf/33 pf 200 khz, 15 pf/15 pf 7 6 5 4 3 2 1 4.0 4.5 5.0 5.5 6.0 v dd (volts) start-up time (ms) 20 mhz, 33 pf/33 pf 8 mhz, 33 pf/33 pf 8 mhz, 15 pf/15 pf 20 mhz, 15 pf/15 pf
picmicro mid-range mcu family ds31031a-page 31-20 1997 microchip technology inc. figure 31-30: example typical xtal start-up time vs. v dd (xt mode, 25 c) 70 60 50 40 30 20 10 0 3.0 3.5 2.5 4.0 5.0 5.5 6.0 4.5 v dd (volts) start-up time (ms) 200 khz, 68 pf/68 pf 200 khz, 47 pf/47 pf 1 mhz, 15 pf/15 pf 4 mhz, 15 pf/15 pf
1997 microchip technology inc. ds31031a-page 31-21 section 31. device characteristics device characteristics 31 31.3.6 tested crystals and their capacitor values this table shows the crystal frequency and manufacturer that was used for every tests in this sec- tion, as well as the capacitor values/ranges that exhibited the best characteristics. table 31-2: example capacitor selection for crystal oscillators 31.3.7 example eprom memory erase times the uv erase time of an eprom cell depends on the geometry size of the eprom cell and the manufacturing technology. table 31-3 shows some of the expected erase times for each different device. table 31-3: example of typical eprom erase time recommendations table 31-4: refer to the device data sheet for the typical erase times for a device. osc type crystal frequency capacitor range c1 capacitor range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf note: higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level speci?ation. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components or verify oscillator performance. crystals used: 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm example device wavelength (angstroms) intensity ( m w/cm 2 ) distance from uv lamp (inches) typical time (1) (minutes) 1 2537 12,000 1 15 - 20 2 2537 12,000 1 20 3 2537 12,000 1 40 4 2537 12,000 1 60 note 1: if these criteria are not met, the erase times will be different.
picmicro mid-range mcu family ds31031a-page 31-22 1997 microchip technology inc. 31.4 revision history revision a this is the initial released revision of the device characteristics description.
1997 microchip technology inc. ds31032a page 32-1 m development tools 32 section 32. development tools highlights this section of the manual contains the following major topics: 32.1 introduction ............................................................................................................... ...32-2 32.2 the integrated development environment (ide) .........................................................32-3 32.3 mplab software language support ...........................................................................32-6 32.4 mplab-sim simulator software ..................................................................................32-8 32.5 mplab emulator hardware support ...........................................................................32-9 32.6 mplab programmer support ....................................................................................32-10 32.7 supplemental tools....................................................................................................32-11 32.8 development boards..................................................................................................32-12 32.9 development tools for other microchip products ......................................................32-14 32.10 related application notes..........................................................................................32-15 32.11 revision history .........................................................................................................3 2-16
picmicro mid-range mcu family ds31032a-page 32-2 1997 microchip technology inc. 32.1 introduction microchip offers a wide range of tightly integrated development tools to ease the application development process. these can be broken down into the core development tools and the sup- plemental tools. the core tools are as follows: mplab integrated development environment, including full featured editor language products - mpasm assembler - mplab-c c compiler mplab-sim software simulator real-time in-circuit emulators - picmaster/picmaster ce emulator with full featured trace and breakpoint debug capabilities - icepic low-cost emulator with breakpoint debug capabilities device programmers - pro mate a ii universal programmer - picstart a plus entry-level prototype programmer supplemental tools: other software programming tools - fuzzytech a - mp fuzzy logic development system - mp-driveway application code generator development boards - picdem-1 low-cost demonstration board - picdem-2 low-cost demonstration board - picdem-3 low-cost demonstration board - picdem-14a low-cost demonstration board the minimum con?uration of mplab, is the integrated development environment (ide), the assembler (mpasm), and the software simulator (mplab-sim). other tools are added to mplab as they are installed. this gives a common platform for the design activity, from the writing and assembling of the source code, through the simulation/emulation, to the programming of proto- type devices. in addition to microchip, there are many third party vendors. microchips third party handbook gives an overview of the manufactures and their tools. note: the most current version may be downloaded from microchips web site or bbs for free.
1997 microchip technology inc. ds31032a-page 32-3 section 32. development tools development tools 32 32.2 the integrated development environment (ide) the core set of development tools operate under the ide umbrella, called mplab. this gives a consistent look and feel to all the development tools so that minimal learning of the new tool inter- face is required. the mplab ide integrates all the following aspects of development: source code editing project management machine code generation (from assembly or ?? device simulation device emulation device programming mplab is a pc based windows 3.x application. it has been extensively tested using windows 95 and recommended in either of these operating environments. this comprehensive tool suite allows the complete development of a project without leaving the mplab environment. windows is a registered trademark of microsoft corporation.
picmicro mid-range mcu family ds31032a-page 32-4 1997 microchip technology inc. 32.2.1 mplab the mplab ide software brings an ease of software development previously unseen in the 8-bit microcontroller market. mplab is a windows based application that contains: a full featured editor three operating modes - editor - emulator - simulator a project manager customizable tool bar and key mapping a status bar with project information extensive on-line help mplab allows you to: edit your source ?es. this includes: - mpasm assembly language - mplab-c ? language one touch assemble (or compile) and download to pic16/17 tools (automatically updates all project information) debug using: - source ?es - absolute listing ?e - program memory run up to four emulators on the same pc run or single-step - program memory - source ?e - absolute listing microchips simulator, mplab-sim, operates under the same platform as the picmaster emu- lator. this allows the user to learn a single tool set which functions equivalently for both the sim- ulator and the full featured emulator.
1997 microchip technology inc. ds31032a-page 32-5 section 32. development tools development tools 32 figure 32-1 shows a typical mplab desktop in the middle of a project. some of the highlights are: tool bars, multiple choices and user con?urable status, mode information, and button help on footer bar multiple windows, such as - source code - source listing (most useful for ? programs) - register ?e window (ram) - watch windows (to look at speci? register) - stop watch window for time/cycle calculations programmer support (in this case pro mate pull down menu) figure 32-1: mplab project window
picmicro mid-range mcu family ds31032a-page 32-6 1997 microchip technology inc. 32.3 mplab software language support to make the device operate as desired in the application, a software program needs to be written for the microcontroller. this software program needs to be written in one of the programming lan- guages for the device. currently mplab supports two of microchips language products: microchip assembler (mpasm) microchip ? compiler (mplab-c) other language products that support common object description (cod) may also work with mplab 32.3.1 assembler (mpasm) the mpasm universal macro assembler is a pc-hosted symbolic assembler. it supports all microchip microcontroller families. mpasm offers full featured macro capabilities, conditional assembly, and several source and list- ing formats. it generates various object code formats to support microchip's development tools as well as third party programmers. mpasm allow full symbolic debugging from the microchip universal emulator system (picmaster). mpasm has the following features to assist in developing software for speci? use applications. provides translation of assembler source code to object code for all microchip microcon- trollers. macro assembly capability. produces all the ?es (object, listing, symbol, and special) required for symbolic debug with microchips emulator systems. supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the picmicro. directives are helpful in making the development of your assemble source code shorter and more maintain- able. 32.3.2 c compiler (mplab-c) the mplab-c is a complete ? compiler for microchips picmicro family of microcontrollers. the compiler provides powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler provides symbol information that is compatible with the mplab ide memory display, watch windows, and file register windows.
1997 microchip technology inc. ds31032a-page 32-7 section 32. development tools development tools 32 32.3.3 mplink linker mplink is a linker for the microchip c compiler, mplab-c, and the microchip relocatable assem- bler, mpasm. mplink is introduced with mplab-c v2.00 and can only be used with these or later versions. mplink allows you to produce modular, re-usable code with mplab-c and mpasm. control over the linking process is accomplished through a linker ?cript ?e and with command line options. mplink ensures that all symbolic references are resolved and that code and data ? into the available picmicro device. mplink combines multiple input object modules generated by mplab-c or mpasm, into a sin- gle executable ?e. the actual addresses of data and the location of functions will be assigned when mplink is executed. this means that you will instruct mplink to place code and data somewhere within the named regions of memory, not to speci? physical locations. once the linker knows about the rom and ram memory regions available in the target picmicro device and it analyzes all the input ?es, it will try to ? the applications routines into rom and assign its data variables into available ram. if there is too much code or too many variables to ?, mplink will give an error message. mplink also provides ?xibility for specifying that certain blocks of data memory are re-usable, so that different routines (which never call each other and don? depend on this data to be retained between execution) can share limited ram space. 32.3.4 mplib librarian mplib is a librarian for use with coff object modules created using either mpasm v2.0, mpasmwin v2.0, or mplab-c v2.0 or later. mplib manages the creation and modi?ation of library ?es. a library ?e is a collection of object modules that are stored in a single ?e. there are several reasons for creating library ?es: libraries make linking easier. since library ?es can contain many object ?es, the name of a library ?e can be used instead of the names of many separate object when linking. libraries help keep code small. since a linker only uses the required object ?es contained in a library, not all object ?es which are contained in the library necessarily wind up in the linkers output module. libraries make projects more maintainable. if a library is included in a project, the addition or removal of calls to that library will not require a change to the link process. libraries help convey the purpose of a group of object modules. since libraries can group together several related object modules, the purpose of a library ?e is usually more under- standable that the purpose of its individual object modules. for example, the purpose of a ?e named ?ath.lib is more apparent that the purpose of 'power.o', 'ceiling.o', and '?or.o'.
picmicro mid-range mcu family ds31032a-page 32-8 1997 microchip technology inc. 32.4 mplab-sim simulator software the software simulator is a no-cost tool with which to evaluate microchips products and designs. the use of the simulator greatly helps debug software, particularly algorithms. depending on the complexity of a design project a time/cost bene? should be looked at comparing the simulator with an emulator. for projects that have multiple engineers in the development, the simulator in conjunction with an emulator can keep costs down and will allow speedy debug of the tough problems. mplab-sim simulator simulates the picmicro series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. mplab-sim supports symbolic debugging using mplab-c, and mpasm. the software simula- tor offers the low cost ?xibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
1997 microchip technology inc. ds31032a-page 32-9 section 32. development tools development tools 32 32.5 mplab emulator hardware support microchip offers two emulators, a high-end version (picmaster) and a low-cost version (icepic). both versions offer a very good price/feature value, and the selection of which emula- tor should depend on the feature set that you wish. for people looking at doing several projects with microchip devices (or using the high-end devices) the use of picmaster may offset the additional investment, through time savings achieved with the sophisticated breakpoint and trace capabilities. 32.5.1 picmaster: high performance universal in-circuit emulator the picmaster universal in-circuit emulator provides the product development engineer with a complete microcontroller design tool set for all microcontrollers in the baseline, mid-range, and high end families. picmaster operates in the mplab ? integrated development environ- ment (ide), which allows editing, ?ake and download, and source debugging from a single environment. interchangeable target probes allow the system to be easily re-con?ured for emulation of differ- ent processors. the universal architecture of the picmaster allows expansion to support all new microchip microcontrollers. the picmaster emulator system has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. a ce compliant version of picmaster is available for european union (eu) countries. 32.5.2 icepic: low-cost pic16cxxx in-circuit emulator icepic is a low-cost in-circuit emulator solution for the microchip base-line and mid-range fam- ilies of 8-bit otp microcontrollers. icepic user interface operates on pc-compatible machines ranging from 286-at a through pen- tium ? based machines under windows 3.x environment. icepic features real-time emulation. icepic is available under the mplab environment. icepic is designed by neosoft inc. and is manufactured under license by rf solutions. other emulator solutions may be available directly from rf solutions.
picmicro mid-range mcu family ds31032a-page 32-10 1997 microchip technology inc. 32.6 mplab programmer support microchip offers two levels of device programmer support. for most bench setups the picstart plus is suf?ient. when true system quali?ation is done, the pro mate ii should be the mini- mum used, due to the validation of program memory at v dd min and v dd max for maximum reli- ability 32.6.1 pro mate ii: universal device programmer the pro mate ii universal programmer is a full-featured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii operates under mplab or as a dos command driven program. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for error mes- sages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode the pro mate ii can read, verify or program baseline, mid-range, and high end devices. it can also set con?uration and code-protect bits in this mode. the pro mate ii programmer also supports microchips serial eeprom and k ee l oq security devices. a separate in-circuit serial programming (icsp) module is available for volume programming in a manufacturing environment. see the programming module documentation for speci? applica- tion requirements. 32.6.2 picstart plus low-cost development kit the picstart plus programmer is an easy-to-use, low-cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment soft- ware makes using the programmer simple and ef?ient. picstart plus is not recommended for production programming, since it does not do program memory veri?ation at v ddmin and v ddmax . picstart plus supports all baseline, mid-range, and high end devices. for devices with up more than 40 pins an adapter socket is required. dip packages are the form factor that are directly supported. other package types may be supported with adapter sockets.
1997 microchip technology inc. ds31032a-page 32-11 section 32. development tools development tools 32 32.7 supplemental tools microchip endeavors to provide a broad range of solutions to our customers. some of these prod- ucts may fall outside the realm of the classic development tools and include more advanced top- ics such as high level languages, fuzzy logic, or visual programming aids. these tools are considered supplemental tools and may be available directly from microchip or from another ven- dor. a comprehensive listing of alternate tool providers is contained in the third party guide. 32.7.1 fuzzy tech-mp fuzzy logic development system the fuzzy tech-mp fuzzy logic development tool is available in two versions - a low cost intro- ductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design, and a full-featured version, fuzzy tech-mp, for implementing more complex systems. both versions include microchips fuzzy lab ? demonstration board for hands-on experience with fuzzy logic systems implementation. 32.7.2 mp-driveway ? ?application code generator mp-driveway is an easy-to-use windows-based application code generator. with mp-drive- way you can visually con?ure all the peripherals in a pic16/17 device and, with a click of the mouse, generate all the initialization and many functional code modules in c language. the out- put is fully compatible with microchips mplab-c c compiler. the code produced is highly mod- ular and allows easy integration of your own code. 32.7.3 third party guide looking for something else? microchip strongly encourages and supports its third parties. microchip publishes the ?hird party guide? it is an extensive volume that provides: company product contact information consultants for over 100 companies and 200 products. these products include emulators, device program- mers, gang programmers, language products, and other tool solutions.
picmicro mid-range mcu family ds31032a-page 32-12 1997 microchip technology inc. 32.8 development boards development boards give a quick start on a circuit that demonstrates the capabilities of a partic- ular device. the device program can then be modi?d for your own evaluation of the device func- tionality and operation. 32.8.1 picdem-1 low-cost pic16/17 demonstration board the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrollers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c710, pic16c711, pic16c8x, pic17c42a, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample micro controllers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test ?mware. the user can also connect the picdem-1 board to the picmaster emulator and down load the ?mware to the emulator for testing. additional prototype area is available to build additional hard- ware. some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 32.8.2 picdem-2 low-cost pic16cxxx demonstration board the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c63, pic16c64, pic16c65, pic16c72, pic16c73 and pic16c74 microcon trollers. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii programmer or picstart-plus, and easily test ?mware. the picmaster emulator may also be used with the picdem-2 board to test ?mware. additional prototype area has been provided for additional hardware. some of the features include a rs-232 interface, push-button switches, a potentiometer for simulated analog input, a serial eeprom to demon- strate usage of the i 2 c bus and separate headers for connection to an lcd module and a key- pad.
1997 microchip technology inc. ds31032a-page 32-13 section 32. development tools development tools 32 32.8.3 picdem-3 low-cost pic16cxxx demonstration board the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers that have an lcd module. all the necessary hardware and software is included to run the basic dem- onstration programs. the user can program the sample microcontrollers, provided with the picdem-3 board, on a pro mate ii programmer or picstart plus with an adapter socket, and easily test ?mware. the picmaster emulator may also be used with the picdem-3 board to test ?mware. additional prototype area has been provided for adding hard- ware. some of the features include an rs-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. the pic- dem-3 provides an additional rs-232 interface and windows 3.1 software for showing the de-multiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hard- ware de-multiplexer for the lcd signals. 32.8.4 picdem-14a low-cost pic14c000 demonstration board the picdem-14a demo board is a general purpose platform which is provided to help evaluate the pic14c000 mixed signal microcontroller. the board runs a pic14c000 measuring the volt- age of a potentiometer and the on-chip temperature sensor. the voltages are then calibrated to the internal bandgap voltage reference. the voltage and temperature data are then transmitted to the rs-232 port. this data can be displayed using a terminal emulation program, such as win- dows terminal. this demo board also includes peripherals that allow users to display data on an lcd panel, read from and write to a serial eeprom, and prototype custom circuitry to interface to the microcontroller.
picmicro mid-range mcu family ds31032a-page 32-14 1997 microchip technology inc. 32.9 development tools for other microchip products 32.9.1 seeval a evaluation and programming system the seeval serial eeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special fea- tures of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade-off analysis and reliability calculations. the total endurance kit can signi?antly reduce time-to-market and results in a more optimized system. 32.9.2 k ee l oq a evaluation and programming tools k ee l oq evaluation and programming tools supports microchips hcs secure data products. the hcs evaluation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
1997 microchip technology inc. ds31032a-page 32-15 section 32. development tools development tools 32 32.10 related application notes this section lists application notes that are related to this section of the manual. these applica- tion notes may not be written speci?ally for the mid-range mcu family (that is they may be writ- ten for the base-line, or the high-end), but the concepts are pertinent, and could be used (with modi?ation and possible limitations). the current application notes related to microchips devel- opment tools are: title application note # air flow using fuzzy logic an600
picmicro mid-range mcu family ds31032a-page 32-16 1997 microchip technology inc. 32.11 revision history revision a this is the initial released revision of microchips development tools description.
1997 microchip technology inc. ds30133a page 33-1 m code development 33 section 33. code development highlights no material is available at this time. please monitor the microchip web site for the b revision of the code development section of the mid-range reference manual.
picmicro mid-range mcu family ds30133a-page 33-2 1997 microchip technology inc. 33.1 revision history revision a this is the initial released revision for the code development with a picmicro description.
1997 microchip technology inc. ds31034a page 34-1 m appendix 34 section 34. appendix highlights this section of the manual contains the following major topics: appendix a:i 2 c ? overview....................................................................................................34-2 appendix b:list of lcd glass manufacturers ......................................................................34-11 appendix c:device enhancement .......................................................................................34-13 appendix d:revision history................................................................................................34-1 9 i 2 c is a trademark of philips corporation.
picmicro mid-range mcu family ds31034a-page 34-2 1997 microchip technology inc. appendix a: i 2 c ? overview this section provides an overview of the inter-integrated circuit (i 2 c) bus, with subsection a.2 ?ddressing i 2 c devices discussing the operation of the ssp modules in i 2 c mode. the i 2 c bus is a two-wire serial interface. the original speci?ation, or standard mode, is for data transfers of up to 100 kbps. an enhanced speci?ation, or fast mode (400 kbps) is supported. standard and fast mode devices will operate when attached to the same bus, if the bus operates at the speed of the slower device. the i 2 c interface employs a comprehensive protocol to ensure reliable transmission and recep- tion of data. when transmitting data, one device is the ?aster which initiates transfer on the bus and generates the clock signals to permit that transfer, while the other device(s) acts as the ?lave. all portions of the slave protocol are implemented in the ssp modules hardware, except general call support, while portions of the master protocol need to be addressed in the pic16cxx software. the mssp module supports the full implementation of the i 2 c master pro- tocol, the general call address, and data transfers upto 1 mbps. the 1 mbps data transfers are supported by some of microchips serial eeproms. table a-1 de?es some of the i 2 c bus ter- minology. in the i 2 c interface protocol each device has an address. when a master wishes to initiate a data transfer, it ?st transmits the address of the device that it wishes to ?alk to. all devices ?isten to see if this is their address. within this address, a bit speci?s if the master wishes to read-from/write-to the slave device. the master and slave are always in opposite modes (trans- mitter/receiver) of operation during a data transfer. that is they can be thought of as operating in either of these two relations: master-transmitter and slave-receiver slave-transmitter and master-receiver in both cases the master generates the clock signal. the output stages of the clock (scl) and data (sda) lines must have an open-drain or open-col- lector in order to perform the wired-and function of the bus. external pull-up resistors are used to ensure a high level when no device is pulling the line down. the number of devices that may be attached to the i 2 c bus is limited only by the maximum bus loading speci?ation of 400 pf and addressing capability.
1997 microchip technology inc. ds31034a-page 34-3 appendix a appenidx 34 a.1 initiating and terminating data transfer during times of no data transfer (idle time), both the clock line (scl) and the data line (sda) are pulled high through the external pull-up resistors. the start and stop conditions determine the start and stop of data transmission. the start condition is de?ed as a high to low transition of the sda when the scl is high. the stop condition is de?ed as a low to high transition of the sda when the scl is high. figure a-1 shows the start and stop conditions. the master generates these conditions for starting and terminating data transfer. due to the de?ition of the start and stop conditions, when data is being transmitted, the sda line can only change state when the scl line is low. figure a-1: start and stop conditions table a-1: i 2 c bus terminology term description transmitter the device that sends the data to the bus. receiver the device that receives the data from the bus. master the device which initiates the transfer, generates the clock and terminates the transfer. slave the device addressed by a master. multi-master more than one master device in a system. these masters can attempt to control the bus at the same time without corrupting the message. arbitration procedure that ensures that only one of the master devices will control the bus. this ensure that the transfer data does not get corrupted. synchronization procedure where the clock signals of two or more devices are synchro- nized. sda scl s p start condition change of data allowed change of data allowed stop condition
picmicro mid-range mcu family ds31034a-page 34-4 1997 microchip technology inc. a.2 addressing i 2 c devices there are two address formats. the simplest is the 7-bit address format with a r/w bit ( figure a-2 ). the more complex is the 10-bit address with a r/w bit ( figure a-3 ). for 10-bit address format, two bytes must be transmitted. the ?st ?e bits specify this to be a 10-bit address format. the 1st transmitted byte has 5-bits which specify a 10-bit address, the two msbs of the address, and the r/w bit. the second byte is the remaining 8-bits of the address. figure a-2: 7-bit address format figure a-3: i 2 c 10-bit address format s r/w ack sent by slave slave address s r/w read/write pulse msb lsb start condition ack acknowledge s 1 1 1 1 0 a9 a8 r/w a ck a7 a6 a5 a4 a3 a2 a1 a0 a ck sent by slave = 0 for write s r/w a ck - start condition - read/write pulse - acknowledge
1997 microchip technology inc. ds31034a-page 34-5 appendix a appenidx 34 a.3 transfer acknowledge all data must be transmitted per byte, with no limit to the number of bytes transmitted per data transfer. after each byte, the slave-receiver generates an acknowledge bit (a ck ) ( figure a-4 ). when a slave-receiver doesn? acknowledge the slave address or received data, the master must abort the transfer. the slave must leave sda high so that the master can generate the stop con- dition ( figure a-1 ). figure a-4: slave-receiver acknowledge if the master is receiving the data (master-receiver), it generates an acknowledge signal for each received byte of data, except for the last byte. to signal the end of data to the slave-transmitter, the master does not generate an acknowledge (not acknowledge). the slave then releases the sda line so the master can generate the stop condition. the master can also generate the stop condition during the acknowledge pulse for valid termination of data transfer. if the slave needs to delay the transmission of the next byte, holding the scl line low will force the master into a wait state. data transfer continues when the slave releases the scl line. this allows the slave to move the received data or fetch the data it needs to transfer before allowing the clock to start. this wait state technique can also be implemented at the bit level, figure a-5 . figure a-5: data transfer wait state s data output by transmitter data output by receiver scl from master start condition clock pulse for acknowledgment not acknowledge acknowledge 1 2 8 9 12 78 9 123 89 p sda scl s start condition address r/w ack wait state data ack msb acknowledgment signal from receiver acknowledgment signal from receiver byte complete interrupt with receiver clock line held low while interrupts are serviced stop condition
picmicro mid-range mcu family ds31034a-page 34-6 1997 microchip technology inc. figure a-6 and figure a-7 show master-transmitter and master-receiver data transfer sequences. figure a-6: master-transmitter sequence figure a-7: master-receiver sequence for 7-bit address: s slave address (code + a9:a8) s r/w a1 slave address (a7:a0) a2 data a data p a master transmitter addresses a slave receiver with a 10-bit address. a/a slave address r/w a data a data a/a p '0' (write) data transferred (n bytes - acknowledge) a master transmitter addresses a slave receiver with a 7-bit address. the transfer direction is not changed. from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition (write) for 10-bit address: for 7-bit address: s slave address (code + a9:a8) s r/w a1 slave address (a7:a0) a2 a master transmitter addresses a slave receiver with a 10-bit address. slave address r/w a data a data a p '1' (read) data transferred (n bytes - acknowledge) a master reads a slave immediately after the ?st byte. from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition (write) for 10-bit address: slave address (code + a9:a8) sr r/w a3 a data a p data (read)
1997 microchip technology inc. ds31034a-page 34-7 appendix a appenidx 34 when a master does not wish to relinquish the bus (which occurs by generating a stop condi- tion), a repeated start condition (sr) must be generated. this condition is identical to the start condition (sda goes high-to-low while scl is high), but occurs after a data transfer acknowledge pulse (not the bus-free state). this allows a master to send ?ommands to the slave and then receive the requested information or to address a different slave device. this sequence is shown in figure a-8 . figure a-8: combined format combined format: s combined format - a master addresses a slave with a 10-bit address, then transmits slave address r/w a data a/a sr p (read) sr = repeated transfer direction of data and acknowledgment bits depends on r/w bits. from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition slave address (code + a9:a8) sr r/w a (write) data to this slave and reads data from this slave. slave address (a7:a0) data sr slave address (code + a9:a8) r/w a data a a p a a data a/a data (read) slave address r/w a data a/a start condition (write) direction of transfer may change at this point (read or write) (n bytes + acknowledge)
picmicro mid-range mcu family ds31034a-page 34-8 1997 microchip technology inc. a.4 multi-master the i 2 c protocol allows a system to have more than one master. this is called multi-master. when two or more masters try to transfer data at the same time, arbitration and synchronization occur. a.4.1 arbitration arbitration takes place on the sda line, while the scl line is high. the master which transmits a high when the other master transmits a low loses arbitration ( figure a-9 ), and turns off its data output stage. a master which lost arbitration can generate clock pulses until the end of the data byte where it lost arbitration. when the master devices are addressing the same device, arbitra- tion continues into the data. figure a-9: multi-master arbitration (two masters) masters that also incorporate the slave function, and have lost arbitration must immediately switch over to slave-receiver mode. this is because the winning master-transmitter may be addressing it. arbitration is not allowed between: a repeated start condition a stop condition and a data bit a repeated start condition and a stop condition care needs to be taken to ensure that these conditions do not occur. transmitter 1 loses arbitration data 1 sda data 1 data 2 sda scl
1997 microchip technology inc. ds31034a-page 34-9 appendix a appenidx 34 a.4.2 clock synchronization clock synchronization occurs after the devices have started arbitration. this is performed using a wired-and connection to the scl line. a high to low transition on the scl line causes the con- cerned devices to start counting off their low period. once a device clock has gone low, it will hold the scl line low until its scl high state is reached. the low to high transition of this clock may not change the state of the scl line, if another device clock is still within its low period. the scl line is held low by the device with the longest low period. devices with shorter low periods enter a high wait-state, until the scl line comes high. when the scl line comes high, all devices start counting off their high periods. the ?st device to complete its high period will pull the scl line low. the scl line high time is determined by the device with the shortest high period, figure a-10 . figure a-10: clock synchronization figure a-11: i 2 c bus start/stop bits timing speci?ation table a-2: i 2 c bus start/stop bits timing speci?ation microchip parameter no. sym characteristic min typ max units conditions 90 t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condi- tion setup time 400 khz mode 600 91 t hd : sta start condition 100 khz mode 4000 ns after this period the ?st clock pulse is generated hold time 400 khz mode 600 92 t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 clk 1 clk 2 scl wait state start counting high period counter reset 91 93 scl sda start condition stop condition 90 92
picmicro mid-range mcu family ds31034a-page 34-10 1997 microchip technology inc. figure a-12: i 2 c bus data timing speci?ation table a-3: i 2 c bus data timing speci?ation microchip parameter no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 m s 400 khz mode 0.6 m s 101 t low clock low time 100 khz mode 4.7 m s 400 khz mode 1.3 m s 102 t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91 t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the ?st clock pulse is generated 400 khz mode 0.6 m s 106 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107 t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92 t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109 t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode 1000 ns 110 t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmis- sion can start 400 khz mode 1.3 m s d102 cb bus capacitive loading 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the unde?ed region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement tsu;dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must out- put the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus speci?ation) before the scl line is released. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
1997 microchip technology inc. ds31034a-page 34-11 appendix b appenidx 34 appendix b: list of lcd glass manufacturers aeg-mis 3340 peachtree rd. ne suite 500 atlanta, ga 30326 tel: 404-239-0277 fax: 404-239-0383 interstate electronics corp. 1001 e. bull rd. anaheim, ca 92805 tel: 800-854-6979 fax: 714-758-4111 all shore inds inc. 1 edgewater plaza staten island, ny 10305 tel: 718-720-0018 fax: 718-720-0225 kent display systems 343 portage blvd. kent, oh 44240 tel: 330-673-8784 crystaloid 5282 hudson drive hudson, oh 44236-3769 tel: 216-655-2429 fax: 216-655-2176 lcd planar optics corporation 2100-2 artic ave. bohemia, ny 11716 tel: 516-567-4100 fax: 516-567-8516 dci inc. 14812 w. 117th st. olathe, ks 66062-9304 tel: 913-782-5672 fax: 913-782-5766 lxd inc. 7650 first place oakwood village, oh 44146 tel: 216-786-8700 fax: 216-786-8711 excel technology international corporation unit 5, bldg. 4, stryker lane belle mead, nj 08502 tel: 908-874-4747 fax: 908-874-3278 nippon sheet glass tomen america inc. 1285 avenue of the americas new york, ny 10019 tel: 212-397-4600 fax: 212-397-3351 f-p electronics/mark iv industries 6030 ambler drive mississauga, on canada l4w 2pi tel: 905-624-3020 fax: 905-238-3141 optrex america 44160 plymouth oaks blvd. plymouth, mi 48170 tel: 313-416-8500 fax: 313-416-8520 hunter components 24800 chagrin blvd, suite 101 cleveland, oh 44122 tel: 216-831-1464 fax: 216-831-1463 phillips components lcd business unit 1273 lyons road, bldg g dayton, oh 45459 tel: 573-436-9500 fax: 573-436-2230
picmicro mid-range mcu family ds31034a-page 34-12 1997 microchip technology inc. satori electric 23717 hawthorne blvd. 3rd floor torrance, ca 90505 tel: 310-214-1791 fax: 310-214-1721 varitronix limited inc. 3250 wilshire blvd. suite 1901 los angeles, ca 90010 tel: 213-738-8700 fax: 213-738-5340 seiko instruments usa inc. electronic components division 2990 west lomita blvd. torrance, ca 90505 tel: 213-517-7770 213-517-8113 fax: 213-517-7792 varitronix limited inc. 4/f, liven house 61-63 king yip street kwun tong, kowloon hong kong tel: 852 2389 4317 fax: 852 2343 9555 standish international european technical center am ba?mstuck ii 65520 bad camberg/erbach germany tel: 011 49 6434 3324 fax: 011 49 6434 377238 varitronix (france) s.a.r.l. 13/15 chemin de chilly 91160 champlain france tel:(33) 1 69 09 7070 fax:(33) 1 69 09 0535 standish lcd w7514 highway v lake mills, wi 53551 tel: 414-648-1000 fax: 414-648-1001 varitronix italia, s.r.l. via bruno buozzi 90 20099 sesto san giovanni milano, italy tel:(39) 2 2622 2744 fax:(39) 2 2622 2745 truly semiconductors ltd. (usa) 2620 concord ave. suite 106 alhambra, ca 91803 tel: 818-284-3033 fax: 818-284-6026 varitronix (uk) limited display house, 3 milbanke court milbanke way, bracknell berkshire rg12 1br united kingdom tel:(44) 1344 30377 fax(44) 1344 300099 truly semiconductor ltd. 2/f, chung shun knitting center 1-3 wing yip street, kwai chung, n.t., hong kong tel: 852 2487 9803 fax: 852 2480 0126 varitronix (canada) limited 18 crown steel drive, suite 101 markham, ontario canada l3r 9x8 tel:(905) 415-0023 fax:(905) 415-0094 vikay america inc . 195 w. main st. avon, ct 06001-3685 tel: 860-678-7600 fax: 860-678-7625
1997 microchip technology inc. ds31034a-page 34-13 appendix c appenidx 34 appendix c: device enhancement as the midrange architecture matured, certain modules and features have been enhanced. they are: 1. the data memory map 2. the ssp module 3. the a/d module 4. brown-out reset added to the core 5. mclr filter 6. usart 7. device oscillator the following subsections discuss the implementations of these enhancements. c.1 data memory map the data memory map shows the location of the special function registers (sfrs) and the general purpose registers (gprs). sfrs provide controls and give status on the operation of the device, while the gprs are the general purpose ram. figure c-1 show the various memory maps that have been implemented in the midrange family. memory map a was implemented on the ?st midrange devices. they were 18/20-pin devices that had limited peripheral features. when the product roadmap dictated the requirement for devices with increased i/o, and a richer peripheral set, memory map b was implemented. mem- ory map c is actually a subset of memory map b , but context saving (due to an interrupt) requires additional software overhead. this is because there is no gpr in bank1. to minimize the context saving software, memory map d was de?ed. a common ram memory map will be used for all future devices. see the ?emory organization section for use and implementation of the midrange picmicros memory. figure c-1: various data memory maps bank0 bank1 sfr sfr gpr (1) bank0 bank1 sfr sfr gpr (2) bank0 bank1 sfr sfr gpr gpr 80h 9fh a0h ffh 00h 1fh 20h 7fh 80h 9fh a0h ffh 80h 8bh 8ch ffh 00h 1fh 20h 7fh 00h 0bh 0ch 7fh bank0 bank1 sfr sfr gpr gpr 80h 9fh a0h ffh 00h 1fh 20h 7fh bank2 bank3 sfr sfr gpr gpr 180h 19fh 1a0h 1ffh 100h 11fh 120h 17fh (1) (1) (1) a b c d (3) note 1: mapped in bank0. 2: unimplemented, read as '0'. 3: some devices have some gpr located in the sfr region. f0h 70h 1f0h 170h
picmicro mid-range mcu family ds31034a-page 34-14 1997 microchip technology inc. c.2 ssp (synchronous serial port) module the ssp module has two modes of operation; spi (serial peripheral interface) ? 2 c (inter-integrated circuit). there are now three different ssp modules that exist in microchips design library. the ?st ssp module (now called basic ssp) implements two of the four spi modes, and the i 2 c module in slave mode. the second ssp module (called ssp) implements all four spi modes, and the i 2 c module in slave mode. the third ssp module (called master ssp) implements all four spi modes, and the i 2 c module in master and slave modes. table c-1 shows the devices that have an ssp module and denotes which version is implemented. as new devices are introduced, either the ssp module or master ssp module will be implemented (that is, the basic ssp mod- ule is being phased out). only select devices will be introduced with the master ssp module due to the size (silicon area => cost) difference in relation to the ssp module. if your application requires i 2 c master mode, then you should also check into microchips high-end family, pic17cxxx. table c-1: devices with an ssp module device synchronous serial port version ssp basic ssp master ssp (1) pic16c62 yes pic16c62a yes pic16cr62 yes pic16c63 yes pic16cr63 yes pic16c64 yes pic16c64a yes pic16cr64 yes pic16c65 yes pic16c65a yes pic16cr65 yes pic16c66 yes pic16c67 yes pic16c72 yes pic16cr72 yes pic16c73 yes pic16c73a yes pic16c74 yes pic16c74a yes pic16c76 yes pic16c77 yes pic16c923 yes pic16c924 yes future devices with ssp module see device data sheet see device data sheet note 1: at present no midrange devices are available with the master ssp module. please refer to microchips web site or bbs for release of product briefs. you will be able to ?d out the details of features for new devices. this module is available on microchips high end family (pic17cxxx). please refer to microchips web site, bbs, regional sales of?e, or factory repre- sentatives.
1997 microchip technology inc. ds31034a-page 34-15 appendix c appenidx 34 c.3 a/d (analog-to-digital) module there now exists several different versions of the a/d module in microchips design library. the ?st a/d module (now called basic 8-bit a/d) is an 8-bit a/d with four input channels. the second a/d module (called 8-bit a/d) is an 8-bit a/d with up to 8 input channels. the third a/d module (called 10-bit a/d) is a 10-bit a/d with up to16 input channels implemented. table c-2 shows which devices have an a/d module, and the version implemented. as new devices are intro- duced, either the 8-bit a/d module or 10-bit a/d module will be implemented (that is the basic 8-bit a/d module is being phased out). if your application requires the 10-bit a/d, you should refer to microchips high end family (pic17cxxx). this family currently has some devices that have this module implemented. table c-2: devices with a/d modules device 8-bit a/d basic 8-bit a/d 10-bit a/d (1) slope a/d pic16c710 yes pic16c71 yes pic16c711 yes pic16c715 yes pic16c72 yes pic16cr72 yes pic16c73 yes pic16c73a yes pic16c74 yes pic16c74a yes pic16c76 yes pic16c77 yes pic16c924 yes pic14c000 yes future devices with a/d module see device data sheet see device data sheet see device data sheet see device data sheet note 1: at present no midrange devices are available with the 10-bit a/d module. please refer to microchips web site or bbs for release of product briefs. you will be able to ?d out the details of features for new devices. this module is available on microchips high end family (pic17cxxx). please refer to microchips web site, bbs, regional sales of?e, or factory repre- sentatives.
picmicro mid-range mcu family ds31034a-page 34-16 1997 microchip technology inc. c.4 brown-out reset an internal brown-out reset (bor) circuit was added as a special feature. this circuit will be added to most new devices. the exception will be for devices whose target market will require normal operation below the bor trip point (handheld battery applications). table c-3 shows the devices that evolved into having the bor circuitry. table c-3: devices that were revised to include on-chip brown-out reset c.5 comparator if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif interrupt ?g bit may not get set. base device no brown-out reset subsequent device with brown-out reset pic16c62 pic16c62a pic16c64 pic16c64a pic16c65 pic16c65a pic16c71 pic16c711 pic16c73 pic16c73a pic16c74 pic16c74a
1997 microchip technology inc. ds31034a-page 34-17 appendix c appenidx 34 c.6 mclr filter the master clear (mclr ) logic has had a ?ter added. this ?ter ignores short duration (glitch) low level pulses on the master clear pin. table c-4 shows whether the device has the master clear ?ter. table c-4: devices with master clear filter device master clear no filter (fast reset) filter pic16c61 yes pic16c62 yes pic16c62a yes pic16cr62 yes pic16c63 yes pic16cr63 yes pic16c64 yes pic16c64a yes pic16cr64 yes pic16c65 yes pic16c65a yes pic16cr65 yes pic16c66 yes pic16c67 yes pic16c620 yes pic16c621 yes pic16c622 yes pic16c710 yes pic16c71 yes pic16c711 yes pic16c715 yes pic16c72 yes pic16cr72 yes pic16c73 yes pic16c73a yes pic16c74 yes pic16c74a yes pic16c76 yes pic16c77 yes pic16c83 yes pic16c84 yes pic16f83 yes pic16f84 yes pic16c923 yes pic16c924 yes all new devices yes
picmicro mid-range mcu family ds31034a-page 34-18 1997 microchip technology inc. c.7 usart the original usart/sci module that was offered on midrange devices speci?d a ?igh speed mode (when the brgh control bit is set). due to the design of the sampling circuitry, the opera- tion of this mode was not as robust as desired. the sampling circuitry has been changed so that operation now meets microchips requirements. the difference in the sampling is described in the ?sart section. table c-5 shows which devices use the new and old sampling logic. table c-5: usart/sci sampling logic c.8 device oscillator a new mode has been added into the device oscillator which allows the device to operate from an internal rc. this is speci?d at time of device programming (con?uration word). this mode will be included on many future devices. see the device data sheets con?uration word to deter- mine if the device supports this mode. c.9 parallel slave port the control pins have changed from level sensitive to edge sensitive. table c-6: parallel slave port change sensitivity device sampling logic old new pic16c63 yes pic16cr63 yes pic16c65 yes pic16c65a yes pic16cr65 yes pic16c66 yes pic16c67 yes pic16c73 yes pic16c73a yes pic16c74 yes pic16c74a yes pic16c76 yes pic16c77 yes new devices with usart/sci module ?es device sensitivity level edge pic16c64 yes pic16c64a yes pic16c65 yes pic16c65a yes pic16c67 yes pic16c74 yes pic16c74a yes pic16c77 yes new devices with parallel slave port ?es
1997 microchip technology inc. ds31034a-page 34-19 appendix d appenidx 34 appendix d: revision history revision a this is the initial released revision of the reference guide appendix.
picmicro mid-range mcu family ds31034a-page 34-20 1997 microchip technology inc.
1997 microchip technology inc. ds31035a page 35-1 m glossary 35 section 35. glossary a a/d see analog to digital. acquisition time (t acq ) this is related to analog to digital (a/d) converters. this is the time that the a/ds holding capac- itor acquires the analog input voltage level connected to it. when the go bit is set, the analog input is disconnected from the holding capacitor and the a/d conversion is started. alu arithmetical logical unit. device logic that is responsible for the mathematical (add, subtract, ...), logical (and, or, ...), and shifting operations. analog to digital (a/d) the conversion of an analog input voltage to a ratiometric digital equivalent value. assembly language a symbolic language that describes the binary machine code in a readable form.
picmicro mid-range mcu family ds31035a-page 35-2 1997 microchip technology inc. b bank this is a method of addressing data memory. since midrange devices have 7-bits for direct addressing, instructions can address up to 128 bytes (including special function registers). to allow more data memory to be present on a device, data memory is partitioned into contiguous banks of 128 bytes each. to select the desired bank, the bank selection bits (rp1:rp0) need to be appropriately con?ured. since there are presently 2 bank selection bits, 4 banks can be implemented. baud generally how the communication speed of serial ports is described. equivalent to bits per sec- ond (bps). bcd see binary coded decimal. binary coded decimal (bcd) each 4-bit nibble expresses a digit from 0-9. usually two digits are packed to a byte giving a range of 0 - 99. bor see brown-out reset. brown-out a condition where the supply voltage of the device temporarily falls below the speci?d minimum operation point. this can occur when a load is switched on and causes the system/device voltage to drop. brown-out reset (bor) circuitry which will force the device to the reset state if the (device) voltage falls below a speci?d voltage level. some devices have an internal bor circuit, while other devices would require an external circuit to be created. bus width this is the number of bits of information that the bus carries. for the data memory, the bus width is 8-bits. for the midrange devices the program memory bus width is 14-bits.
1997 microchip technology inc. ds31035a-page 35-3 glossary glossary 35 c capture a function of the ccp module in which the value of a timer/counter is ?aptured? into a holding register, when a predetermined event occurs. ccp capture, compare, pulse width modulation (pwm). this module can be con?ured to operate as an input capture, or a timer compare, or a pwm output. common ram this is a region of the data memory ram that is the same ram location across all banks. this common ram maybe implemented between addresses 70h -7fh (inclusive). this common area is useful for the saving of required variables during context switching (such as during an inter- rupt). compare a function of the ccp module in which the device will perform an action when a timers register value matches the value in the compare register. compare register a 16-bit register that contains a value that is compared to the 16-bit tmr1 register. the compare function triggers when the counter matches the contents of the compare register. capture register a 16-bit register that gets loaded with the value of the 16-bit tmr1 register when a capture event occurs. con?uration word this is a location that speci?s the characteristics that the device will have for operation (such as oscillator mode, wdt enable, start-up timer enables). these characteristics can be speci?d at time of device programming. for eprom memory devices, as long as the bit is a '1', it may at a later time be programmed as a '0'. the device must be erased for a '0' to be returned to a '1'. conversion time (tconv) this is related to analog to digital (a/d) converters. this is the time that the a/d converter requires to convert the analog voltage level on the holding capacitor to a digital value. cpu central processing unit. decodes the instructions, and determines the operands that are needed and the operations that need to be done. arithmetic, logical, or shift operations will be passed to the alu.
picmicro mid-range mcu family ds31035a-page 35-4 1997 microchip technology inc. d d/a see digital to analog dac digital to analog converter data bus the bus which is used to transfer data to and from the data memory. data eeprom data electrically erasable programmable read only memory. this memory has the capability to be programmed and re-programmed by the cpu to ensure that in the case of a power loss critical values/variables are retained in the non-volatile memory. data memory the memory that is on the data bus. this memory is volatile (sram) and contains both the spe- cial function registers and general purpose registers. direct addressing when the data memory address is contained in the instruction. the execution of this type of instruction will always access the data at the embedded address. digital to analog e eeprom electrically erasable programmable read only memory. this memory has the capability to be programmed and erased in-circuit. eprom electrically programmable read only memory. this memory has the capability to be pro- grammed in-circuit. erasing requires that the program memory be exposed to uv light. extrc external resistor-capacitor (rc). some devices have a device oscillator option that allows the clock to come from an external rc. this is the same as rc mode on some devices. f flash memory this memory has the capability to be programmed and erased in-circuit. program memory tech- nology that is almost functionally equivalent to program eeprom memory. fosc frequency of the device oscillator.
1997 microchip technology inc. ds31035a-page 35-5 glossary glossary 35 g gio general input/output gpio general purpose input/output gpr general purpose register (ram). a portion of the data memory that can be used to store the programs dynamic variables. h harvard architecture in this architecture the program memory and data memory buses are separated. this allows concurrent accesses to data memory and program memory, which increases the performance of the device. holding capacitor this is a capacitor in the analog to digital (a/d) module which ?olds to analog input level once the conversion is started. during acquisition, the holding capacitor is charged/discharged by the voltage level on the analog input pin. once the conversion is started, the holding capacitor is dis- connected from the analog input and ?olds this voltage for the a/d conversion. hs high speed. one of the device oscillator modes. the oscillator circuit is tuned to support the high frequency operation. used for operation from 4 mhz to 20 mhz.
picmicro mid-range mcu family ds31035a-page 35-6 1997 microchip technology inc. i i 2 c inter-integrated circuit. this is a two wire communication interface. this feature is one of the modes of the ssp module. indirect addressing when the data memory address is not contained in the instruction. the instruction operates on the indf address, which causes the data memory address to be the value in the fsr register. the execution of the instruction will always access the data at the address pointed to by the fsr register. instruction bus the bus which is used to transfer instruction words from the program memory to the cpu. instruction fetch due to the harvard architecture, when one instruction is to be executed, the next location in pro- gram memory is ?etched and ready to be decoded as soon as the currently executing instruction is completed. instruction cycle the events for an instruction to execute. there are four events which can generally be described as: decode, read, execute, and write. not all events will be done by all instructions. to see the operations during the instruction cycle, please look in the description of each instruction. four external clocks (tosc) make one instruction cycle (t cy ). interrupt a signal to the cpu that causes the program ?w to be forced to the interrupt vector address (04h in program memory). before the program ?w is changed, the contents of the program counter (pc) are forced onto the hardware stack, so that program execution may return to the interrupted point. intrc internal resistor-capacitor (rc). some devices have a device oscillator option that allows the clock to come from an internal rc.
1997 microchip technology inc. ds31035a-page 35-7 glossary glossary 35 l lcd liquid crystal display. useful for giving visual status of a system. this may require the speci?a- tion of custom lcd glass. led light emitting diode. useful for giving visual status of a system. literal this is a constant value that is embedded in an instruction word. long word instruction an instruction word that embeds all the required information (opcode and data) into a single word. this ensures that every instruction is accessed and executed in a single instruction cycle. lp one of the device oscillator modes. used for low frequency operation which allows the oscillator to be tuned for low power consumption. operation is up to 200 khz. lsb least signi?ant bit. lsb least signi?ant byte. m machine cycle this is a concept where the device clock is divided down to a unit time. for picmicros this unit time is 4 times the device oscillator (4t osc ), also known as t cy . msb most signi?ant bit. msb most signi?ant byte.
picmicro mid-range mcu family ds31035a-page 35-8 1997 microchip technology inc. n non-return to zero two level encoding used to transmit data over a communications medium. a bit value of '1' indi- cates a high voltage signal. a bit value of '0' indicates a low voltage signal. the data line defaults to a high level. nrz see non-return to zero o opcode the portion of the 14-bit instruction word that speci?s the operation that needs to occur. the opcode is of variable length depending on the instruction that needs to be executed. the opcode varies from 4-bits to x-bits. the remainder of the instruction word contains program or data mem- ory information. oscillator start-up timer (ost) this timer counts 1024 crystal/resonator oscillator clock before releasing the internal reset sig- nal. ost see oscillator start-up timer.
1997 microchip technology inc. ds31035a-page 35-9 glossary glossary 35 p pages method of addressing the program memory. midrange devices have 11-bit addressing for call and goto instructions, which gives these instructions a 2-kword reach. to allow more program memory to be present on a device, program memory is partitioned into contiguous pages, where each page is 2-kwords. to select the desired page, the page selection bits (pclatch<5:4>) need to be appropriately con?ured. since there are presently 2 page selection bits, 4 pages can be implemented. parallel slave port (psp) a parallel communication port which is used to interface to a microprocessors 8-bit data bus. pop a termed used to refer to the action of restoring information from a stack (software and/or hard- ware). see push. postscaler a circuit that slows the rate of the interrupt generation (or wdt reset) from a counter/timer by dividing it down. power-on reset por) circuitry which determines if the device voltage rose from a powered down level (0v). if the device voltage is rising from ground, a device reset occurs and the pwrt is started. power-up timer (pwrt) a timer which holds the internal reset signal low for a timed delay to allow the device voltage to reach the valid operating voltage range. once the timer times out, the ost circuitry is enabled (for all crystal/resonator device oscillator modes). prescaler a circuit that slows the rate of a clocking source to a counter/timer. program bus the bus which is used to transfer instruction words form the program memory to the cpu. program counter a register which speci?s the address in program memory that is the next instruction to execute. program memory any memory that is one the program memory bus. static variables may be contained in program memory (such as tables). psp see parallel slave port. pulse width modulation (pwm) a serial signal in which the information is contained in the width of a (high) pulse of a constant frequency signal. a pwm output, from the ccp module, of the same duty cycle requires no soft- ware overhead. push a termed used to refer to the action of saving information onto a stack (software and/or hard- ware). see pop. pwm pulse width modulation.
picmicro mid-range mcu family ds31035a-page 35-10 1997 microchip technology inc. q q-cycles this is the same as a device oscillator cycle. there are 4 q-cycles for each instruction cycle. r rc resistor-capacitor. the default con?uration for the device oscillator. this allows a r eal- c heap implementation for the device clock source. this clock source does not supply an accurate time-base. operation to 4 mhz is supported. (see extrc). read-modify-write this is where a register is read, then modi?d, and then written back to the original register. this may be done in one instruction cycle or multiple instruction cycles. register file this is the data memory. contains the sfrs and gprs. rom read only memory. memory that is ?ed and cannot be modi?d.
1997 microchip technology inc. ds31035a-page 35-11 glossary glossary 35 s sampling time sampling time is the complete time to get an a/d result. it includes the acquisition time and the conversion time. serial peripheral interface (spi) this is one of the modes of the ssp module. this is typically a 3-wire interface, with a data out line, a data in line, and a clock line. since the clock is present, this is a synchronous interface. sfr special function register. these registers contain the control bits and status information for the device. single cycle instruction an instruction that executes in a ?ingle machine cycle (t cy ). sleep this is the low power mode of the device, where the devices oscillator is disabled.this reduces the current the device consumes. certain peripherals may be placed into modes where they con- tinue to operate. special function registers (sfr) these registers contain the control bits and status information for the device. spi see serial peripheral interface. stack a portion of the cpu which retains the return address for program execution. the stack gets loaded with the value in the program counter when a call instruction is executed or an interrupt occurs.
picmicro mid-range mcu family ds31035a-page 35-12 1997 microchip technology inc. t t ad in the a/d converter, the time for a single bit of the analog voltage to be converted to a digital value. t cy the time for an instruction to complete. this time is equal to fosc/4 and is divided into four q-cycles. tosc the time for the device oscillator to do a single period. u usart universal synchronous asynchronous receiver transmitter. this module can either operate as a full duplex asynchronous communications port, or a half duplex synchronous communications port. when operating in the asynchronous mode, this can be interfaced to a pcs serial port.
1997 microchip technology inc. ds31035a-page 35-13 glossary glossary 35 v voltage reference (v ref ) a voltage level that can be used as a reference point for a/d conversions (a vdd and a vss ) or the trip point for comparators. von neumann architecture in this architecture the program memory and data memory are contained in the same area. this means that accesses to the program memory and data memory must occur sequentially, which affects the performance of the device. w w register see working register. watchdog timer (wdt) used to increase the robustness of a design by recovering from software ?ws that were not expected in the design of the product or other system related issues. the watchdog timer causes a reset if it is not cleared prior to over?w. the clock source for a picmicro is an on-chip rc oscillator which enhances system reliability. wdt watchdog timer. working register (w) can also be thought of as the accumulator of the device. also used as an operand in conjunction with the alu during two operand instructions. x xt one of the device oscillator modes. used for operation from 100 khz to 4 mhz.
picmicro mid-range mcu family ds31035a-page 35-14 1997 microchip technology inc. 35.1 revision history revision a this is the initial released revision of the glossary.
? 2002 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq , microid, mplab, pic, picmicro, picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified. note the following details of the code protection feature on picmicro ? mcus. the picmicro family meets the specifications contained in the microchip data sheet. microchip believes that its family of picmicro microcontrollers is one of the most secure products of its kind on the market to day, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowl - edge, require using the picmicro microcontroller in a manner outside the operating specifications contained in the data sheet. the person doing so may be engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ? unbreakable ? . code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our product. if you have any further questions about this matter, please contact the local sales office nearest to you.
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